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91. 发明授权

US07608513B2 Dual gate LDMOS device fabrication methods 失效
标题翻译：双栅LDMOS器件制造方法
公开(公告)号：US07608513B2
公开(公告)日：2009-10-27
申请号：US11626928
申请日：2007-01-25
申请人： Hongning Yang , Veronique C. Macary , Won Gi Min , Jiang-Kai Zuo
发明人： Hongning Yang , Veronique C. Macary , Won Gi Min , Jiang-Kai Zuo
IPC分类号： H01L21/336
CPC分类号： H01L29/7835 , H01L21/26586 , H01L29/0692 , H01L29/0847 , H01L29/1045 , H01L29/1083 , H01L29/402 , H01L29/66537 , H01L29/66659 , H01L29/7831
摘要： An N-channel device (40, 60) is described having a lightly doped substrate (42, 42′) in which adjacent or spaced-apart P (46, 46′) and N (44) wells are provided. A lateral isolation wall (76) surrounds at least a portion of the substrate (42, 42′) and is spaced apart from the wells (46, 46′, 44). A first gate (G1) (56) overlies the P (46) well or the substrate (42′) between the wells (46′, 44) or partly both. A second gate (G2) (66), spaced apart from G1 (56), overlies the N-well (44). A body contact (74) to the substrate (42, 42′) is spaced apart from the isolation wall (76) by a first distance (745) within the space charge region of the substrate (42, 42′) to isolation wall (76) PN junction. When the body contact (74) is connected to G2 (66), a predetermined static bias Vg2 is provided to G2 (66) depending upon the isolation wall bias (Vbias) and the first distance (745). The resulting device (40, 60) operates at higher voltage with lower Rdson and less HCI.
摘要翻译：描述了具有轻掺杂衬底（42,42'）的N沟道器件（40,60），其中提供相邻或间隔开的P（46,46'）和N（44）阱。横向隔离壁（76）围绕衬底（42,42'）的至少一部分并且与井（46,46'，44）间隔开。第一栅极（G1）（56）覆盖在孔（46'，44）之间的P（46）阱或衬底（42'）上，或者部分覆盖两者。与G1（56）间隔开的第二门（G2）（66）覆盖在N阱（44）上。衬底（42,42'）的主体接触件（74）与隔离壁（76）隔开第一距离（745），在衬底（42,42'）的空间电荷区域内与隔离壁（ 76）PN结。当身体接触（74）连接到G2（66）时，根据隔离壁偏压（Vbias）和第一距离（745），将预定的静态偏压Vg2提供给G2（66）。所得到的装置（40,60）以更低的Rdson和更少的HCI工作在更高的电压。

92. 发明授权

US07393752B2 Semiconductor devices and method of fabrication 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：US07393752B2
公开(公告)日：2008-07-01
申请号：US11189587
申请日：2005-07-25
申请人： Hongning Yang , Jiang-Kai Zuo
发明人： Hongning Yang , Jiang-Kai Zuo
IPC分类号： H01L21/336
CPC分类号： H01L29/7835 , H01L21/26586 , H01L21/823807 , H01L21/823892 , H01L29/1045 , H01L29/1083 , H01L29/66659
摘要： A semiconductor having an ˜5V operational range, including a drain side enhanced gate-overlapped LDD (GOLD) and a source side halo implant region and well implant. A method in accordance with an embodiment of the invention comprises forming a gate electrode overlying a substrate and a very lightly doped epitaxial layer formed on the substrate. A high energy implant region forms a well in a source side of the lightly doped epitaxial layer. A self-aligned halo implant region is formed on a source side of the device and within the high energy well implant. An implant region on a drain side of the lightly doped epitaxial layer forms the gate overlapped LDD (GOLD). A doped region within the halo implant region forms a source. A doped region within the gate overlapped LDD (GOLD) forms a drain. The structure enables the manufacture of a deep submicron (
摘要翻译：具有〜5V工作范围的半导体，包括漏极侧增强的栅极重叠LDD（GOLD）和源极晕圈注入区域以及阱注入。根据本发明的实施例的方法包括形成覆盖衬底的栅电极和形成在衬底上的非常轻掺杂的外延层。高能注入区域在轻掺杂外延层的源极侧形成阱。自对准的晕圈植入区域形成在器件的源极侧和高能阱植入体内。在轻掺杂外延层的漏极侧的注入区域形成栅极重叠的LDD（GOLD）。卤素注入区域内的掺杂区域形成源。栅极重叠LDD（GOLD）内的掺杂区域形成漏极。该结构使得能够使用现有的0.13mum工艺流程制造深亚微米（<0.3mum）的功率MOSFET，而无需额外的掩模和处理步骤。

93. 发明授权

US09281375B2 Methods of producing bipolar transistors having emitter-base junctions of varying depths and/or doping concentrations 有权
标题翻译：制造具有不同深度和/或掺杂浓度的发射极 - 基结的双极型晶体管的方法
公开(公告)号：US09281375B2
公开(公告)日：2016-03-08
申请号：US14313114
申请日：2014-06-24
申请人： Xin Lin , Bernhard H. Grote , Jiang-Kai Zuo
发明人： Xin Lin , Bernhard H. Grote , Jiang-Kai Zuo
IPC分类号： H01L21/331 , H01L29/73 , H01L29/66 , H01L21/8222 , H01L21/8249 , H01L29/735 , H01L29/70
CPC分类号： H01L29/6625 , H01L21/8222 , H01L21/8249 , H01L29/705 , H01L29/7317 , H01L29/735
摘要： Methods for producing bipolar transistors are provided. In one embodiment, the method includes producing a bipolar transistor including first and second connected emitter-base (EB) junctions of varying different depths. A buried layer (BL) collector is further produced to have a third depth greater than the depths of the EB junctions. The emitters and bases corresponding to the different EB junctions are provided during a chain implant. An isolation region may overlie the second EB junction location. The BL collector is laterally spaced from the first EB junction by a variable amount to facilitate adjustment of the transistor properties. The BL collector may or may not underlie at least a portion of the second EB junction. Regions of opposite conductivity type overlie and underlie the BL collector to preserve breakdown voltage. The transistor can be readily “tuned” by mask adjustments alone to meet various device requirements.
摘要翻译：提供了制造双极晶体管的方法。在一个实施例中，该方法包括产生包括变化不同深度的第一和第二连接的发射极基极（EB）结的双极晶体管。进一步制造掩埋层（BL）集电体以具有大于EB结的深度的第三深度。在链植入期间提供对应于不同EB结的发射器和基座。隔离区域可以覆盖第二EB结点位置。 BL收集器与第一EB结横向间隔可变量以便于调整晶体管特性。 BL收集器可以或可以不位于第二EB结的至少一部分的下面。相反导电类型的区域叠加在BL集电极之下，以保持击穿电压。晶体管可以通过单独的掩模调节容易地“调谐”以满足各种器件要求。

94. 发明授权

US09136327B1 Deep trench isolation structures and systems and methods including the same 有权
标题翻译：深沟槽隔离结构及其系统和方法包括相同
公开(公告)号：US09136327B1
公开(公告)日：2015-09-15
申请号：US14464901
申请日：2014-08-21
申请人： Xu Cheng , Daniel J. Blomberg , Jiang-Kai Zuo
发明人： Xu Cheng , Daniel J. Blomberg , Jiang-Kai Zuo
IPC分类号： H01L21/336 , H01L29/06 , H01L29/36 , H01L21/762 , H01L21/8234 , H01L27/02
CPC分类号： H01L29/0649 , H01L21/76224 , H01L21/823481 , H01L27/0203 , H01L27/0207 , H01L29/36
摘要： Deep trench isolation structures and systems and methods including the same are disclosed herein. The systems include a semiconductor device. The semiconductor device includes a semiconductor body, a device region, and the deep trench isolation structure. The deep trench isolation structure is configured to electrically isolate the device region from other device regions that extend within the semiconductor body. The deep trench isolation structure includes an isolation trench, a dielectric material that extends within the isolation trench, a first semiconducting region, and a second semiconducting region. The methods include methods of manufacturing a semiconductor device that includes the disclosed deep trench isolation structures. The methods also include methods of operating an integrated circuit device that includes a plurality of semiconductor devices that include the disclosed deep trench isolation structures.
摘要翻译：深沟槽隔离结构及其系统和方法在此公开。该系统包括半导体器件。半导体器件包括半导体本体，器件区域和深沟槽隔离结构。深沟槽隔离结构被配置为将器件区域与在半导体本体内延伸的其它器件区域电隔离。深沟槽隔离结构包括隔离沟槽，在隔离沟槽内延伸的介电材料，第一半导体区域和第二半导体区域。该方法包括制造包括所公开的深沟槽隔离结构的半导体器件的方法。所述方法还包括操作集成电路器件的方法，所述集成电路器件包括包括所公开的深沟槽隔离结构的多个半导体器件。

95. 发明授权

US09099489B2 Bipolar transistor with high breakdown voltage 有权
标题翻译：具有高击穿电压的双极晶体管
公开(公告)号：US09099489B2
公开(公告)日：2015-08-04
申请号：US13545746
申请日：2012-07-10
申请人： Xin Lin , Daniel J. Blomberg , Jiang-Kai Zuo
发明人： Xin Lin , Daniel J. Blomberg , Jiang-Kai Zuo
IPC分类号： H01L29/02 , H01L21/02 , H01L29/66 , H01L29/732 , H01L29/06 , H01L29/417 , H01L29/08
CPC分类号： H01L29/66272 , H01L29/0607 , H01L29/063 , H01L29/0808 , H01L29/0821 , H01L29/41708 , H01L29/732
摘要： A higher breakdown voltage transistor has separated emitter, base contact, and collector contact. Underlying the emitter and the base contact are, respectively, first and second base portions of a first conductivity type. Underlying and coupled to the collector contact is a collector region of a second, opposite, conductivity type, having a central portion extending laterally toward, underneath, or beyond the base contact and separated therefrom by the second base portion. A floating collector region of the same conductivity type as the collector region underlies and is separated from the emitter by the first base portion. The collector and floating collector regions are separated by a part of the semiconductor (SC) region in which the base is formed. A further part of the SC region in which the base is formed, laterally bounds or encloses the collector region.
摘要翻译：较高的击穿电压晶体管具有分离的发射极，基极接触和集电极接触。分别位于发射极和基极接触面之下的第一和第二基极部分是第一导电类型。底部并且耦合到集电极触点的是第二相对导电类型的集电极区域，其具有横向朝向，在下面或超过基部触点延伸并且由第二基部分离的中心部分。与集电极区域相同的导电类型的浮置集电极区域位于第一基底部分的下方并与发射极分离。集电极和集电极区域由形成有基极的半导体（SC）区域的一部分分开。 SC区域的另一部分，其中形成基底，横向界定或围绕收集器区域。

96. 发明申请

US20150104920A1 SEMICONDUCTOR DEVICE AND RELATED FABRICATION METHODS 有权
标题翻译：半导体器件及相关制造方法
公开(公告)号：US20150104920A1
公开(公告)日：2015-04-16
申请号：US14575204
申请日：2014-12-18
申请人： Xin Lin , Daniel J. Blomberg , Jiang-Kai Zuo
发明人： Xin Lin , Daniel J. Blomberg , Jiang-Kai Zuo
IPC分类号： H01L29/66 , H01L21/265
CPC分类号： H01L29/6625 , H01L21/265 , H01L29/0649 , H01L29/36 , H01L29/66234 , H01L29/66272 , H01L29/73 , H01L29/732 , H01L29/735
摘要： Semiconductor device structures and related fabrication methods are provided. An exemplary semiconductor device structure includes a collector region of semiconductor material having a first conductivity type, a base region of semiconductor material within the collector region, the base region having a second conductivity type opposite the first conductivity type, and a doped region of semiconductor material having the second conductivity type, wherein the doped region is electrically connected to the base region and the collector region resides between the base region and the doped region. In exemplary embodiments, the dopant concentration of the doped region is greater than a dopant concentration of the collector region to deplete the collector region as the electrical potential of the base region exceeds that of the collector region.
摘要翻译：提供半导体器件结构和相关的制造方法。示例性的半导体器件结构包括具有第一导电类型的半导体材料的集电极区域，在集电极区域内的半导体材料的基极区域，具有与第一导电类型相反的第二导电类型的基极区域和半导体材料的掺杂区域具有第二导电类型，其中所述掺杂区域电连接到所述基极区域，并且所述集电极区域位于所述基极区域和所述掺杂区域之间。在示例性实施例中，掺杂区域的掺杂剂浓度大于集电极区域的掺杂剂浓度以消耗集电极区域，因为基极区域的电位超过集电极区域的电位。

97. 发明授权

US08946041B2 Methods for forming high gain tunable bipolar transistors 有权
标题翻译：用于形成高增益可调双极晶体管的方法
公开(公告)号：US08946041B2
公开(公告)日：2015-02-03
申请号：US13534971
申请日：2012-06-27
申请人： Xin Lin , Daniel J. Blomberg , Jiang-Kai Zuo
发明人： Xin Lin , Daniel J. Blomberg , Jiang-Kai Zuo
IPC分类号： H01L21/331 , H01L29/66 , H01L29/08 , H01L29/10 , H01L29/732 , H01L21/8249 , H01L27/06
CPC分类号： H01L29/66272 , H01L21/8249 , H01L27/0623 , H01L29/0804 , H01L29/1004 , H01L29/7322
摘要： Embodiments for forming improved bipolar transistors are provided, manufacturable by a CMOS IC process. The improved transistor comprises an emitter having first and second portions of different depths, a base underlying the emitter having a central portion of a first base width underlying the first portion of the emitter, a peripheral portion having a second base width larger than the first base width partly underlying the second portion of the emitter, and a transition zone of a third base width and lateral extent lying laterally between the first and second portions of the base, and a collector underlying the base. The gain of the transistor is larger than a conventional bipolar transistor made using the same CMOS process. By adjusting the lateral extent of the transition zone, the properties of the improved transistor can be tailored to suit different applications without modifying the underlying CMOS IC process.
摘要翻译：提供用于形成改进的双极晶体管的实施例，可通过CMOS IC工艺制造。改进的晶体管包括具有不同深度的第一和第二部分的发射器，发射器下面的基底具有位于发射器的第一部分下方的第一基底宽度的中心部分，具有大于第一基底的第二基底宽度的周边部分部分位于发射体的第二部分下方的宽度，以及位于基底的第一和第二部分之间横向置换的第三基底宽度和横向范围的过渡区，以及位于基底的收集器。晶体管的增益大于使用相同CMOS工艺制造的常规双极晶体管。通过调整过渡区域的横向范围，可以调整改进晶体管的性能以适应不同的应用，而无需修改底层的CMOS IC工艺。

98. 发明申请

US20140308792A1 METHODS OF PRODUCING BIPOLAR TRANSISTORS HAVING EMITTER-BASE JUNCTIONS OF VARYING DEPTHS AND/OR DOPING CONCENTRATIONS 有权
标题翻译：生产具有变化深度和/或掺杂浓度的发射体基极结的双极晶体管的方法
公开(公告)号：US20140308792A1
公开(公告)日：2014-10-16
申请号：US14313114
申请日：2014-06-24
申请人： Xin Lin , Bernhard H. Grote , Jiang-Kai Zuo
发明人： Xin Lin , Bernhard H. Grote , Jiang-Kai Zuo
IPC分类号： H01L29/66 , H01L29/735
CPC分类号： H01L29/6625 , H01L21/8222 , H01L21/8249 , H01L29/705 , H01L29/7317 , H01L29/735
摘要： Methods for producing bipolar transistors are provided. In one embodiment, the method includes producing a bipolar transistor including first and second connected emitter-base (EB) junctions of varying different depths. A buried layer (BL) collector is further produced to have a third depth greater than the depths of the EB junctions. The emitters and bases corresponding to the different EB junctions are provided during a chain implant. An isolation region may overlie the second EB junction location. The BL collector is laterally spaced from the first EB junction by a variable amount to facilitate adjustment of the transistor properties. The BL collector may or may not underlie at least a portion of the second EB junction. Regions of opposite conductivity type overlie and underlie the BL collector to preserve breakdown voltage. The transistor can be readily “tuned” by mask adjustments alone to meet various device requirements.
摘要翻译：提供了制造双极晶体管的方法。在一个实施例中，该方法包括产生包括变化不同深度的第一和第二连接的发射极基极（EB）结的双极晶体管。进一步制造掩埋层（BL）集电体以具有大于EB结的深度的第三深度。在链植入期间提供对应于不同EB结的发射器和基座。隔离区域可以覆盖第二EB结点位置。 BL收集器与第一EB结横向间隔可变量以便于调整晶体管特性。 BL收集器可以或可以不位于第二EB结的至少一部分的下面。相反导电类型的区域叠加在BL集电极之下，以保持击穿电压。晶体管可以通过单独的掩模调节容易地“调谐”以满足各种器件要求。

99. 发明授权

US08487398B2 Capacitor device using an isolated well and method therefor 有权
标题翻译：使用隔离井的电容器件及其方法
公开(公告)号：US08487398B2
公开(公告)日：2013-07-16
申请号：US12835900
申请日：2010-07-14
申请人： Hongzhong Xu , Zhihong Zhang , Jiang-Kai Zuo
发明人： Hongzhong Xu , Zhihong Zhang , Jiang-Kai Zuo
IPC分类号： H01L21/70
CPC分类号： H01L29/94 , H01L29/66181
摘要： A semiconductor device includes an isolated p-type well, wherein the isolated p-type well is a first electrode of a capacitor device; a capacitor dielectric on the isolated p-type well; a p-type polysilicon electrode over the capacitor dielectric, wherein the p-type polysilicon electrode is a second electrode of the capacitor device; a first p-type contact region in the isolated p-type well, laterally extending from a first sidewall of the p-type polysilicon electrode; a second p-type contact region in the isolated p-type well, laterally extending from a second sidewall of the p-type polysilicon electrode, opposite the first sidewall of the p-type polysilicon electrode, wherein a portion of the isolated p-type well between the first and second p-type contact regions is under the p-type polysilicon electrode and the capacitor dielectric; and an n-type isolation region surrounding the isolated p-type well. This device may be conveniently coupled to a fringe capacitor.
摘要翻译：半导体器件包括隔离的p型阱，其中隔离的p型阱是电容器器件的第一电极; 隔离p型阱上的电容器电介质; 电容器电介质上的p型多晶硅电极，其中p型多晶硅电极是电容器器件的第二电极; 分离的p型阱中的第一p型接触区，从p型多晶硅电极的第一侧壁横向延伸; 在隔离的p型阱中的第二p型接触区域，从p型多晶硅电极的第二侧壁横向延伸，与p型多晶硅电极的第一侧壁相对，其中一部分隔离的p型第一和第二p型接触区之间的阱在p型多晶硅电极和电容器电介质之下; 以及围绕隔离p型阱的n型隔离区。该装置可以方便地连接到边缘电容器。

100. 发明申请

US20100301403A1 SEMICONDUCTOR DEVICE WITH MULTIPLE GATES AND DOPED REGIONS AND METHOD OF FORMING 有权
标题翻译：具有多个门和多个区域的半导体器件及其形成方法
公开(公告)号：US20100301403A1
公开(公告)日：2010-12-02
申请号：US12475232
申请日：2009-05-29
申请人： WON GI MIN , John L. Huber , Jiang-Kai Zuo
发明人： WON GI MIN , John L. Huber , Jiang-Kai Zuo
IPC分类号： H01L29/788 , H01L21/336
CPC分类号： H01L29/7816 , H01L29/0619 , H01L29/0696 , H01L29/404
摘要： A semiconductor device includes a source region within a semiconductor substrate, a drain region within the semiconductor substrate, a control gate over the semiconductor substrate and between the source region and the drain region, a first gate between the control gate and the drain region, and a first doped region within the semiconductor region and between the control gate and the first gate. The method of forming the semiconductor device may include depositing an electrode material over the semiconductor substrate, patterning the electrode material to form a control gate and a first gate, implanting a first doped region within the semiconductor substrate between the control gate and the first gate while using the control gate and the first gate as a mask, and implanting a source region within the semiconductor substrate.
摘要翻译：半导体器件包括半导体衬底内的源极区域，半导体衬底内的漏极区域，半导体衬底上的控制栅极以及源极区域和漏极区域之间的控制栅极，控制栅极和漏极区域之间的第一栅极，以及半导体区域内和控制栅极与第一栅极之间的第一掺杂区域。形成半导体器件的方法可以包括在半导体衬底上沉积电极材料，图案化电极材料以形成控制栅极和第一栅极，在控制栅极和第一栅极之间注入半导体衬底内的第一掺杂区域，同时使用控制栅极和第一栅极作为掩模，并且在半导体衬底内注入源极区域。

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