专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

91. 发明授权

US06437627B1 High voltage level shifter for switching high voltage in non-volatile memory intergrated circuits 失效
标题翻译：用于在非易失性存储器集成电路中切换高电压的高电压电平转换器
公开(公告)号：US06437627B1
公开(公告)日：2002-08-20
申请号：US08519396
申请日：1995-08-25
申请人： Hieu Van Tran , Trevor Blyth
发明人： Hieu Van Tran , Trevor Blyth
IPC分类号： H03L500
CPC分类号： H03K17/102 , H03K3/356052 , H03K3/356147
摘要： A high voltage level shifter utilizing only low voltage PMOS and low voltage NMOS devices. The high voltage level shifter is used to distribute the high voltage almost equally among the PMOS devices and almost equally among the NMOS devices to meet the device electrical specification of low voltage MOS devices for various breakdown mechanisms. A layout technique is also used to achieve a much higher junction breakdown of N+ drain to P-substrate and a better gated diode breakdown of NMOS devices.
摘要翻译：仅使用低电压PMOS和低电压NMOS器件的高电压电平移位器。高电压电平转换器用于在PMOS器件中几乎均匀地分配高电压，并且在NMOS器件中几乎相等地分配高电压，以满足用于各种击穿机制的低电压MOS器件的器件电气规范。还使用布局技术来实现N +漏极到P衬底的更高的结击穿和NMOS器件的更好的门控二极管击穿。

92. 发明申请

US20140140138A1 Three-Dimensional Flash Memory System 有权
标题翻译：三维闪存系统
公开(公告)号：US20140140138A1
公开(公告)日：2014-05-22
申请号：US13680719
申请日：2012-11-19
申请人： Hieu Van Tran , Hung Quoc Nguyen , Mark Reiten
发明人： Hieu Van Tran , Hung Quoc Nguyen , Mark Reiten
IPC分类号： G11C16/06
CPC分类号： G11C29/76 , G11C5/02 , G11C5/06 , G11C7/04 , G11C16/0483 , G11C16/06 , G11C16/08 , G11C16/10 , G11C16/26 , G11C16/30 , G11C16/3404 , G11C29/021 , G11C29/022 , G11C29/028 , G11C29/1201 , G11C29/26 , G11C2213/71 , H01L25/0652 , H01L25/18 , H01L2224/13025 , H01L2224/14181 , H01L2224/16145 , H01L2224/16225 , H01L2225/06513 , H01L2225/06541 , H01L2924/15311
摘要： A three-dimensional flash memory system is disclosed.
摘要翻译：公开了三维闪存系统。

93. 发明授权

US08705282B2 Mixed voltage non-volatile memory integrated circuit with power saving 有权
标题翻译：混合电压非易失性存储器集成电路，省电
公开(公告)号：US08705282B2
公开(公告)日：2014-04-22
申请号：US13286969
申请日：2011-11-01
申请人： Hieu Van Tran , Anh Ly , Thuan Vu , Hung Quoc Nguyen
发明人： Hieu Van Tran , Anh Ly , Thuan Vu , Hung Quoc Nguyen
IPC分类号： G11C11/34 , G11C16/04
CPC分类号： G11C16/30 , G11C5/147 , G11C11/5628 , G11C16/08
摘要： An integrated circuit die has a first die pad for receiving a first voltage and a second die pad for receiving a second voltage. The second voltage is less than the first voltage. A first circuit which is operable at the first voltage is in the integrated circuit die. A second circuit which is operable at the second voltage is in the integrated circuit die and is connected to the second die pad. A circuit that detects current flow from the second die pad is in the integrated circuit die. A switch is interposed between the first die pad and the first circuit to disconnect the first die pad from the first circuit in response to current flow detected by the circuit for detecting current flow.
摘要翻译：集成电路管芯具有用于接收第一电压的第一管芯焊盘和用于接收第二电压的第二管芯焊盘。第二电压小于第一电压。可在第一电压下操作的第一电路在集成电路管芯中。可在第二电压下操作的第二电路在集成电路管芯中，并连接到第二管芯焊盘。检测来自第二管芯焊盘的电流的电路在集成电路管芯中。开关被插入在第一管芯焊盘和第一电路之间，以响应于用于检测电流的电路检测到的电流来将第一管芯焊盘与第一电路断开。

94. 发明申请

US20140094011A1 Self-Aligned Method Of Forming A Semiconductor Memory Array Of Floating Gate Memory Cells With Single Poly Layer 有权
标题翻译：形成具有单个多层的浮动门存储器单元的半导体存储器阵列的自对准方法
公开(公告)号：US20140094011A1
公开(公告)日：2014-04-03
申请号：US13631474
申请日：2012-09-28
申请人： Nhan Do , Vipin Tiwari , Hieu Van Tran , Xian Liu
发明人： Nhan Do , Vipin Tiwari , Hieu Van Tran , Xian Liu
IPC分类号： H01L21/336
CPC分类号： H01L29/7881 , H01L29/0847 , H01L29/42324 , H01L29/66825
摘要： A method of forming a semiconductor memory cell that includes forming the floating and control gates from the same poly layer. Layers of insulation, conductive and second insulation material are formed over a substrate. A trench is formed in the second insulation material extending down to and exposing the conductive layer. Spacers are formed in the trench, separated by a small and defined gap at a bottom of the trench that exposes a portion of the conductive layer. A trench is then formed through the exposed portion of the conductive layer by performing an anisotropic etch through the gap. The trench is filled with third insulation material. Selected portions of the conductive layer are removed, leaving two blocks thereof separated by the third insulation material.
摘要翻译：一种形成半导体存储单元的方法，包括从同一多晶层形成浮置和控制栅极。在衬底上形成绝缘层，导电和第二绝缘材料层。在第二绝缘材料中形成沟槽，其向下延伸并暴露导电层。间隔件形成在沟槽中，由沟槽底部的小的和限定的间隙分开，露出导电层的一部分。然后通过穿过间隙进行各向异性蚀刻，通过导电层的暴露部分形成沟槽。沟槽填充有第三绝缘材料。去除导电层的选定部分，留下两个由第三绝缘材料隔开的块。

95. 发明申请

US20130242672A1 Non-volatile Memory Device And A Method Of Operating Same 有权
标题翻译：非易失性存储器件及其操作方法相同
公开(公告)号：US20130242672A1
公开(公告)日：2013-09-19
申请号：US13419269
申请日：2012-03-13
申请人： Hieu Van Tran , Hung Quoc Nguyen , Nhan Do
发明人： Hieu Van Tran , Hung Quoc Nguyen , Nhan Do
IPC分类号： G11C16/04
CPC分类号： G11C16/04 , G11C16/0425 , G11C16/06 , G11C16/12 , G11C16/30 , G11C16/3418
摘要： An array of non-volatile memory cells in a semiconductor substrate of a first conductivity type. Each memory cell comprises first and second regions of a second conductivity type on a surface of the substrate, with a channel region therebetween. A word line overlies one portion of the channel region, is adjacent to the first region, and has little or no overlap with the first region. A floating gate overlies another portion of the channel region, and is adjacent to the first portion and the second region. A coupling gate overlies the floating gate. An erase gate overlies the second region. A bit line is connected to the first region. A negative charge pump circuit generates a negative voltage. A control circuit generates a plurality of control signals in response to receiving a command signal, and applies the negative voltage to the word line of unselected memory cells.
摘要翻译：在第一导电类型的半导体衬底中的非易失性存储单元阵列。每个存储单元包括在衬底的表面上的第二导电类型的第一和第二区域，其间具有沟道区域。字线重叠在通道区域的一部分上，与第一区域相邻，并且与第一区域几乎没有或没有重叠。浮动栅极覆盖沟道区域的另一部分，并且与第一部分和第二区域相邻。耦合栅极覆盖浮栅。擦除门覆盖第二区域。位线连接到第一区域。负电荷泵电路产生负电压。控制电路响应于接收到命令信号而产生多个控制信号，并将负电压施加到未选择存储单元的字线。

96. 发明授权

US08497667B2 Fast voltage regulators for charge pumps 有权
标题翻译：快速电压调节器
公开(公告)号：US08497667B2
公开(公告)日：2013-07-30
申请号：US13306950
申请日：2011-11-29
申请人： Hieu Van Tran , Sang Thanh Nguyen , Anh Ly , Hung Q. Nguyen , Wingfu Aaron Lau , Nasrin Jaffari , Thuan Trong Vu , Vishal Sarin , Loc B. Hoang
发明人： Hieu Van Tran , Sang Thanh Nguyen , Anh Ly , Hung Q. Nguyen , Wingfu Aaron Lau , Nasrin Jaffari , Thuan Trong Vu , Vishal Sarin , Loc B. Hoang
IPC分类号： G05F3/16
CPC分类号： H02M3/07 , G11C5/145 , H02M1/36 , H02M1/44 , Y10T307/50
摘要： A digital multilevel memory system includes a charge pump and a voltage regulator for generating regulated high voltages for various memory operations. The charge pump may include a plurality of boost circuits to boost the output of the charge pump during a fast start up. Afterwards, the boost circuits are disabled to allow the charge pump to generate high voltages without boosting. The boost circuits may be successively enabled to boost the voltage. The boost circuits may be loadless. The voltage regulator may operate in an open loop and may include a resistive divider as a reference voltage for regulating the high voltage from the charge pump. The charge pump may include spread spectrum pump clocking to reduce electromagnetic inference for capacitor or inductor on-chip charge pumping.
摘要翻译：数字多电平存储器系统包括电荷泵和用于产生用于各种存储器操作的调节高电压的电压调节器。电荷泵可以包括多个升压电路，以在快速启动期间升高电荷泵的输出。之后，升压电路被禁止，使电荷泵产生高电压而不加速。升压电路可以被连续地使能以升高电压。升压电路可以是无负载的。电压调节器可以在开环中工作，并且可以包括电阻分压器作为用于调节来自电荷泵的高电压的参考电压。电荷泵可以包括扩频泵时钟，以减少用于电容器或电感器片上电荷泵浦的电磁推理。

97. 发明申请

US20130126958A1 Array Of Split Gate Non-volatile Floating Gate Memory Cells Having Improved Strapping Of The Coupling Gates 有权
标题翻译：阵列的分离门非易失性浮动门存储单元改进了耦合门的捆扎
公开(公告)号：US20130126958A1
公开(公告)日：2013-05-23
申请号：US13299320
申请日：2011-11-17
申请人： Parviz Ghazavi , Hieu Van Tran , Shiuh-Luen Wang , Nhan Do , Henry A. Om'mani
发明人： Parviz Ghazavi , Hieu Van Tran , Shiuh-Luen Wang , Nhan Do , Henry A. Om'mani
IPC分类号： H01L27/088
CPC分类号： H01L27/0207 , H01L21/28273 , H01L27/11519 , H01L27/11521 , H01L29/42328 , H01L29/66825 , H01L29/7885
摘要： An array of non-volatile memory cells with spaced apart first regions extending in a row direction and second regions extending in a column direction, with a channel region defined between each second region and its associated first region. A plurality of spaced apart word line gates each extending in the row direction and positioned over a first portion of a channel region. A plurality of spaced apart floating gates are positioned over second portions of the channel regions. A plurality of spaced apart coupling gates each extending in the row direction and over the floating gates. A plurality of spaced apart metal strapping lines each extending in the row direction and overlying a coupling gate. A plurality of spaced apart erase gates each extending in the row direction and positioned over a first region and adjacent to a floating gate and coupling gate.
摘要翻译：具有在行方向上延伸的具有间隔开的第一区域和在列方向上延伸的第二区域的非易失性存储器单元的阵列，其中限定在每个第二区域与其相关联的第一区域之间的通道区域。每个在行方向上延伸并定位在通道区域的第一部分上方的多个间隔开的字线门。多个间隔开的浮动栅极位于沟道区域的第二部分上方。多个间隔开的耦合栅极，每个在行方向和浮动栅极上延伸。多个间隔开的金属捆绑线，各自在行方向上延伸并且覆盖耦合门。多个间隔开的擦除栅极，每个沿行方向延伸并定位在第一区域上并且与浮栅和耦合栅极相邻。

98. 发明授权

US08339187B2 Charge pump systems and methods 有权
公开(公告)号：US08339187B2
公开(公告)日：2012-12-25
申请号：US13070405
申请日：2011-03-23
申请人： Hieu Van Tran , Sang Thanh Nguyen , Nasrin Jaffari , Hung Quoc Nguyen , Anh Ly
发明人： Hieu Van Tran , Sang Thanh Nguyen , Nasrin Jaffari , Hung Quoc Nguyen , Anh Ly
IPC分类号： H02M3/18 , G05F3/20
CPC分类号： G05F3/02 , H02M3/073 , H02M2001/322
摘要： Digital multilevel memory systems and methods include a charge pump for generating regulated high voltages for various memory operations. The charge pump may include a plurality of pump stages. Aspects of exemplary systems may include charge pumps that performs orderly charging and discharging at low voltage operation conditions. Additional aspects may include features that enable state by state pumping, for example, circuitry that avoids cascaded short circuits among pump stages. Each pump stage may also include circuitry that discharges its nodes, such as via self-discharge through associated pump interconnection(s). Further aspects may also include features that: assist power-up in the various pump stages, double voltage, shift high voltage levels, provide anti-parallel circuit configurations, and/or enable buffering or precharging features, such as self-buffering and self-precharging circuitry.

99. 发明授权

US08018773B2 Array of non-volatile memory cells including embedded local and global reference cells and system 有权
公开(公告)号：US08018773B2
公开(公告)日：2011-09-13
申请号：US12398155
申请日：2009-03-04
申请人： Hieu Van Tran , Anh Ly , Hung Q. Nguyen , Thuan T. Vu
发明人： Hieu Van Tran , Anh Ly , Hung Q. Nguyen , Thuan T. Vu
IPC分类号： G11C16/06
CPC分类号： G11C16/28 , G11C5/025 , G11C7/14 , G11C16/30 , H01L27/11521 , H01L29/42328 , H01L29/7881
摘要： An array of memory cells has a first side adjacent to a first column, a second side opposite the first side, a third side adjacent to a first row, and a fourth side opposite the third side. Each memory cell is connected to a bit line, a high voltage source, and a low voltage source. Reference cells, substantially the same as the memory cells, evenly spaced apart, are embedded in the array. A high voltage decoder is on the first side, connected to the memory cells and reference cells in the same row. A low voltage row decoder is on the second side, connected to the memory cells and reference cells in the same row. Sense amplifiers are on the third side, connected to the memory cells and to the reference cells.

100. 发明授权

US07969239B2 Charge pump circuit and a novel capacitor for a memory integrated circuit 有权
标题翻译：电荷泵电路和用于存储器集成电路的新型电容器
公开(公告)号：US07969239B2
公开(公告)日：2011-06-28
申请号：US12569832
申请日：2009-09-29
申请人： Hieu Van Tran , Hung Q. Nguyen , Thuan T. Vu , Anh Ly
发明人： Hieu Van Tran , Hung Q. Nguyen , Thuan T. Vu , Anh Ly
IPC分类号： H01L25/00
CPC分类号： H02M3/07 , G11C5/145
摘要： A novel capacitor for use in a charge pump circuit has a substrate with a planar surface. A first electrode is in a first plane spaced apart from the planar surface. A second electrode is adjacent to and is spaced apart from the first electrode in the first plane and is capacitively coupled thereto. A third electrode is in a second plane, spaced apart from the first plane and is capacitively coupled to the first electrode. A fourth electrode is adjacent to and spaced apart from the third electrode in the second plane and is capacitively coupled to the third electrode and capacitively coupled to the second electrode. The first and fourth electrodes are electrically connected together and the second and third electrodes are electrically connected together. In addition, a cylindrical shape electrode, and a great wall electrode, and charge pump capacitor-by-pattern-filling is disclosed. A charge pump circuit using the foregoing described capacitor has a plurality of transistors for charging the capacitor and discharging the capacitor thereby increasing the voltage of the charge pump circuit.
摘要翻译：用于电荷泵电路的新型电容器具有具有平坦表面的基板。第一电极处于与平面间隔开的第一平面中。第二电极与第一平面中的第一电极相邻并且与第一电极间隔开并且与其电容耦合。第三电极处于与第一平面间隔开的第二平面中并与第一电极电容耦合。第四电极在第二平面中与第三电极相邻并间隔开，并且电容耦合到第三电极并电容耦合到第二电极。第一和第四电极电连接在一起，第二和第三电极电连接在一起。另外，公开了圆柱形电极和长壁电极以及电荷泵电容器逐图案填充。使用上述电容器的电荷泵电路具有多个用于对电容器充电并对电容器进行放电的晶体管，从而增加电荷泵电路的电压。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式