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1. 发明授权

US08072815B2 Array of non-volatile memory cells including embedded local and global reference cells and system 有权
标题翻译：阵列非易失性存储单元包括嵌入式本地和全局参考单元和系统
公开(公告)号：US08072815B2
公开(公告)日：2011-12-06
申请号：US12965504
申请日：2010-12-10
申请人： Hieu Van Tran , Anh Ly , Hung Q. Nguyen , Thuan T. Vu
发明人： Hieu Van Tran , Anh Ly , Hung Q. Nguyen , Thuan T. Vu
IPC分类号： G11C16/06
CPC分类号： G11C16/28 , G11C5/025 , G11C7/14 , G11C16/30 , H01L27/11521 , H01L29/42328 , H01L29/7881
摘要： An array of memory cells has a first side adjacent to a first column, a second side opposite the first side, a third side adjacent to a first row, and a fourth side opposite the third side. Each memory cell is connected to a bit line, a high voltage source, and a low voltage source. Reference cells, substantially the same as the memory cells, evenly spaced apart, are embedded in the array. A high voltage decoder is on the first side, connected to the memory cells and reference cells in the same row. A low voltage row decoder is on the second side, connected to the memory cells and reference cells in the same row. Sense amplifiers are on the third side, connected to the memory cells and to the reference cells.
摘要翻译：存储单元阵列具有与第一列相邻的第一侧，与第一侧相对的第二侧，与第一行相邻的第三侧和与第三侧相对的第四侧。每个存储单元连接到位线，高电压源和低电压源。基本上与存储单元基本相同的参考单元被均匀间隔地嵌入阵列中。高压解码器位于第一侧，连接到同一行的存储单元和参考单元。低压行解码器位于第二侧，连接到同一行中的存储单元和参考单元。感测放大器位于第三侧，连接到存储单元和参考单元。

2. 发明申请

US20110080790A1 Array Of Non-volatile Memory Cells Including Embedded Local And Global Reference Cells And System 有权
标题翻译：包括嵌入式本地和全局参考单元和系统的非易失性存储单元阵列
公开(公告)号：US20110080790A1
公开(公告)日：2011-04-07
申请号：US12965504
申请日：2010-12-10
申请人： Hieu Van Tran , Anh Ly , Hung Q. Nguyen , Thuan T. Vu
发明人： Hieu Van Tran , Anh Ly , Hung Q. Nguyen , Thuan T. Vu
IPC分类号： G11C16/06
CPC分类号： G11C16/28 , G11C5/025 , G11C7/14 , G11C16/30 , H01L27/11521 , H01L29/42328 , H01L29/7881
摘要： An array of memory cells has a first side adjacent to a first column, a second side opposite the first side, a third side adjacent to a first row, and a fourth side opposite the third side. Each memory cell is connected to a bit line, a high voltage source, and a low voltage source. Reference cells, substantially the same as the memory cells, evenly spaced apart, are embedded in the array. A high voltage decoder is on the first side, connected to the memory cells and reference cells in the same row. A low voltage row decoder is on the second side, connected to the memory cells and reference cells in the same row. Sense amplifiers are on the third side, connected to the memory cells and to the reference cells.
摘要翻译：存储单元阵列具有与第一列相邻的第一侧，与第一侧相对的第二侧，与第一行相邻的第三侧和与第三侧相对的第四侧。每个存储单元连接到位线，高电压源和低电压源。基本上与存储单元基本相同的参考单元被均匀间隔地嵌入阵列中。高压解码器位于第一侧，连接到同一行的存储单元和参考单元。低压行解码器位于第二侧，连接到同一行中的存储单元和参考单元。感测放大器位于第三侧，连接到存储单元和参考单元。

3. 发明申请

US20100226181A1 Array Of Non-volatile Memory Cells Including Embedded Local And Global Reference Cells And System 有权
公开(公告)号：US20100226181A1
公开(公告)日：2010-09-09
申请号：US12398155
申请日：2009-03-04
申请人： Hieu Van Tran , Anh Ly , Hung Q. Nguyen , Thuan T. Vu
发明人： Hieu Van Tran , Anh Ly , Hung Q. Nguyen , Thuan T. Vu
IPC分类号： G11C16/06
CPC分类号： G11C16/28 , G11C5/025 , G11C7/14 , G11C16/30 , H01L27/11521 , H01L29/42328 , H01L29/7881
摘要： A non-volatile memory device comprises an array of non-volatile memory cells arranged in a plurality of rows and columns. Each memory cell has a bit terminal for connection to a bit line, a high voltage terminal for connection to a high voltage source, and a low voltage terminal for connection to a low voltage source. The array has a first side adjacent to a first column of memory cells, and a second side opposite the first side, a third side adjacent to a first row of memory cells, and a fourth side opposite the third side. The memory device further comprises a plurality of columns of reference memory cells embedded in the memory array, with a plurality of reference cells in each row of the array of non-volatile memory cells, substantially evenly spaced apart from one another. Each of the reference memory cells is substantially the same as the non-volatile memory cells, and has a bit terminal for connection to a bit line, a high voltage terminal for connection to a high voltage source and a low voltage terminal for connection to a low voltage source. A high voltage decoder is positioned on the first side, and has a plurality of high voltage lines, with each high voltage line connected to the high voltage terminal of the memory cells and reference cells in the same row. A low voltage row decoder is positioned on the second side, and has a plurality of low voltage lines, with each low voltage line connected to the low voltage terminal of the memory cells and reference cells in the same row. A plurality of sense amplifiers are positioned on the third side, with each sense amplifier connected to the bit terminal of one column of non-volatile memory cells and to the bit terminal of a column of reference memory cells. This invention also includes N-of-M selective reference scheme, distributed source line pull down, source line resistance strap compensation, replica-data-pattern current consumption, data current compensation, and bit line voltage error compensation.

4. 发明授权

US07839682B2 Array and pitch of non-volatile memory cells 有权
标题翻译：非易失性存储单元的阵列和间距
公开(公告)号：US07839682B2
公开(公告)日：2010-11-23
申请号：US12362106
申请日：2009-01-29
申请人： Hieu Van Tran , Anh Ly , Hung Q. Nguyen , Thuan T. Vu
发明人： Hieu Van Tran , Anh Ly , Hung Q. Nguyen , Thuan T. Vu
IPC分类号： G11C16/00
CPC分类号： G11C16/10 , G11C16/0408
摘要： An array of non-volatile memory cells is arranged in a plurality of rows and columns, wherein each memory cell has at least three terminals: a first terminal for the read out of the signal from the memory cell, a second terminal to which high voltage is supplied during certain operation, and a third terminal to which low voltage is supplied in all operations. The cells in the same column have a common bit line connected to the first terminal of memory cells in the same column. The array comprises a first and second sub arrays of memory cells arranged adjacent to one another in the same row. A first decoder is positioned to one side of the first sub array in the same row as the first sub array. A second decoder is positioned to another side of the second sub array in the same row as the second sub array. A first high voltage line is connected to the second decoder and to only the second terminal of the memory cells in the same row in the first sub array. A second high voltage line, different from the first high voltage line, is connected to the second decoder and to only the second terminal of the memory cells in the same row in the second sub array. A low voltage line is connected to the first decoder and to the thirds terminal of the memory cells in the same row of the first and second sub arrays.
摘要翻译：一组非易失性存储单元被布置成多个行和列，其中每个存储单元具有至少三个端子：用于从存储单元读出信号的第一端子，高电压的第二端子在一定操作期间提供，并且在所有操作中提供低电压的第三端子。同一列中的单元具有连接到同一列中的存储器单元的第一端的公共位线。阵列包括在同一行中彼此相邻布置的存储单元的第一和第二子阵列。第一解码器位于与第一子阵列相同的行中的第一子阵列的一侧。第二解码器被定位在与第二子阵列相同的行中的第二子阵列的另一侧。第一高压线路连接到第二解码器，并且仅连接到第一子阵列中的同一行中的存储器单元的第二端子。与第一高压线不同的第二高压线路连接到第二解码器，并且仅连接到第二子阵列中同一行中的存储器单元的第二端子。低电压线连接到第一解码器和第一和第二子阵列的同一行中的存储器单元的第三端子。

5. 发明授权

US08018773B2 Array of non-volatile memory cells including embedded local and global reference cells and system 有权
公开(公告)号：US08018773B2
公开(公告)日：2011-09-13
申请号：US12398155
申请日：2009-03-04
申请人： Hieu Van Tran , Anh Ly , Hung Q. Nguyen , Thuan T. Vu
发明人： Hieu Van Tran , Anh Ly , Hung Q. Nguyen , Thuan T. Vu
IPC分类号： G11C16/06
CPC分类号： G11C16/28 , G11C5/025 , G11C7/14 , G11C16/30 , H01L27/11521 , H01L29/42328 , H01L29/7881
摘要： An array of memory cells has a first side adjacent to a first column, a second side opposite the first side, a third side adjacent to a first row, and a fourth side opposite the third side. Each memory cell is connected to a bit line, a high voltage source, and a low voltage source. Reference cells, substantially the same as the memory cells, evenly spaced apart, are embedded in the array. A high voltage decoder is on the first side, connected to the memory cells and reference cells in the same row. A low voltage row decoder is on the second side, connected to the memory cells and reference cells in the same row. Sense amplifiers are on the third side, connected to the memory cells and to the reference cells.

6. 发明授权

US07969239B2 Charge pump circuit and a novel capacitor for a memory integrated circuit 有权
标题翻译：电荷泵电路和用于存储器集成电路的新型电容器
公开(公告)号：US07969239B2
公开(公告)日：2011-06-28
申请号：US12569832
申请日：2009-09-29
申请人： Hieu Van Tran , Hung Q. Nguyen , Thuan T. Vu , Anh Ly
发明人： Hieu Van Tran , Hung Q. Nguyen , Thuan T. Vu , Anh Ly
IPC分类号： H01L25/00
CPC分类号： H02M3/07 , G11C5/145
摘要： A novel capacitor for use in a charge pump circuit has a substrate with a planar surface. A first electrode is in a first plane spaced apart from the planar surface. A second electrode is adjacent to and is spaced apart from the first electrode in the first plane and is capacitively coupled thereto. A third electrode is in a second plane, spaced apart from the first plane and is capacitively coupled to the first electrode. A fourth electrode is adjacent to and spaced apart from the third electrode in the second plane and is capacitively coupled to the third electrode and capacitively coupled to the second electrode. The first and fourth electrodes are electrically connected together and the second and third electrodes are electrically connected together. In addition, a cylindrical shape electrode, and a great wall electrode, and charge pump capacitor-by-pattern-filling is disclosed. A charge pump circuit using the foregoing described capacitor has a plurality of transistors for charging the capacitor and discharging the capacitor thereby increasing the voltage of the charge pump circuit.
摘要翻译：用于电荷泵电路的新型电容器具有具有平坦表面的基板。第一电极处于与平面间隔开的第一平面中。第二电极与第一平面中的第一电极相邻并且与第一电极间隔开并且与其电容耦合。第三电极处于与第一平面间隔开的第二平面中并与第一电极电容耦合。第四电极在第二平面中与第三电极相邻并间隔开，并且电容耦合到第三电极并电容耦合到第二电极。第一和第四电极电连接在一起，第二和第三电极电连接在一起。另外，公开了圆柱形电极和长壁电极以及电荷泵电容器逐图案填充。使用上述电容器的电荷泵电路具有多个用于对电容器充电并对电容器进行放电的晶体管，从而增加电荷泵电路的电压。

7. 发明申请

US20100188900A1 ARRAY AND PITCH OF NON-VOLATILE MEMORY CELLS 有权
标题翻译：非易失性记忆细胞的阵列和位点
公开(公告)号：US20100188900A1
公开(公告)日：2010-07-29
申请号：US12362106
申请日：2009-01-29
申请人： Hieu Van Tran , Anh Ly , Hung Q. Nguyen , Thuan T. Vu
发明人： Hieu Van Tran , Anh Ly , Hung Q. Nguyen , Thuan T. Vu
IPC分类号： G11C16/04 , G11C16/06
CPC分类号： G11C16/10 , G11C16/0408
摘要： An array of non-volatile memory cells is arranged in a plurality of rows and columns, wherein each memory cell has at least three terminals: a first terminal for the read out of the signal from the memory cell, a second terminal to which high voltage is supplied during certain operation, and a third terminal to which low voltage is supplied in all operations. The cells in the same column have a common bit line connected to the first terminal of memory cells in the same column. The array comprises a first and second sub arrays of memory cells arranged adjacent to one another in the same row. A first decoder is positioned to one side of the first sub array in the same row as the first sub array. A second decoder is positioned to another side of the second sub array in the same row as the second sub array. A first high voltage line is connected to the second decoder and to only the second terminal of the memory cells in the same row in the first sub array. A second high voltage line, different from the first high voltage line, is connected to the second decoder and to only the second terminal of the memory cells in the same row in the second sub array. A low voltage line is connected to the first decoder and to the thirds terminal of the memory cells in the same row of the first and second sub arrays.
摘要翻译：一组非易失性存储单元被布置成多个行和列，其中每个存储单元具有至少三个端子：用于从存储单元读出信号的第一端子，高电压的第二端子在一定操作期间提供，并且在所有操作中提供低电压的第三端子。同一列中的单元具有连接到同一列中的存储器单元的第一端的公共位线。阵列包括在同一行中彼此相邻布置的存储单元的第一和第二子阵列。第一解码器位于与第一子阵列相同的行中的第一子阵列的一侧。第二解码器被定位在与第二子阵列相同的行中的第二子阵列的另一侧。第一高压线路连接到第二解码器，并且仅连接到第一子阵列中的同一行中的存储器单元的第二端子。与第一高压线不同的第二高压线路连接到第二解码器，并且仅连接到第二子阵列中同一行中的存储器单元的第二端子。低电压线连接到第一解码器和第一和第二子阵列的同一行中的存储器单元的第三端子。

8. 发明授权

US07848140B2 Flash memory array system including a top gate memory cell 有权
标题翻译：包括顶栅存储单元的闪存阵列系统
公开(公告)号：US07848140B2
公开(公告)日：2010-12-07
申请号：US12507783
申请日：2009-07-22
申请人： Hieu Van Tran , Hung Quoc Nguyen , Anh Ly , Sheng-Hsiung Hsueh , Sang Thanh Nguyen , Loc B. Hoang , Steve Choi , Thuan T. Vu
发明人： Hieu Van Tran , Hung Quoc Nguyen , Anh Ly , Sheng-Hsiung Hsueh , Sang Thanh Nguyen , Loc B. Hoang , Steve Choi , Thuan T. Vu
IPC分类号： G11C16/04
CPC分类号： G11C8/10 , G11C16/0433 , G11C16/08 , G11C29/832
摘要： A memory system includes memory cells arranged in sectors. A decoder corresponding to a sector disables memory cells having a defective top gate. The decoder may include a low voltage or high voltage latch for the disabling. A top gate handling algorithm is included. The memory system may include dynamic top gate coupling. A programming algorithm and waveforms with top gate handling is included.
摘要翻译：存储器系统包括布置在扇区中的存储器单元。对应于扇区的解码器禁止具有缺陷顶门的存储单元。解码器可以包括用于禁用的低电压或高电压锁存器。包括顶栅处理算法。存储器系统可以包括动态顶栅耦合。包括具有顶栅处理的编程算法和波形。

9. 发明授权

US07626863B2 Flash memory array system including a top gate memory cell 有权
标题翻译：包括顶栅存储单元的闪存阵列系统
公开(公告)号：US07626863B2
公开(公告)日：2009-12-01
申请号：US11707343
申请日：2007-02-16
申请人： Hieu Van Tran , Hung Quoc Nguyen , Anh Ly , Sheng-Hsiung Hsueh , Sang Thanh Nguyen , Loc B. Hoang , Steve Choi , Thuan T. Vu
发明人： Hieu Van Tran , Hung Quoc Nguyen , Anh Ly , Sheng-Hsiung Hsueh , Sang Thanh Nguyen , Loc B. Hoang , Steve Choi , Thuan T. Vu
IPC分类号： G11C16/04
CPC分类号： G11C8/10 , G11C16/0433 , G11C16/08 , G11C29/832
摘要： A memory system includes memory cells arranged in sectors. A decoder corresponding to a sector disables memory cells having a defective top gate. The decoder may include a low voltage or high voltage latch for the disabling. A top gate handling algorithm is included. The memory system may include dynamic top gate coupling. A programming algorithm and waveforms with top gate handling is included.
摘要翻译：存储器系统包括布置在扇区中的存储器单元。对应于扇区的解码器禁止具有缺陷顶门的存储单元。解码器可以包括用于禁用的低电压或高电压锁存器。包括顶栅处理算法。存储器系统可以包括动态顶栅耦合。包括具有顶栅处理的编程算法和波形。

10. 发明授权

US07447073B2 Method for handling a defective top gate of a source-side injection flash memory array 有权
标题翻译：用于处理源侧注入闪存阵列的有缺陷的顶栅的方法
公开(公告)号：US07447073B2
公开(公告)日：2008-11-04
申请号：US11707341
申请日：2007-02-16
申请人： Hieu Van Tran , Hung Quoc Nguyen , Anh Ly , Sheng-Hsiung Hsueh , Sang Thanh Nguyen , Loc B. Hoang , Steve Choi , Thuan T. Vu
发明人： Hieu Van Tran , Hung Quoc Nguyen , Anh Ly , Sheng-Hsiung Hsueh , Sang Thanh Nguyen , Loc B. Hoang , Steve Choi , Thuan T. Vu
IPC分类号： G11C16/34
CPC分类号： G11C8/10 , G11C16/0433 , G11C16/08 , G11C29/832
摘要： A memory system includes memory cells arranged in sectors. A decoder corresponding to a sector disables memory cells having a defective top gate. The decoder may include a low voltage or high voltage latch for the disabling. A top gate handling algorithm is included. The memory system may include dynamic top gate coupling. A programming algorithm and waveforms with top gate handling is included.
摘要翻译：存储器系统包括布置在扇区中的存储器单元。对应于扇区的解码器禁止具有缺陷顶门的存储单元。解码器可以包括用于禁用的低电压或高电压锁存器。包括顶栅处理算法。存储器系统可以包括动态顶栅耦合。包括具有顶栅处理的编程算法和波形。

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