专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

91. 发明授权

US07286620B2 Equalizer for reduced intersymbol interference via partial clock switching 有权
标题翻译：均衡器通过部分时钟切换减少符号间干扰
公开(公告)号：US07286620B2
公开(公告)日：2007-10-23
申请号：US10665235
申请日：2003-09-17
申请人： Hayden C. Cranford, Jr. , Westerfield J. Ficken , Wentai Liu
发明人： Hayden C. Cranford, Jr. , Westerfield J. Ficken , Wentai Liu
IPC分类号： H04L1/00
CPC分类号： H04L25/03133
摘要： A method and system for is disclosed for reducing intersymbol interference in a stream of data bits to be transmitted over a transmission medium. Aspects of the present invention include a phase delayed clock generated from a reference clock that produces an edge on sub-bit boundaries; and a digital filter coupled to the phase delayed clock for performing equalization on the data bits, wherein the phase delayed clock causes the digital filter to perform partial clock switching, such that equalization is performed on the data bits on-sub-bit boundaries.
摘要翻译：公开了一种用于减少要在传输介质上传输的数据位流中的符号间干扰的方法和系统。本发明的方面包括从产生子位边界边缘的参考时钟产生的相位延迟时钟; 以及耦合到所述相位延迟时钟的数字滤波器，用于对所述数据位执行均衡，其中所述相位延迟时钟使所述数字滤波器执行部分时钟切换，使得对所述数据位在子位边界执行均衡。

92. 发明授权

US07187206B2 Power savings in serial link transmitters 失效
标题翻译：串行链路发射机节电
公开(公告)号：US07187206B2
公开(公告)日：2007-03-06
申请号：US10697514
申请日：2003-10-30
申请人： Steven M. Clements , Carrie E. Cox , Hayden C. Cranford, Jr.
发明人： Steven M. Clements , Carrie E. Cox , Hayden C. Cranford, Jr.
IPC分类号： H03K19/0175 , H03H11/26
CPC分类号： H04L25/028 , H03K17/163 , H03K17/164
摘要： Aspects of saving power in a serial link transmitter are described. The aspects include providing a parallel arrangement of segments, each segment comprising prebuffer and output stage circuitry of the serial link transmitter and each segment enabled independently to achieve multiple power levels and multiple levels of pre-emphasis while maintaining a substantially constant propagation delay in a signal path of the serial link transmitter. Further aspects include providing a bypass path in the prebuffer stage circuitry to implement a controllable idle state in the segments and tail current and resistive load elements in the prebuffer circuitry as sectioned portions for slew rate control capability. Also included is provision of a control element with pre-emphasis delay circuitry in the transmitter signal path to allow inversion of a last delayed bit of the pre-emphasis delay circuitry to achieve a polarity change of a pre-emphasis weight.
摘要翻译：描述了在串行链路发射机中节省功率的方面。这些方面包括提供段的并行布置，每个段包括串行链路发射机的预缓冲器和输出级电路，并且每个段独立地使能以实现多个功率电平和多级预加重，同时保持信号中基本恒定的传播延迟串行链路发射机的路径。另外的方面包括在预缓冲器级电路中提供旁路路径，以实现段中的可控空闲状态，并将预缓冲器电路中的尾电流和电阻负载元件作为转换速率控制能力的切片部分。还包括在发射机信号路径中提供具有预加重延迟电路的控制元件，以允许预加重延迟电路的最后延迟位的反转，以实现预加重权重的极性改变。

93. 发明授权

US06999540B2 Programmable driver/equalizer with alterable analog finite impulse response (FIR) filter having low intersymbol interference and constant peak amplitude independent of coefficient settings 有权
标题翻译：可编程驱动器/均衡器具有可变模拟有限脉冲响应（FIR）滤波器，具有低符号间干扰和恒定峰值幅度，独立于系数设置
公开(公告)号：US06999540B2
公开(公告)日：2006-02-14
申请号：US09749908
申请日：2000-12-29
申请人： Hayden C. Cranford, Jr.
发明人： Hayden C. Cranford, Jr.
IPC分类号： H04B1/10
CPC分类号： H04L25/03885
摘要： A programmable driver/equalizer with an alterable FIR enables the equalization of serial links or other transmission systems to adapt to a variety of transmission media, specifically, intersymbol interference (ISI). Current mode differential drive circuits are coupled to a transmission media via a Finite Impulse Response (FIR) filter operating in the Z transform mode. The FIR filter includes A and B coefficient setting circuit, and is coupled to the drivers. The driver circuit also includes A coefficient level driver compensation and B coefficient level driver compensation to reduce self-induced ISI from the driver while the filter coefficients are activated. The coefficient setting circuit receive a combination of control bits to select the appropriate response for the driver to the various transmission media parameters. Adjustments to the driver output current are made at data run lengths exceeding certain values and subsequent adjustments are made for data run lengths exceeding larger values.
摘要翻译：具有可变FIR的可编程驱动器/均衡器使得串行链路或其他传输系统的均衡能够适应各种传输介质，特别是符号间干扰（ISI）。电流模式差分驱动电路通过在Z变换模式下工作的有限脉冲响应（FIR）滤波器耦合到传输介质。 FIR滤波器包括A和B系数设置电路，并且耦合到驱动器。驱动器电路还包括A系数电平驱动器补偿和B系数电平驱动器补偿，以在激活滤波器系数时从驱动器中减少自感应ISI。系数设置电路接收控制位的组合，以便为各种传输介质参数选择适合于驾驶员的响应。驱动器输出电流的调整是在超过某些值的数据运行长度上进行的，随后对数据运行长度超过较大值进行调整。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式