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91. 发明授权

US07969239B2 Charge pump circuit and a novel capacitor for a memory integrated circuit 有权
标题翻译：电荷泵电路和用于存储器集成电路的新型电容器
公开(公告)号：US07969239B2
公开(公告)日：2011-06-28
申请号：US12569832
申请日：2009-09-29
申请人： Hieu Van Tran , Hung Q. Nguyen , Thuan T. Vu , Anh Ly
发明人： Hieu Van Tran , Hung Q. Nguyen , Thuan T. Vu , Anh Ly
IPC分类号： H01L25/00
CPC分类号： H02M3/07 , G11C5/145
摘要： A novel capacitor for use in a charge pump circuit has a substrate with a planar surface. A first electrode is in a first plane spaced apart from the planar surface. A second electrode is adjacent to and is spaced apart from the first electrode in the first plane and is capacitively coupled thereto. A third electrode is in a second plane, spaced apart from the first plane and is capacitively coupled to the first electrode. A fourth electrode is adjacent to and spaced apart from the third electrode in the second plane and is capacitively coupled to the third electrode and capacitively coupled to the second electrode. The first and fourth electrodes are electrically connected together and the second and third electrodes are electrically connected together. In addition, a cylindrical shape electrode, and a great wall electrode, and charge pump capacitor-by-pattern-filling is disclosed. A charge pump circuit using the foregoing described capacitor has a plurality of transistors for charging the capacitor and discharging the capacitor thereby increasing the voltage of the charge pump circuit.
摘要翻译：用于电荷泵电路的新型电容器具有具有平坦表面的基板。第一电极处于与平面间隔开的第一平面中。第二电极与第一平面中的第一电极相邻并且与第一电极间隔开并且与其电容耦合。第三电极处于与第一平面间隔开的第二平面中并与第一电极电容耦合。第四电极在第二平面中与第三电极相邻并间隔开，并且电容耦合到第三电极并电容耦合到第二电极。第一和第四电极电连接在一起，第二和第三电极电连接在一起。另外，公开了圆柱形电极和长壁电极以及电荷泵电容器逐图案填充。使用上述电容器的电荷泵电路具有多个用于对电容器充电并对电容器进行放电的晶体管，从而增加电荷泵电路的电压。

92. 发明申请

US20110022905A1 Test Circuit and Method for Multilevel Cell Flash Memory 有权
标题翻译：多电平单元闪存的测试电路和方法
公开(公告)号：US20110022905A1
公开(公告)日：2011-01-27
申请号：US12899120
申请日：2010-10-06
申请人： Hieu Van Tran , Anh Ly , Sang Thanh Nguyen , Vishal Sarin , Hung O. Nguyen , William John Saiki , Loc B. Hoang
发明人： Hieu Van Tran , Anh Ly , Sang Thanh Nguyen , Vishal Sarin , Hung O. Nguyen , William John Saiki , Loc B. Hoang
IPC分类号： G11C29/00
CPC分类号： G11C11/5621 , G11C16/04 , G11C29/50 , G11C29/50004
摘要： A test device and method may be used to detect voltage, current or signals of a digital multilevel memory cell system or to test operation or performance by applying inputted voltages, currents or signals to the memory cell system.
摘要翻译：可以使用测试装置和方法来检测数字多电平存储器单元系统的电压，电流或信号，或者通过将输入的电压，电流或信号施加到存储器单元系统来测试操作或性能。

93. 发明授权

US07868604B2 Fast voltage regulators for charge pumps 有权
标题翻译：快速电压调节器
公开(公告)号：US07868604B2
公开(公告)日：2011-01-11
申请号：US11941964
申请日：2007-11-18
申请人： Hieu Van Tran , Sang Thanh Nguyen , Anh Ly , Hung Q. Nguyen , Wingfu Aaron Lau , Nasrin Jaffari , Thuan Trong Vu , Vishal Sarin , Loc B. Hoang
发明人： Hieu Van Tran , Sang Thanh Nguyen , Anh Ly , Hung Q. Nguyen , Wingfu Aaron Lau , Nasrin Jaffari , Thuan Trong Vu , Vishal Sarin , Loc B. Hoang
IPC分类号： H02M3/18
CPC分类号： H02M3/07 , G11C5/145 , H02M1/36 , H02M1/44 , Y10T307/50
摘要： A digital multilevel memory system includes a charge pump and a voltage regulator for generating regulated high voltages for various memory operations. The charge pump may include a plurality of boost circuits to boost the output of the charge pump during a fast start up. Afterwards, the boost circuits are disabled to allow the charge pump to generate high voltages without boosting. The boost circuits may be successively enabled to boost the voltage. The boost circuits may be loadless. The voltage regulator may operate in an open loop and may include a resistive divider as a reference voltage for regulating the high voltage from the charge pump. The charge pump may include spread spectrum pump clocking to reduce electromagnetic inference for capacitor or inductor on-chip charge pumping.
摘要翻译：数字多电平存储器系统包括电荷泵和用于产生用于各种存储器操作的调节高电压的电压调节器。电荷泵可以包括多个升压电路，以在快速启动期间升高电荷泵的输出。之后，升压电路被禁止，使电荷泵产生高电压而不加速。升压电路可以被连续地使能以升高电压。升压电路可以是无负载的。电压调节器可以在开环中工作，并且可以包括电阻分压器作为用于调节来自电荷泵的高电压的参考电压。电荷泵可以包括扩频泵时钟，以减少用于电容器或电感器片上电荷泵浦的电磁推理。

94. 发明授权

US07831872B2 Test circuit and method for multilevel cell flash memory 有权
标题翻译：多电平单元闪存的测试电路和方法
公开(公告)号：US07831872B2
公开(公告)日：2010-11-09
申请号：US12637365
申请日：2009-12-14
申请人： Hieu Van Tran , Anh Ly , Sang Thanh Nguyen , Vishal Sarin , Hung Q. Nguyen , William John Saiki , Loc B. Hoang
发明人： Hieu Van Tran , Anh Ly , Sang Thanh Nguyen , Vishal Sarin , Hung Q. Nguyen , William John Saiki , Loc B. Hoang
IPC分类号： G11C29/00
CPC分类号： G11C11/5621 , G11C16/04 , G11C29/50 , G11C29/50004
摘要： A test device and method may be used to detect voltage, current or signals of a digital multilevel memory cell system or to test operation or performance by applying inputted voltages, currents or signals to the memory cell system.
摘要翻译：可以使用测试装置和方法来检测数字多电平存储器单元系统的电压，电流或信号，或者通过将输入的电压，电流或信号施加到存储器单元系统来测试操作或性能。

95. 发明申请

US20100188900A1 ARRAY AND PITCH OF NON-VOLATILE MEMORY CELLS 有权
标题翻译：非易失性记忆细胞的阵列和位点
公开(公告)号：US20100188900A1
公开(公告)日：2010-07-29
申请号：US12362106
申请日：2009-01-29
申请人： Hieu Van Tran , Anh Ly , Hung Q. Nguyen , Thuan T. Vu
发明人： Hieu Van Tran , Anh Ly , Hung Q. Nguyen , Thuan T. Vu
IPC分类号： G11C16/04 , G11C16/06
CPC分类号： G11C16/10 , G11C16/0408
摘要： An array of non-volatile memory cells is arranged in a plurality of rows and columns, wherein each memory cell has at least three terminals: a first terminal for the read out of the signal from the memory cell, a second terminal to which high voltage is supplied during certain operation, and a third terminal to which low voltage is supplied in all operations. The cells in the same column have a common bit line connected to the first terminal of memory cells in the same column. The array comprises a first and second sub arrays of memory cells arranged adjacent to one another in the same row. A first decoder is positioned to one side of the first sub array in the same row as the first sub array. A second decoder is positioned to another side of the second sub array in the same row as the second sub array. A first high voltage line is connected to the second decoder and to only the second terminal of the memory cells in the same row in the first sub array. A second high voltage line, different from the first high voltage line, is connected to the second decoder and to only the second terminal of the memory cells in the same row in the second sub array. A low voltage line is connected to the first decoder and to the thirds terminal of the memory cells in the same row of the first and second sub arrays.
摘要翻译：一组非易失性存储单元被布置成多个行和列，其中每个存储单元具有至少三个端子：用于从存储单元读出信号的第一端子，高电压的第二端子在一定操作期间提供，并且在所有操作中提供低电压的第三端子。同一列中的单元具有连接到同一列中的存储器单元的第一端的公共位线。阵列包括在同一行中彼此相邻布置的存储单元的第一和第二子阵列。第一解码器位于与第一子阵列相同的行中的第一子阵列的一侧。第二解码器被定位在与第二子阵列相同的行中的第二子阵列的另一侧。第一高压线路连接到第二解码器，并且仅连接到第一子阵列中的同一行中的存储器单元的第二端子。与第一高压线不同的第二高压线路连接到第二解码器，并且仅连接到第二子阵列中同一行中的存储器单元的第二端子。低电压线连接到第一解码器和第一和第二子阵列的同一行中的存储器单元的第三端子。

96. 发明授权

US07728563B2 Fast voltage regulators for charge pumps 有权
标题翻译：快速电压调节器
公开(公告)号：US07728563B2
公开(公告)日：2010-06-01
申请号：US12340571
申请日：2008-12-19
申请人： Hieu Van Tran , Sang Thanh Nguyen , Anh Ly , Hung O. Nguyen , Wingfu Aaron Lau , Nasrin Jaffari , Thuan Trong Vu , Vishal Sarin , Loc B. Hoang
发明人： Hieu Van Tran , Sang Thanh Nguyen , Anh Ly , Hung O. Nguyen , Wingfu Aaron Lau , Nasrin Jaffari , Thuan Trong Vu , Vishal Sarin , Loc B. Hoang
IPC分类号： G05F1/613
CPC分类号： H02M3/07 , G11C5/145 , H02M1/36 , H02M1/44 , Y10T307/50
摘要： A digital multilevel memory system includes a charge pump and a voltage regulator for generating regulated high voltages for various memory operations. The charge pump may include a plurality of boost circuits to boost the output of the charge pump during a fast start up. Afterwards, the boost circuits are disabled to allow the charge pump to generate high voltages without boosting. The boost circuits may be successively enabled to boost the voltage. The boost circuits may be loadless. The voltage regulator may operate in an open loop and may include a resistive divider as a reference voltage for regulating the high voltage from the charge pump. The charge pump may include spread spectrum pump clocking to reduce electromagnetic inference for capacitor or inductor on-chip charge pumping.
摘要翻译：数字多电平存储器系统包括电荷泵和用于产生用于各种存储器操作的调节高电压的电压调节器。电荷泵可以包括多个升压电路，以在快速启动期间升高电荷泵的输出。之后，升压电路被禁止，使电荷泵产生高电压而不加速。升压电路可以被连续地使能以升高电压。升压电路可以是无负载的。电压调节器可以在开环中工作，并且可以包括电阻分压器作为用于调节来自电荷泵的高电压的参考电压。电荷泵可以包括扩频泵时钟，以减少用于电容器或电感器片上电荷泵浦的电磁推理。

97. 发明申请

US20100002509A1 INTEGRATED FLASH MEMORY SYSTEMS AND METHODS FOR LOAD COMPENSATION 有权
标题翻译：集成闪存存储器系统和负载补偿方法
公开(公告)号：US20100002509A1
公开(公告)日：2010-01-07
申请号：US12558285
申请日：2009-09-11
申请人： Hieu Van Tran
发明人： Hieu Van Tran
IPC分类号： G11C16/04 , G11C16/06 , G11C7/02
CPC分类号： G11C16/26
摘要： Systems and methods are disclosed including features that compensate for variations in the magnitude of supply voltages used in memory arrays. According to some aspects, compensation circuits may provide a tunable current-limiting load for data columns, where the load can be tuned to dynamically compensate for variations in supply voltage. In certain aspects, a compensation circuit may employ an operational amplifier configured as a voltage follower. The voltage follower compensates for any variations in supply voltage, forcing a constant voltage drop across the load element(s), thus maintaining a constant load. Other circuits may also be included, such as precharge circuits, clamp circuits, buffer circuits, trimming circuit, and sense amplifier circuits with sensed body effect. System-On-Chip integrated system aspects may include a microcontroller, a mixed IP, and a flash memory system having functionality and blocks that interface and interoperate with each other for load compensation.
摘要翻译：公开了系统和方法，其包括补偿存储器阵列中使用的电源电压的幅度变化的特征。根据一些方面，补偿电路可以为数据列提供可调谐的限流负载，其中可以调整负载来动态补偿电源电压的变化。在某些方面，补偿电路可以采用配置为电压跟随器的运算放大器。电压跟随器补偿电源电压的任何变化，迫使负载元件上的恒定电压降，从而保持恒定的负载。还可以包括其他电路，例如预充电电路，钳位电路，缓冲电路，微调电路，以及感测体效应的读出放大器电路。片上系统集成系统方面可以包括微控制器，混合IP和闪存系统，其具有彼此接口和互操作以进行负载补偿的功能和块。

98. 发明申请

US20090323415A1 FLASH MEMORY ARRAY SYSTEM INCLUDING A TOP GATE MEMORY CELL 有权
标题翻译：闪存存储器阵列系统，包括顶盖存储器单元
公开(公告)号：US20090323415A1
公开(公告)日：2009-12-31
申请号：US12507783
申请日：2009-07-22
申请人： Hieu Van Tran , Hung Quoc Nguyen , Anh Ly , Sheng-Hsiung Hsueh , Sang Thanh Nguyen , Loc B. Hoang , Steve Choi , Thuan T. Vu
发明人： Hieu Van Tran , Hung Quoc Nguyen , Anh Ly , Sheng-Hsiung Hsueh , Sang Thanh Nguyen , Loc B. Hoang , Steve Choi , Thuan T. Vu
IPC分类号： G11C16/04 , G11C16/06
CPC分类号： G11C8/10 , G11C16/0433 , G11C16/08 , G11C29/832
摘要： A memory system includes memory cells arranged in sectors. A decoder corresponding to a sector disables memory cells having a defective top gate. The decoder may include a low voltage or high voltage latch for the disabling. A top gate handling algorithm is included. The memory system may include dynamic top gate coupling. A programming algorithm and waveforms with top gate handling is included.
摘要翻译：存储器系统包括布置在扇区中的存储器单元。对应于扇区的解码器禁止具有缺陷顶门的存储单元。解码器可以包括用于禁用的低电压或高电压锁存器。包括顶栅处理算法。存储器系统可以包括动态顶栅耦合。包括具有顶栅处理的编程算法和波形。

99. 发明授权

US07616028B2 Sense amplifier for low voltage high speed sensing 有权
标题翻译：用于低电压高速感应的感应放大器
公开(公告)号：US07616028B2
公开(公告)日：2009-11-10
申请号：US11942665
申请日：2007-11-19
申请人： Hieu Van Tran , Sang Thanh Nguyen , Hung Quoc Nguyen
发明人： Hieu Van Tran , Sang Thanh Nguyen , Hung Quoc Nguyen
IPC分类号： G01R19/00
CPC分类号： G11C11/5642 , G11C7/06 , G11C7/062
摘要： A memory system includes a sense amplifier for detecting content of data memory cells by comparison with a voltage stored in a reference cell. The sense amplifier may comprise a comparator, first and second load circuits, and a low impedance circuit. A first input of the comparator is coupled to the low impedance circuit and a reference voltage node. A second input of the comparator is coupled to a data voltage node. The first load circuit loads a reference cell coupled to the reference voltage node. The second load circuit loads a data cell coupled to the data voltage node.
摘要翻译：存储器系统包括用于通过与存储在参考单元中的电压进行比较来检测数据存储单元的内容的读出放大器。读出放大器可以包括比较器，第一和第二负载电路以及低阻抗电路。比较器的第一输入耦合到低阻抗电路和参考电压节点。比较器的第二输入耦合到数据电压节点。第一负载电路加载耦合到参考电压节点的参考电池。第二负载电路加载耦合到数据电压节点的数据单元。

100. 发明申请

US20080278986A1 High-Speed and Low-Power Differential Non-Volatile Content Addressable Memory Cell and Array 有权
标题翻译：高速和低功耗差分非易失性内容可寻址存储器单元和阵列
公开(公告)号：US20080278986A1
公开(公告)日：2008-11-13
申请号：US12176281
申请日：2008-07-18
申请人： Vishal Sarin , Hieu Van Tran , Isao Nojima
发明人： Vishal Sarin , Hieu Van Tran , Isao Nojima
IPC分类号： G11C15/04
CPC分类号： G11C14/00 , G11C15/046
摘要： A differential non-volatile content addressable memory array has a differential non-volatile content addressable memory cell which uses a pair of non-volatile storage elements. Each of the non-volatile storage elements can be a split-gate floating gate transistor or a stack gate floating gate transistor having a first terminal, a second terminal, a channel therebetween and a floating gate over at least a portion of the channel to control the conduction of electrons in the channel, and a control gate. The floating gate storage transistor can be in one of two states: a first state, such as erase, in which current can flow between the first terminal and the second terminal, and a second state, such as programmed, in which substantially no current flows between the first terminal and the second terminal. A pair of differential compare data lines connects to the control gate of each of the pair of non-volatile floating gate transistors. A match line connects to the first terminal of each of the pair of non-volatile floating gate transistors to a first voltage. Finally, the second terminals of each storage element is connected to a second voltage, different from the first voltage. A current passing through the memory cell is indicative of a mis-match between the contents of the compare data lines and the contents of the storage elements.
摘要翻译：差分非易失性内容可寻址存储器阵列具有使用一对非易失性存储元件的差分非易失性内容可寻址存储器单元。每个非易失性存储元件可以是分离栅极浮栅晶体管或堆叠栅极浮栅晶体管，其具有第一端子，第二端子，其间的沟道以及通道的至少一部分上的浮置栅极以控制通道中的电子传导，以及控制栅极。浮置栅极存储晶体管可以处于以下两种状态之一：电流可以在第一端子和第二端子之间流动的第一状态，例如擦除，以及第二状态，诸如编程的，其中基本上没有电流流动在第一端子和第二端子之间。一对差分比较数据线连接到该对非易失性浮栅晶体管中的每一个的控制栅极。匹配线将一对非易失性浮栅晶体管的每一个的第一端连接到第一电压。最后，每个存储元件的第二端子被连接到与第一电压不同的第二电压。通过存储单元的电流表示比较数据线的内容与存储元件的内容之间的错误匹配。

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