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91. 发明授权

US6091110A MOSFET device having recessed gate-drain shield and method 有权
标题翻译： MOSFET器件具有凹陷的栅极 - 漏极屏蔽和方法
公开(公告)号：US6091110A
公开(公告)日：2000-07-18
申请号：US430530
申请日：1999-10-29
申请人： Francois Hebert , Szehim Ng
发明人： Francois Hebert , Szehim Ng
IPC分类号： H01L21/336 , H01L29/06 , H01L29/40 , H01L29/78
CPC分类号： H01L29/402 , H01L29/66659 , H01L29/7835
摘要： A method of fabricating a MOSFET transistor and resulting structure having a drain-gate feedback capacitance shield formed in a recess between a gate electrode and the drain region. The shield does not overlap the gate and thereby minimizes effect on the input capacitance of the transistor. The process does not require complex or costly processing since one additional non-critical mask is required with selective etch used to create the recess.
摘要翻译：一种制造MOSFET晶体管的方法，所得结构具有形成在栅极电极和漏极区域之间的凹槽中的漏极 - 栅极反馈电容屏蔽。屏蔽不与栅极重叠，从而最小化对晶体管的输入电容的影响。该方法不需要复杂或昂贵的处理，因为需要一个附加的非临界掩模，用于产生凹槽的选择性蚀刻。

92. 发明授权

US5841166A Lateral DMOS transistor for RF/microwave applications 失效
公开(公告)号：US5841166A
公开(公告)日：1998-11-24
申请号：US711495
申请日：1996-09-10
申请人： Pablo E. D'Anna , Francois Hebert
发明人： Pablo E. D'Anna , Francois Hebert
IPC分类号： H01L21/336 , H01L29/10 , H01L29/41 , H01L29/417 , H01L29/423 , H01L29/78 , H01L29/76 , H01L29/94 , H01L31/062 , H01L31/113
CPC分类号： H01L29/7816 , H01L29/1087 , H01L29/41741 , H01L29/66674 , H01L29/7801 , H01L29/1095 , H01L29/41 , H01L29/42368 , Y10S148/126
摘要： An IGFET device (lateral DMOS transistor) with reduced cell dimensions which is especially suitable for RF and microwave applications, includes a semiconductor substrate having an epitaxial layer with a device formed in a surface of the epitaxial layer. A sinker contact is provided from the surface to the epitaxial layer to the substrate for use in grounding the source region to the grounded substrate. The sinker contact is aligned with the source region and spaced from the width of the channel region whereby lateral diffusion in forming the sinker contact does not adversely affect the pitch of the cell structure. The reduced pitch increases output power and reduces parasitic capacitance whereby the device is well-suited for low side switches and as an RF/microwave power transistor.

93. 发明授权

US5385861A Planarized trench and field oxide and poly isolation scheme 失效
标题翻译：平面化沟槽和场氧化物和多晶隔离方案
公开(公告)号：US5385861A
公开(公告)日：1995-01-31
申请号：US213144
申请日：1994-03-15
申请人： Rashid Bashir , Francois Hebert , Datong Chen
发明人： Rashid Bashir , Francois Hebert , Datong Chen
IPC分类号： H01L21/762 , H01L21/763 , H01L21/76
CPC分类号： H01L21/76227 , H01L21/763 , Y10S148/05
摘要： A novel device isolation scheme for separating active regions on a semiconductor substrate by combining field oxide formation with trench isolation is disclosed. According to this scheme, shallow and deep trenches are etched into the semiconductor substrate. A layer of nitride is deposited over the entire substrate followed by a layer of poly-silicon. Oxide spacers on the poly-silicon and a photoresist mask is aligned within the oxide spacers, thereby permitting the selective etching of the poly-silicon layer. The poly-silicon layer overlying the active regions of the semiconductor substrate are etched away. Then an oxidation step is performed such that the poly-silicon layer filling the shallow trenches is oxidized while the poly-silicon filling the deep trenches remains unoxidized. The alignment of the photoresist becomes highly non-critical because of the use of the oxide spacers and fully walled junctions are provided.
摘要翻译：公开了一种用于通过组合场氧化物形成和沟槽隔离来分离半导体衬底上的有源区的新型器件隔离方案。根据该方案，将浅沟槽和深沟槽蚀刻到半导体衬底中。一层氮化物沉积在整个衬底上，随后是一层多晶硅。在多晶硅和光致抗蚀剂掩模之间的氧化物间隔物在氧化物间隔物内对准，从而允许多晶硅层的选择性蚀刻。覆盖半导体衬底的有源区的多晶硅层被蚀刻掉。然后执行氧化步骤，使得填充浅沟槽的多晶硅层被氧化，而填充深沟槽的多晶硅保持未氧化。由于使用氧化物间隔物并且提供了完全的壁结，因此光致抗蚀剂的取向变得非常关键。

94. 发明授权

US08815641B2 Diamond SOI with thin silicon nitride layer and related methods 有权
标题翻译：具有薄氮化硅层的金刚石SOI及相关方法
公开(公告)号：US08815641B2
公开(公告)日：2014-08-26
申请号：US12719988
申请日：2010-03-09
申请人： Rick C. Jerome , Francois Hebert , Craig McLachlan , Kevin Hoopingarner
发明人： Rick C. Jerome , Francois Hebert , Craig McLachlan , Kevin Hoopingarner
IPC分类号： H01L29/06 , H01L21/20
CPC分类号： H01L21/02532 , H01L21/02381 , H01L21/02444 , H01L21/02488 , H01L21/02505 , H01L21/02521 , H01L21/76254 , H01L23/3732 , H01L2924/0002 , H01L2924/00
摘要： A method and structure for a semiconductor device including a thin nitride layer formed between a diamond SOI layer and device silicon layer to block diffusion of ions and improve lifetime of the device silicon.
摘要翻译：一种半导体器件的方法和结构，包括在金刚石SOI层和器件硅层之间形成的薄氮化物层，以阻止离子的扩散并提高器件硅的寿命。

95. 发明授权

US08637360B2 Power devices with integrated protection devices: structures and methods 有权
标题翻译：具有集成保护装置的电力设备：结构和方法
公开(公告)号：US08637360B2
公开(公告)日：2014-01-28
申请号：US12950202
申请日：2010-11-19
申请人： Francois Hebert
发明人： Francois Hebert
IPC分类号： H01L21/338
CPC分类号： H01L27/0255 , H01L21/8258 , H01L27/0629 , H01L27/0688 , H01L29/0619 , H01L29/0653 , H01L29/1075 , H01L29/2003 , H01L29/41766 , H01L29/66136 , H01L29/66143 , H01L29/66462 , H01L29/7786 , H01L29/8611 , H01L29/872
摘要： Exemplary embodiments provide structures and methods for power devices with integrated clamp structures. The integration of clamp structures can protect the power device, e.g., from electrical overstress (EOS). In one embodiment, active devices can be formed over a substrate, while a clamp structure can be integrated outside the active regions of the power device, for example, under the active regions and/or inside the substrate. Integrating clamp structure outside active regions of power devices can maximize the active area for a given die size and improve robustness of the clamped device since the current will spread in the substrate by this integration.
摘要翻译：示例性实施例提供了具有集成钳位结构的功率器件的结构和方法。夹紧结构的集成可以保护功率器件，例如不受电力过应力（EOS）的影响。在一个实施例中，有源器件可以形成在衬底上，而钳位结构可以集成在功率器件的有源区域外部，例如在有源区域下方和/或衬底内部。在功率器件的有源区域之外集成钳位结构可以使给定管芯尺寸的有效面积最大化，并且改善钳位器件的鲁棒性，因为电流将通过该积分在衬底中扩展。

96. 发明申请

US20140001588A1 OPTICAL SENSORS DEVICES INCLUDING A HYBRID OF WAFER-LEVEL INORGANIC DIELECTRIC AND ORGANIC COLOR FILTERS 审中-公开
标题翻译：光传感器设备，包括水平无机电介质和有机彩色滤光片的混合
公开(公告)号：US20140001588A1
公开(公告)日：2014-01-02
申请号：US13535925
申请日：2012-06-28
申请人： Michael I-Shan Sun , Francois Hebert , Kenneth C. Dyer , Eric S. Lee
发明人： Michael I-Shan Sun , Francois Hebert , Kenneth C. Dyer , Eric S. Lee
IPC分类号： H01L27/14 , H01L31/18
CPC分类号： H01L27/14621
摘要： Monolithic optical sensor devices, and methods for fabricating such devices, are described herein. In an embodiment, a semiconductor wafer substrate includes a plurality of photodetector (PD) regions. A wafer-level inorganic dielectric optical filter is deposited and thereby formed over at least a subset of the plurality of PD regions. One or more wafer-level organic color filter(s) is/are deposited and thereby formed on one or more selected portion(s) of the wafer-level inorganic dielectric optical filter that is/are over selected ones of the PD regions. For example, an organic red filter, an organic green filter and an organic blue filter can be over, respectively, portions of the wafer-level inorganic dielectric optical filter that are over first, second and third PD regions.
摘要翻译：本文描述了单片光学传感器装置及其制造方法。在一个实施例中，半导体晶片衬底包括多个光电检测器（PD）区域。沉积晶片级无机介质光学滤波器，从而形成在多个PD区域的至少一个子集上。沉积一个或多个晶片级有机彩色滤光片，从而在晶片级无机介质光学滤波器的一个或多个选定的部分上形成PD选择的一部分。例如，有机红色滤色器，有机绿色滤色器和有机蓝色滤色器可以分别结束在第一，第二和第三PD区域之上的晶片级无机介质滤光器的部分。

97. 发明授权

US08492225B2 Integrated trench guarded schottky diode compatible with powerdie, structure and method 有权
标题翻译：集成沟槽保护肖特基二极管兼容电源，结构和方法
公开(公告)号：US08492225B2
公开(公告)日：2013-07-23
申请号：US12938589
申请日：2010-11-03
申请人： Dev Alok Girdhar , Francois Hebert
发明人： Dev Alok Girdhar , Francois Hebert
IPC分类号： H01L21/336
CPC分类号： H01L27/0629 , H01L27/088 , H01L29/4236 , H01L29/66621 , H01L29/7834 , H01L2924/0002 , H01L2924/00
摘要： A method and structure for a voltage converter including a trench field effect transistor (FET) and a trench guarded Schottky diode which is integrated with the trench FET. In an embodiment, a voltage converter can include a lateral FET, a trench FET, and a trench guarded Schottky diode integrated with the trench FET. A method to form a voltage converter can include the formation of a trench FET gate, a trench guarded Schottky diode gate, and a lateral FET gate using a single conductive layer such as a polysilicon layer.
摘要翻译：一种电压转换器的方法和结构，包括与沟槽FET集成的沟槽场效应晶体管（FET）和沟槽保护肖特基二极管。在一个实施例中，电压转换器可以包括横向FET，沟槽FET和与沟槽FET集成的沟槽保护肖特基二极管。形成电压转换器的方法可以包括使用诸如多晶硅层的单个导电层形成沟槽FET栅极，沟槽保护肖特基二极管栅极和横向FET栅极。

98. 发明申请

US20130043940A1 BACK-TO-BACK STACKED DIES 有权
标题翻译：背靠背堆叠的DIES
公开(公告)号：US20130043940A1
公开(公告)日：2013-02-21
申请号：US13358718
申请日：2012-01-26
申请人： Francois Hebert , Steven R. Rivet , Michael Althar , Peter Oaklander
发明人： Francois Hebert , Steven R. Rivet , Michael Althar , Peter Oaklander
IPC分类号： H01L25/16 , H01L23/495 , H01L21/50 , H01L23/498
CPC分类号： H01L25/18 , H01L23/3107 , H01L23/3114 , H01L23/367 , H01L23/3732 , H01L23/4334 , H01L23/49517 , H01L23/49541 , H01L23/49562 , H01L23/49575 , H01L23/645 , H01L24/16 , H01L24/17 , H01L24/29 , H01L24/32 , H01L24/45 , H01L24/48 , H01L24/49 , H01L24/73 , H01L25/0657 , H01L25/16 , H01L2224/05553 , H01L2224/13147 , H01L2224/16245 , H01L2224/291 , H01L2224/2919 , H01L2224/32013 , H01L2224/32145 , H01L2224/45014 , H01L2224/45124 , H01L2224/45144 , H01L2224/45147 , H01L2224/48091 , H01L2224/48106 , H01L2224/48137 , H01L2224/48247 , H01L2224/48472 , H01L2224/49111 , H01L2224/49171 , H01L2224/73253 , H01L2224/73265 , H01L2224/83801 , H01L2224/83855 , H01L2224/92247 , H01L2225/0651 , H01L2225/06517 , H01L2225/06558 , H01L2225/06589 , H01L2924/01015 , H01L2924/01029 , H01L2924/10162 , H01L2924/12032 , H01L2924/1306 , H01L2924/13064 , H01L2924/13091 , H01L2924/1425 , H01L2924/14253 , H01L2924/1426 , H01L2924/181 , Y10T29/49121 , H01L2924/00012 , H01L2924/00014 , H01L2924/0665 , H01L2924/014 , H01L2924/00
摘要： Embodiments disclosed herein provide for a circuit including first die having an active side and a backside, wherein the first die is flip-chip mounted to a carrier. The circuit also includes a second die stacked on the backside of the first die, wherein the second die is stacked on the first die such that a backside of the second die is facing the backside of the first die and an active side of the second die faces away from the first die.
摘要翻译：本文公开的实施例提供了包括具有有源侧和背侧的第一管芯的电路，其中第一管芯被倒装芯片安装到载体上。电路还包括堆叠在第一管芯的背面上的第二管芯，其中第二管芯堆叠在第一管芯上，使得第二管芯的背面面向第一管芯的背面，第二管芯的有源侧面对远离第一个模具。

99. 发明申请

US20120256193A1 MONOLITHIC INTEGRATED CAPACITORS FOR HIGH-EFFICIENCY POWER CONVERTERS 审中-公开
标题翻译：用于高效电力转换器的单片集成电容器
公开(公告)号：US20120256193A1
公开(公告)日：2012-10-11
申请号：US13165396
申请日：2011-06-21
申请人： Francois Hebert , Stephen J. Gaul , Shea Petricek
发明人： Francois Hebert , Stephen J. Gaul , Shea Petricek
IPC分类号： H01L29/02 , H01L29/06 , H01L21/02 , H01L29/92
CPC分类号： H01L23/5223 , H01L21/823418 , H01L23/3107 , H01L23/49562 , H01L23/49575 , H01L24/06 , H01L24/48 , H01L24/49 , H01L24/73 , H01L27/0629 , H01L27/088 , H01L28/60 , H01L29/402 , H01L29/4175 , H01L29/42368 , H01L29/456 , H01L29/7813 , H01L29/7835 , H01L2224/04042 , H01L2224/05554 , H01L2224/0603 , H01L2224/32245 , H01L2224/48137 , H01L2224/48247 , H01L2224/48472 , H01L2224/49111 , H01L2224/73265 , H01L2924/00014 , H01L2924/01322 , H01L2924/13091 , H01L2924/30107 , H01L2924/3025 , H01L2924/00012 , H01L2924/00 , H01L2924/00011 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： A semiconductor structure such as a power converter with an integrated capacitor is provided, and comprises a semiconductor substrate, a high-side output power device over the substrate at a first location, and a low-side output power device over the substrate at a second location adjacent to the first location. A first metal layer is over the high-side output power device and electrically coupled to the high-side output power device, and a second metal layer is over the low-side output power device and electrically coupled to the low-side output power device. A dielectric layer is over a portion of the first metal layer and a portion of the second metal layer, and a top metal layer is over the dielectric layer. The integrated capacitor comprises a first bottom electrode that includes the portion of the first metal layer, a second bottom electrode that includes the portion of the second metal layer, the dielectric layer over the portions of the first and second metal layers, and a top electrode that includes the top metal layer over the dielectric layer.
摘要翻译：提供了诸如具有集成电容器的功率转换器的半导体结构，并且包括半导体衬底，在第一位置处的衬底上的高侧输出功率器件和在第二位置处的衬底上的低侧输出功率器件位置与第一个位置相邻。第一金属层位于高侧输出功率器件的上方并且电耦合到高侧输出功率器件，并且第二金属层在低侧输出功率器件的上方并且电耦合到低侧输出功率器件。电介质层位于第一金属层的一部分和第二金属层的一部分上，并且顶部金属层在电介质层的上方。集成电容器包括包括第一金属层的部分的第一底部电极，包括第二金属层的部分的第二底部电极，第一和第二金属层的部分上的电介质层，以及顶部电极其包括在电介质层上的顶部金属层。

100. 发明授权

US08242510B2 Monolithic integration of gallium nitride and silicon devices and circuits, structure and method 有权
标题翻译：氮化镓和硅器件与电路的整体集成，结构和方法
公开(公告)号：US08242510B2
公开(公告)日：2012-08-14
申请号：US12946669
申请日：2010-11-15
申请人： Francois Hebert
发明人： Francois Hebert
IPC分类号： H01L29/15
CPC分类号： H01L29/7787 , H01L21/0242 , H01L21/0245 , H01L21/0254 , H01L21/02658 , H01L21/76281 , H01L21/8258 , H01L27/085 , H01L29/2003 , H01L29/66462
摘要： A structure and method for a semiconductor device includes a silicon device layer and a gallium nitride (GaN) device layer. In an embodiment, the silicon device layer and the GaN device layer have upper surfaces which are coplanar with each other. In another embodiment, the GaN device layer does not directly underlie the silicon device layer, and the silicon device layer does not directly underlie the GaN device layer. The semiconductor device can further include a silicon-based semiconductor device formed on and/or within the silicon device layer, and a nitride-based semiconductor device formed on and/or within the GaN device layer. The GaN device layer can include a plurality of layers which can be formed as conformal blanket layers and then planarized, or which can be selectively formed then planarized.
摘要翻译：半导体器件的结构和方法包括硅器件层和氮化镓（GaN）器件层。在一个实施例中，硅器件层和GaN器件层具有彼此共面的上表面。在另一个实施例中，GaN器件层不直接位于硅器件层之下，并且硅器件层不直接位于GaN器件层的下面。半导体器件还可以包括形成在硅器件层上和/或内部的硅基半导体器件，以及形成在GaN器件层上和/或内部的氮化物基半导体器件。 GaN器件层可以包括可以形成为保形覆盖层然后平坦化的多个层，或者可以选择性地形成，然后进行平面化。

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