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91. 发明授权

US07544987B2 High-k dielectric materials and processes for manufacturing them 有权
公开(公告)号：US07544987B2
公开(公告)日：2009-06-09
申请号：US11070415
申请日：2005-03-02
申请人： Jiong-Ping Lu , Ming-Jang Hwang
发明人： Jiong-Ping Lu , Ming-Jang Hwang
IPC分类号： H01L27/108
CPC分类号： C23C16/34 , C23C16/56 , H01L21/31604 , H01L21/31637 , H01L21/31683 , H01L27/1085 , H01L28/40 , H01L28/57
摘要： High dielectric films of mixed transition metal oxides of titanium and tungsten, or titanium and tantalum, are formed by sequential chemical vapor deposition (CVD) of the respective nitrides and annealing in the presence of oxygen to densify and oxidize the nitrides. The resulting film is useful as a capacitative cell and resists oxygen diffusion to the underlying material, has high capacitance and low current leakage.

92. 发明申请

US20080176345A1 Ebeam inspection for detecting gate dielectric punch through and/or incomplete silicidation or metallization events for transistors having metal gate electrodes 审中-公开
标题翻译：用于检测栅极电介质穿透的Ebeam检查和/或用于具有金属栅电极的晶体管的不完全硅化或金属化事件
公开(公告)号：US20080176345A1
公开(公告)日：2008-07-24
申请号：US11655483
申请日：2007-01-19
申请人： Shaofeng Yu , Richard L. Guldi , Jiong-Ping Lu , Freidoon Mehrad , Jae Hyun Park
发明人： Shaofeng Yu , Richard L. Guldi , Jiong-Ping Lu , Freidoon Mehrad , Jae Hyun Park
IPC分类号： H01L21/66
CPC分类号： H01L22/14
摘要： Gate dielectric punch through and/or incomplete silicidation or metallization events that may occur during transistor formation are identified. The events are identified just after gate electrodes are formed in order to characterize the degree of faulty transistors for process control purposes and to scrap product if sufficiently defective so that subsequent resources are not unnecessarily expended. An electron beam or ebeam is directed at locations of a workpiece whereon on or more transistors are formed. Electrons that are resultantly emitted from these locations are detected and used to develop respective gray level values (GLV's). Gate dielectric punch through and/or incomplete silicidation or metallization events are identified by finding high or low GLV's relative to neighboring areas.
摘要翻译：识别在晶体管形成期间可能发生的栅极电介质穿透和/或不完全的硅化或金属化事件。在形成栅极电极之后才识别事件，以便表征用于过程控制目的的故障晶体管的程度，并且如果充分有缺陷，则废弃产品，使得后续资源不会被不必要地消耗。电子束或ebeam被引导到其上形成有多个晶体管的工件的位置。从这些位置发射的电子被检测并用于开发各自的灰度值（GLV's）。通过相对于相邻区域发现高或低GLV来鉴定栅极电介质穿透和/或不完全硅化或金属化事件。

93. 发明授权

US07341933B2 Method for manufacturing a silicided gate electrode using a buffer layer 有权
标题翻译：使用缓冲层制造硅化栅电极的方法
公开(公告)号：US07341933B2
公开(公告)日：2008-03-11
申请号：US11007569
申请日：2004-12-08
申请人： Shaofeng Yu , Haowen Bu , Jiong-Ping Lu , Lindsey Hall
发明人： Shaofeng Yu , Haowen Bu , Jiong-Ping Lu , Lindsey Hall
IPC分类号： H01L21/3205
CPC分类号： H01L29/66545 , H01L29/51 , H01L29/66507 , H01L29/6656 , H01L29/6659 , H01L29/7833
摘要： The present invention provides a method for manufacturing a semiconductor device and a method for manufacturing an integrated circuit. The method for manufacturing the semiconductor device, among other steps, includes providing a capped polysilicon gate electrode (290) over a substrate (210), the capped polysilicon gate electrode (290) including a buffer layer (260) located between a polysilicon gate electrode layer (250) and a protective layer (270). The method further includes forming source/drain regions (710) in the substrate (210) proximate the capped polysilicon gate electrode (290), removing the protective layer (270) and the buffer layer (260), and siliciding the polysilicon gate electrode layer (250) to form a silicided gate electrode (1110).
摘要翻译：本发明提供一种制造半导体器件的方法和集成电路的制造方法。制造半导体器件的方法以及其他步骤包括在衬底（210）上提供封盖的多晶硅栅电极（290），封装的多晶硅栅电极（290）包括位于多晶硅栅电极层（250）和保护层（270）。该方法还包括在靠近封盖的多晶硅栅极（290）的基板（210）中形成源/漏区（710），去除保护层（270）和缓冲层（260），并且将多晶硅栅电极层（250），以形成硅化物栅电极（1110）。

94. 发明申请

US20060258091A1 Novel method for manufacturing a semiconductor device containing metal silicide regions 有权
标题翻译：用于制造包含金属硅化物区域的半导体器件的新方法
公开(公告)号：US20060258091A1
公开(公告)日：2006-11-16
申请号：US11127669
申请日：2005-05-12
申请人： Juanita DeLoach , Lindsey Hall , Lance Robertson , Jiong-Ping Lu , Donald Miles
发明人： Juanita DeLoach , Lindsey Hall , Lance Robertson , Jiong-Ping Lu , Donald Miles
IPC分类号： H01L21/336
CPC分类号： H01L21/28052 , H01L21/28518 , H01L29/665
摘要： The present invention provides a method for manufacturing a semiconductor device. In one embodiment of the present invention, without limitation, the method for manufacturing the semiconductor device includes forming a gate structure (120) over a substrate (110) and forming source/drain regions (190) in the substrate (110) proximate the gate structure (120). The method further includes forming fluorine containing regions (220) in the source/drain regions (190) employing a fluorine containing plasma using a power level of less than about 75 Watts, forming a metal layer (310) over the substrate (110) and fluorine containing regions (220), and reacting the metal layer (310) with the fluorine containing regions (220) to form metal silicide regions (410) in the source/drain regions (190).
摘要翻译：本发明提供一种制造半导体器件的方法。在本发明的一个实施例中，但不限于，用于制造半导体器件的方法包括在衬底（110）上形成栅极结构（120）并且在靠近栅极的衬底（110）中形成源/漏区（190）结构（120）。该方法还包括在源极/漏极区（190）中使用含氟等离子体，使用小于约75瓦特的功率电平形成含氟区域（220），在基底（110）上形成金属层（310），以及含氟区域（220），并且使金属层（310）与含氟区域（220）反应以在源极/漏极区域（190）中形成金属硅化物区域（410）。

95. 发明授权

US07029967B2 Silicide method for CMOS integrated circuits 有权
标题翻译： CMOS集成电路的硅化法
公开(公告)号：US07029967B2
公开(公告)日：2006-04-18
申请号：US10896599
申请日：2004-07-21
申请人： Song Zhao , Sue E. Crank , Amitava Chatterjee , Kaiping Liu , Jiong-Ping Lu , Donald S. Miles , Duofeng Yue , Lance S. Robertson
发明人： Song Zhao , Sue E. Crank , Amitava Chatterjee , Kaiping Liu , Jiong-Ping Lu , Donald S. Miles , Duofeng Yue , Lance S. Robertson
IPC分类号： H01L21/8238 , H01L21/331
CPC分类号： H01L21/823814 , H01L21/26506 , H01L21/28518 , H01L21/823835 , H01L29/665
摘要： A method for forming metal silicide regions in source and drain regions (160, 170) is described. Prior to the thermal annealing of the source and drain regions (160, 170), germanium is implanted into a semiconductor substrate adjacent to sidewall structures (90, 95) formed adjacent gate structures (60, 70). The position of the implanted germanium species in the semiconductor substrate will overlap the source and drain regions (160, 170). Following thermal annealing of the source and drain regions (160, 170), the implanted germanium prevents the formation of metal silicide spikes.
摘要翻译：描述了在源区和漏区（160,170）中形成金属硅化物区域的方法。在源极和漏极区域（160,170）的热退火之前，将锗注入到与栅极结构（60,70）相邻形成的侧壁结构（90,95）附近的半导体衬底中。植入的锗物质在半导体衬底中的位置将与源区和漏区（160,170）重叠。在源极和漏极区域（160,170）的热退火之后，注入的锗防止形成金属硅化物尖峰。

96. 发明申请

US20060040438A1 Method for improving the thermal stability of silicide 审中-公开
标题翻译：改善硅化物热稳定性的方法
公开(公告)号：US20060040438A1
公开(公告)日：2006-02-23
申请号：US10920547
申请日：2004-08-17
申请人： Jiong-Ping Lu , Jiejie Xu
发明人： Jiong-Ping Lu , Jiejie Xu
IPC分类号： H01L21/8234 , H01L21/4763 , H01L21/44 , H01L21/336
CPC分类号： H01L21/28052 , H01L21/265 , H01L21/28518 , H01L21/823835 , H01L29/665 , H01L29/6656 , H01L29/6659 , H01L29/7833
摘要： An embodiment of the invention is a method of making a transistor by performing an ion implant on a gate electrode layer 110. The method may include forming an interface layer 200 over the semiconductor substrate 20 and performing an anneal to create a silicide 190 on the top surface of the gate electrode 110.
摘要翻译：本发明的实施例是通过在栅电极层110上执行离子注入来制造晶体管的方法。该方法可以包括在半导体衬底20上形成界面层200并执行退火以在栅电极110的顶表面上产生硅化物190。

97. 发明申请

US20060024882A1 Method for manufacturing a semiconductor device having silicided regions 有权
标题翻译：制造具有硅化物区域的半导体器件的方法
公开(公告)号：US20060024882A1
公开(公告)日：2006-02-02
申请号：US10901756
申请日：2004-07-29
申请人： Jiong-Ping Lu , Clint Montgomery , Lindsey Hall , Donald Miles , Duofeng Yue , Thomas Bonifield
发明人： Jiong-Ping Lu , Clint Montgomery , Lindsey Hall , Donald Miles , Duofeng Yue , Thomas Bonifield
IPC分类号： H01L21/336
CPC分类号： H01L21/823835 , H01L21/02057 , H01L21/0206 , H01L21/02068 , H01L27/0629 , H01L29/665 , H01L29/6656 , H01L29/6659 , H01L29/7833
摘要： The present invention provides a method for manufacturing a semiconductor device, and a method for manufacturing an integrated circuit including the semiconductor devices. The method for manufacturing a semiconductor device (100) , among other steps, includes forming a gate structure (120) over a substrate (110) and forming source/drain regions (190) in the substrate (110) proximate the gate structure (120). The method further includes subjecting the gate structure (120) and substrate (110) to a dry etch process and placing fluorine in the source/drain regions to form fluorinated source/drains (320) subsequent to subjecting the gate structure (120) and substrate (110) to the dry etch process. Thereafter, the method includes forming metal silicide regions (510, 520) in the gate structure (120) and the fluorinated source/drains (320).
摘要翻译：本发明提供一种半导体器件的制造方法以及包括该半导体器件的集成电路的制造方法。除了其他步骤之外，用于制造半导体器件（100）的方法包括在衬底（110）上形成栅极结构（120）并且在栅极结构（120）附近的衬底（110）中形成源极/漏极区域（190））。该方法还包括对栅极结构（120）和衬底（110）进行干蚀刻工艺，并且在将栅极结构（120）和衬底（120）经受栅极结构（120）和衬底（110）到干蚀刻工艺。此后，该方法包括在栅极结构（120）和氟化源极/漏极（320）中形成金属硅化物区域（510,520）。

98. 发明申请

US20060019478A1 Silicide method for CMOS integrated circuits 有权
公开(公告)号：US20060019478A1
公开(公告)日：2006-01-26
申请号：US10896599
申请日：2004-07-21
申请人： Song Zhao , Sue Crank , Amitava Chatterjee , Kaiping Liu , Jiong-Ping Lu , Donald Miles , Duofeng Yue , Lance Robertson
发明人： Song Zhao , Sue Crank , Amitava Chatterjee , Kaiping Liu , Jiong-Ping Lu , Donald Miles , Duofeng Yue , Lance Robertson
IPC分类号： H01L21/28
CPC分类号： H01L21/823814 , H01L21/26506 , H01L21/28518 , H01L21/823835 , H01L29/665
摘要： A method for forming metal silicide regions in source and drain regions (160, 170) is described. Prior to the thermal annealing of the source and drain regions (160, 170), germanium is implanted into a semiconductor substrate adjacent to sidewall structures (90, 95) formed adjacent gate structures (60, 70). The position of the implanted germanium species in the semiconductor substrate will overlap the source and drain regions (160, 170). Following thermal annealing of the source and drain regions (160, 170), the implanted germanium prevents the formation of metal silicide spikes.

99. 发明申请

US20060014393A1 Process method to facilitate silicidation 有权
标题翻译：硅化方法
公开(公告)号：US20060014393A1
公开(公告)日：2006-01-19
申请号：US10894374
申请日：2004-07-19
申请人： Jiong-Ping Lu , Freidoon Mehrad , Lindsey Hall , Vivian Liu , Clint Montgomery , Scott Johnson
发明人： Jiong-Ping Lu , Freidoon Mehrad , Lindsey Hall , Vivian Liu , Clint Montgomery , Scott Johnson
IPC分类号： H01L21/302
CPC分类号： H01L21/28518 , H01L21/02046 , H01L21/0206 , H01L21/28052 , H01L29/665
摘要： The present invention substantially removes dry etch residue from a dry plasma etch process 110 prior to depositing a cobalt layer 124 on silicon substrate and/or polysilicon material. Subsequently, one or more annealing processes 128 are performed that cause the cobalt to react with the silicon thereby forming cobalt silicide regions. The lack of dry etch residue remaining between the deposited cobalt and the underlying silicon permits the cobalt silicide regions to be formed substantially uniform with a desired silicide sheet and contact resistance. The dry etch residue is substantially removed by performing a first cleaning operation 112 and then an extended cleaning operation 114 that includes a suitable cleaning solution. The first cleaning operation typically removes some, but not all of the dry etch residue. The extended cleaning operation 114 is performed at a higher temperature and/or for an extended duration and substantially removes dry etch residue remaining after the first cleaning operation 112.
摘要翻译：本发明在将钴层124沉积在硅衬底和/或多晶硅材料上之前基本上从干等离子体蚀刻工艺110去除干蚀刻残留物。随后，进行一个或多个退火工艺128，其使钴与硅反应，从而形成硅化钴区域。残留在沉积的钴和下面的硅之间的干蚀刻残留物的缺乏允许用期望的硅化物片和接触电阻基本上均匀地形成硅化钴区域。通过执行第一清洁操作112，然后进行包括合适的清洁溶液的延长清洁操作114，基本上去除了干蚀刻残留物。第一次清洁操作通常去除一些但不是全部的干蚀刻残留物。延长的清洁操作114在更高的温度和/或延长的持续时间内进行，并且基本上去除了在第一清洁操作112之后残留的干蚀刻残留物。

100. 发明申请

US20050260841A1 Integration scheme for using silicided dual work function metal gates 有权
标题翻译：使用硅化双功能金属门的集成方案
公开(公告)号：US20050260841A1
公开(公告)日：2005-11-24
申请号：US10851750
申请日：2004-05-20
申请人： Jiong-Ping Lu , Gregory Shinn , Ping Jiang
发明人： Jiong-Ping Lu , Gregory Shinn , Ping Jiang
IPC分类号： H01L21/02 , H01L21/28 , H01L21/3205 , H01L21/336 , H01L21/4763 , H01L21/8238 , H01L27/08
CPC分类号： H01L29/66507 , H01L21/28097 , H01L21/823835 , H01L21/823842 , H01L27/0811 , H01L28/60
摘要： The present invention provides a method for manufacturing a semiconductor device and a method for manufacturing an integrated circuit including the semiconductor device. The method for manufacturing the semiconductor device, among other possible steps, includes forming a polysilicon gate electrode (250) over a substrate (210) and forming source/drain regions (610) in the substrate (210) proximate the polysilicon gate electrode (250). The method further includes forming a protective layer (710) over the source/drain regions (610) and the polysilicon gate electrode (250), then removing the protective layer (710) from over a top surface of the polysilicon gate electrode (250) while leaving the protective layer (710) over the source/drain regions (250). After the protective layer (710) has been removed from over the top surface of the polysilicon gate electrode (250), the polysilicon gate electrode (250) is silicided to form a silicided gate electrode (1310). The protective layer (710) is also removed from over the source/drain regions (610) and source/drain contact regions (1610) are formed.
摘要翻译：本发明提供一种制造半导体器件的方法及其制造方法，该集成电路包括该半导体器件。制造半导体器件的方法以及其它可能的步骤包括在衬底（210）上形成多晶硅栅电极（250），并在接近多晶硅栅电极（250）的衬底（210）中形成源/漏区（610））。该方法还包括在源极/漏极区域（610）和多晶硅栅电极（250）之上形成保护层（710），然后从多晶硅栅电极（250）的顶表面上方移除保护层（710）同时将保护层（710）留在源/漏区（250）上。在保护层（710）已从多晶硅栅电极（250）的顶表面上方移除之后，多晶硅栅电极（250）被硅化以形成硅化栅电极（1310）。保护层（710）也从源极/漏极区域（610）上去除并形成源极/漏极接触区域（1610）。

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