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    • 91. 发明授权
      US5980349A Anodically-bonded elements for flat panel displays 失效
    • Anodically-bonded elements for flat panel displays
    • 用于平板显示器的阳极粘接元件
    • US5980349A
    • 1999-11-09
    • US856382
    • 1997-05-14
    • James J. Hofmann , Jason B. Elledge , Zhong-Yi Xia , David A. Cathey
    • James J. Hofmann , Jason B. Elledge , Zhong-Yi Xia , David A. Cathey
    • H01J9/18 , H01J9/24 , H01J9/00
    • H01J9/242 , H01J9/185 , H01J2329/8625 , H01J2329/863
    • A process is disclosed for anodically bonding an array of spacer columns to one of the inner major faces on one of the generally planar plates of an evacuated, flat-panel video display. The process includes the steps of: providing a generally planar plate having a plurality of spacer column attachment sites; providing electrical interconnection between all attachment sites; coating each attachment site with a patch of oxidizable material; providing an array of unattached permanent glass spacer columns, each unattached permanent spacer columns being of uniform length and being positioned longitudinally perpendicular to a single plane, with the plane intersecting the midpoint of each unattached spacer column; positioning the array such that an end of one permanent spacer column is in contact with the oxidizable material patch at each attachment site; and anodically bonding the contacting end of each permanent spacer column to the oxidizable material layer. The invention also includes an evacuated flat panel display having spacer structures which are anodically bonded to an internal major face of the display, as well as a face plate assembly manufactured by the aforestated process.
    • 公开了一种用于将隔离柱阵列阳极结合到抽空的平板显示器的一个平面板上的内主表面之一的工艺。 该方法包括以下步骤：提供具有多个间隔柱附着位点的大致平面的板; 提供所有附件位置之间的电气互连; 用一块可氧化材料涂覆每个附着部位; 提供一组未连接的永久性玻璃间隔柱，每个未连接的永久间隔柱具有均匀的长度并且纵向垂直于单个平面定位，其中平面与每个未连接的间隔柱的中点相交; 定位阵列使得一个永久间隔柱的末端在每个附着位置与可氧化材料贴片接触; 并将每个永久间隔柱的接触端阳极结合到可氧化材料层上。 本发明还包括具有阳极结合到显示器的内部主面的间隔结构的抽真空平板显示器以及通过前述方法制造的面板组件。
    • 基本信息 添加关注 加入工作空间 PDF全文 PDF下载 全文下载 相似专利 双屏查看 权利要求书 说明书全文 Global Dossier Espacenet 法律信息 同族专利 专利引用
    • 98. 发明授权
      US5328810A Method for reducing, by a factor or 2.sup.-N, the minimum masking pitch of a photolithographic process 失效
    • Method for reducing, by a factor or 2.sup.-N, the minimum masking pitch of a photolithographic process
    • 降低光刻工艺的最小掩蔽间距的因子或2-N的方法
    • US5328810A
    • 1994-07-12
    • US981976
    • 1992-11-25
    • Tyler A. Lowrey , Randal W. Chance , David A. Cathey
    • Tyler A. Lowrey , Randal W. Chance , David A. Cathey
    • H01L21/027 , H01L21/033 , H01L21/308 , G03C5/00
    • H01L21/3088 , H01L21/0271 , H01L21/0273 , H01L21/0337 , H01L21/0338 , H01L21/3086 , Y10S148/106
    • The process starts with a primary mask, which may be characterized as a pattern of parallel, photoresist strips having substantially vertical edges, each having a minimum feature width F, and being separated from neighboring strips by a minimum space width which is also approximately equal to F. From this primary mask, a set of expendable mandrel strips is created either directly or indirectly. The set of mandrel strips may be characterized as a pattern of parallel strips, each having a feature width of F/2, and with neighboring strips being spaced from one another by a space width equal to 3/2F. A conformal stringer layer is then deposited. The stringer layer material is selected such that it may be etched with a high degree of selectivity with regard to both the mandrel strips and an underlying layer which will ultimately be patterned using a resultant, reduced-pitch mask. The stringer layer is then anisotropically etched to the point where the top of each mandrel strip is exposed. The mandrel strips are then removed with an appropriate etch. A pattern of stringer strips remains which can then be used as a half-pitch mask to pattern the underlying layer. This process may also be repeated, starting with the half-pitch mask and creating a quarter-pitch mask, etc. As can be seen, this technique permits a reduction in the minimum pitch of the primary mask by a factor of 2.sup.-N (where N is an integer 1, 2, 3, . . . ).
    • 该过程从初始掩模开始，其可以被表征为具有基本垂直边缘的平行的光致抗蚀剂条带的图案，每个具有最小特征宽度F，并且与相邻条带分开最小空间宽度，其最大空间宽度也近似等于 F.从这个主要面罩，直接或间接地创建一组消耗性的芯棒条。 芯棒条的组可以被表征为平行条带的图案，每个条带具有F / 2的特征宽度，并且相邻条带彼此间隔开等于3 / 2F的空间宽度。 然后沉积保形纵梁层。 选择桁条层材料，使得可以以相对于芯棒条和下一层的高度选择性蚀刻，其将最终使用所得到的减少节距的掩模进行图案化。 然后将纵梁层各向异性地蚀刻到每个芯棒条的顶部暴露的点。 然后用适当的蚀刻去除心轴条。 留下一条桁条条纹，然后可以将其作为半间距掩模用于对下层进行图案化。 该过程也可以重复，从半间距掩模开始并产生四分之一间距掩模等。可以看出，该技术允许将初级掩模的最小间距减小2-N倍（ 其中N是整数1,2,3，...）。
    • 基本信息 添加关注 加入工作空间 PDF全文 PDF下载 全文下载 相似专利 双屏查看 权利要求书 说明书全文 Global Dossier Espacenet 法律信息 同族专利 专利引用
    • 99. 发明授权
      US5298463A Method of processing a semiconductor wafer using a contact etch stop 失效
    • Method of processing a semiconductor wafer using a contact etch stop
    • 使用接触蚀刻停止处理半导体晶片的方法
    • US5298463A
    • 1994-03-29
    • US870603
    • 1992-04-16
    • Gurtej S. Sandhu , David A. Cathey
    • Gurtej S. Sandhu , David A. Cathey
    • H01L21/28 , H01L21/285 , H01L21/302 , H01L21/3065 , H01L21/311 , H01L21/768 , H01L21/465
    • H01L21/28512 , H01L21/31111 , H01L21/76802 , Y10S438/97
    • A method of processing a semiconductor wafer includes: a) fabricating a wafer to define a plurality of conductive regions, the conductive regions having outer surfaces positioned at varying elevations on the wafer thereby defining at least one high elevation conductive region and at least one low elevation conductive region; b) providing a planarized insulating dielectric layer atop the wafer; c) patterning the insulating dielectric layer for defining a plurality of contact openings through the insulating dielectric to selected conductive regions at the varying elevations; d) first etching the plurality of contact openings into the patterned insulating layer downwardly to stop at the high elevation conductive region outer surface to which electrical contact is to be made; e) after first etching, selectively depositing a layer of an etch stop material to a selected thickness atop the outer surface of the high elevation conductive region; and f) second etching the plurality of contact openings into the patterned insulating material to the low elevation conductive region outer surface to which electrical contact is to be made using the selectively deposited etch stop material layer over the high elevation conductive region as an etch stop protecting layer during such second etching. Photoresist may or may not remain in place during the second etching depending on insulating dielectric layer thicknesses.
    • 一种处理半导体晶片的方法包括：a）制造晶片以限定多个导电区域，所述导电区域具有位于晶片上不同高度的外表面，从而限定至少一个高仰角导电区域和至少一个低仰角 导电区域 b）在晶片顶上提供平坦化的绝缘介电层; c）图案化所述绝缘电介质层，以在所述不同高度处限定通过所述绝缘电介质到选定导电区域的多个接触开口; d）首先将多个接触开口蚀刻到图案化的绝缘层中，以在要形成电接触的高高度导电区域外表面停止; e）在第一蚀刻之后，在所述高高度导电区域的外表面顶部选择性地沉积蚀刻停止材料层至所选择的厚度; 以及f）使用在高仰角导电区域上的选择性沉积的蚀刻停止材料层将多个接触开口第二蚀刻到图案化的绝缘材料中到达低电导率区域外表面，在其上进行电接触作为蚀刻停止保护 在这样的第二蚀刻期间。 根据绝缘电介质层厚度，光刻胶在第二次蚀刻期间可以或不会保持在适当的位置。
    • 基本信息 添加关注 加入工作空间 PDF全文 PDF下载 全文下载 相似专利 双屏查看 权利要求书 说明书全文 Global Dossier Espacenet 法律信息 同族专利 专利引用
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