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91. 发明申请

US20090262582A1 Method of Programming Flash Memory Device 有权
标题翻译：闪存设备编程方法
公开(公告)号：US20090262582A1
公开(公告)日：2009-10-22
申请号：US12489641
申请日：2009-06-23
申请人： Dong Hyuk Chae , Dae-Seok Byeon
发明人： Dong Hyuk Chae , Dae-Seok Byeon
IPC分类号： G11C16/04
CPC分类号： G11C16/10 , G11C16/0483 , G11C16/08
摘要： Flash memory devices include a memory array having a plurality of NAND strings of EEPROM cells therein. A word line driver is provided to improve programming efficiency. The word line driver is electrically coupled to the memory array by a plurality of word lines. The word line driver includes a plurality of pass voltage switches. These switches have outputs electrically coupled by diodes to the plurality of word lines. Methods of programming flash memory devices include applying a pass voltage to a plurality of unselected word lines in a non-volatile memory array while simultaneously applying a sequentially ramped program voltage to a selected word line in the non-volatile memory array. The sequentially ramped program voltage has a minimum value that is clamped by a word line driver to a level not less than a value of the pass voltage.
摘要翻译：闪存器件包括其中具有多个EEPROM串的NAND串的存储器阵列。提供字线驱动程序以提高编程效率。字线驱动器通过多个字线电耦合到存储器阵列。字线驱动器包括多个通过电压开关。这些开关具有由二极管电耦合到多个字线的输出。编程闪速存储器件的方法包括在非易失性存储器阵列中向多个未选择的字线施加通过电压，同时将顺序斜坡的编程电压施加到非易失性存储器阵列中的选定字线。顺序斜坡编程电压具有被字线驱动器钳位到不小于通过电压值的电平的最小值。

92. 发明授权

US07474564B2 Non-volatile memory device capable of changing increment of program voltage according to mode of operation 有权
标题翻译：能够根据操作模式改变编程电压增量的非易失性存储器件
公开(公告)号：US07474564B2
公开(公告)日：2009-01-06
申请号：US11561807
申请日：2006-11-20
申请人： Dong-Hyuk Chae , Dae-Seok Byeon
发明人： Dong-Hyuk Chae , Dae-Seok Byeon
IPC分类号： G11C11/34
CPC分类号： G11C16/30 , G11C16/04 , G11C16/3454 , G11C16/3459 , G11C29/12005 , G11C29/50 , G11C29/50004 , G11C2029/1202
摘要： A non-volatile memory device includes a word line voltage generator circuit for generating a word line voltage to be supplied to a selected row in response to step control signals, and a program controller for generating the step control signals so that an increment of the word line voltage is varied according to the mode of operation, namely, a test mode or normal mode. Thus test time can be shortened.
摘要翻译：非易失性存储器件包括字线电压发生器电路，用于响应于步进控制信号产生要提供给所选行的字线电压;以及程序控制器，用于产生步进控制信号，使得字的增量线路电压根据操作模式，即测试模式或正常模式而变化。因此可以缩短测试时间。

93. 发明申请

US20080168214A1 MEMORY SYSTEM AND METHOD USING SCRAMBLED ADDRESS DATA 审中-公开
标题翻译：使用SCRAMBLED地址数据的存储器系统和方法
公开(公告)号：US20080168214A1
公开(公告)日：2008-07-10
申请号：US11969261
申请日：2008-01-04
申请人： Oh-Suk Kwon , Sung-Soo Lee , Dae-Seok Byeon
发明人： Oh-Suk Kwon , Sung-Soo Lee , Dae-Seok Byeon
IPC分类号： G06F12/02
CPC分类号： G06F12/023 , G06F12/0246 , G06F2212/2022
摘要： A memory system and a method of provided scrambled address data are disclosed. The method includes converting external address data into row and column addresses provided to a flash memory device, and designating certain scrambled address data values within the external address data and ignoring a current data access operation associated with external address data including a scrambled address data value, such that the plurality of physical pages in each memory block is not selected by the internal address data.
摘要翻译：公开了一种提供加扰地址数据的存储系统和方法。该方法包括将外部地址数据转换成提供给闪存设备的行和列地址，以及指定外部地址数据内的某些加扰地址数据值，并忽略与包括加扰地址数据值的外部地址数据相关联的当前数据访问操作，使得每个存储器块中的多个物理页不被内部地址数据选择。

94. 发明申请

US20080137420A1 FLASH MEMORY DEVICES AND METHODS OF PROGRAMMING THE SAME BY OVERLAPPING PROGRAMMING OPERATIONS FOR MULTIPLE MATS 有权
标题翻译：闪存存储器件及其编程方法通过重写多个程序的编程操作
公开(公告)号：US20080137420A1
公开(公告)日：2008-06-12
申请号：US12034968
申请日：2008-02-21
申请人： Jin-Sung Park , Dae-Seok Byeon
发明人： Jin-Sung Park , Dae-Seok Byeon
IPC分类号： G11C16/06
CPC分类号： G11C16/10 , G11C2216/14
摘要： A flash memory device is programmed by loading first data into a page buffer of a first mat. Second data is loaded into a page buffer of a second mat while programming the first data in a first memory block of the first mat.
摘要翻译：通过将第一数据加载到第一垫的页缓冲器中来编程闪存器件。第二数据被加载到第二垫的页缓冲器中，同时在第一垫的第一存储块中编程第一数据。

95. 发明申请

US20080117682A1 Multi-chip package flash memory device and method for reading status data therefrom 有权
标题翻译：多芯片封装闪存器件和从其读取状态数据的方法
公开(公告)号：US20080117682A1
公开(公告)日：2008-05-22
申请号：US11984595
申请日：2007-11-20
申请人： Dae-Seok Byeon
发明人： Dae-Seok Byeon
IPC分类号： G11C16/06
CPC分类号： G06F13/1684
摘要： A method for reading status data from a multi-chip memory device including pluralities of memory chips is comprised of: providing a command to request an output of the status data to the plurality of memory chips; and accepting the status data of the plurality of memory chips through multiple channels of the multi-chip memory device. The reading method of the status data is helpful to shortening a standby time for accepting the status data of the multi-chip memory device, enhancing an operation rate.
摘要翻译：一种用于从包括多个存储器芯片的多芯片存储器件读取状态数据的方法包括：向多个存储器芯片提供请求输出状态数据的命令; 以及通过多芯片存储器件的多个通道接受多个存储器芯片的状态数据。状态数据的读取方法有助于缩短用于接受多芯片存储器件的状态数据的待机时间，从而提高操作速率。

96. 发明申请

US20080089123A1 Method for Programming a Multi-Level Non-Volatile Memory Device 有权
标题翻译：多级非易失性存储器件编程方法
公开(公告)号：US20080089123A1
公开(公告)日：2008-04-17
申请号：US11848014
申请日：2007-08-30
申请人： Dong-Hyuk Chae , Dae-Seok Byeon
发明人： Dong-Hyuk Chae , Dae-Seok Byeon
IPC分类号： G11C16/04
CPC分类号： G11C11/5628 , G11C2211/5646
摘要： A method for programming multi-level non-volatile memory. A plurality of multi-bit storage cells capable of storing different levels of charge usable to represent data represented by a least significant bits (LSBs) and a most significant bits (MSBs) are programmed first with LSBs and then with MSBs. The programmed storage cells have a threshold voltage lower than a voltage VR1 to store a first value, greater than VR1 and lower than a voltage VR2 to store a second value, and greater than VR2 and lower than a voltage VR3 to store a third value. Each of the cells has a threshold voltage greater than a voltage VR3 when it is desired that the storage cell store a fourth value. VR1 is less than VR2 which is less than VR3. The flag cell is programmed to have a threshold voltage greater than VR3 to indicate that the MSBs have been programmed.
摘要翻译：一种用于编程多级非易失性存储器的方法。能够存储可用于表示由最低有效位（LSB）和最高有效位（MSB）表示的数据的不同电荷电平的多个多位存储单元首先用LSB编程，然后用MSB编程。编程存储单元具有低于电压VR 1的阈值电压，以存储大于VR 1且低于电压VR 2的第一值以存储第二值，并且大于VR 2并低于电压VR 3至存储第三个值。当期望存储单元存储第四值时，每个单元具有大于电压VR 3的阈值电压。 VR 1小于VR 2，小于VR 3。标志单元被编程为具有大于VR 3的阈值电压以指示MSB已被编程。

97. 发明申请

US20080084739A1 Method for Programming a Multi-Level Non-Volatile Memory Device 有权
标题翻译：多级非易失性存储器件编程方法
公开(公告)号：US20080084739A1
公开(公告)日：2008-04-10
申请号：US11847980
申请日：2007-08-30
申请人： Dong Hyuk Chae , Dae-Seok Byeon
发明人： Dong Hyuk Chae , Dae-Seok Byeon
IPC分类号： G11C16/00
CPC分类号： G11C16/3404
摘要： A method for programming multi-level non-volatile memory including at least one flag cell and a plurality of multi-bit storage cells. Each storage cell stores data of a least significant bit (LSB) and a most significant bit (MSB). The cells are programmed with LSB data such that programmed storage cells have a threshold voltage greater than VR1. The threshold voltage is modified to have a threshold voltage greater than VR2 for a third or fourth value. The cells are programmed with MSB data for a threshold voltage lower than a VR1 for a first value greater than VR1 and lower than VR2 for a second value, greater than VR2 and lower than VR3 for a third value, and greater than VR3 for a fourth value. VR1 is less than VR2 which is less than VR3. The flag cell is programmed to signal whether MSB data has been programmed.
摘要翻译：一种用于编程包括至少一个标志单元和多个多位存储单元的多级非易失性存储器的方法。每个存储单元存储最低有效位（LSB）和最高有效位（MSB）的数据。单元被编程为LSB数据，使得编程存储单元具有大于VR 1的阈值电压。对于第三或第四值，阈值电压被修改为具有大于VR 2的阈值电压。对于小于VR 1的阈值电压，对于第一值大于VR 1且小于VR 2的第二值，对于第三值，小区用MSB数据编程，大于VR 2且低于VR 3，并且更大比VR 3为第四个值。 VR 1小于VR 2，小于VR 3。标志单元被编程为通知MSB数据是否被编程。

98. 发明授权

US07215181B2 High voltage generator circuit with ripple stabilization function 有权
标题翻译：具有纹波稳定功能的高压发生器电路
公开(公告)号：US07215181B2
公开(公告)日：2007-05-08
申请号：US11025765
申请日：2004-12-28
申请人： Wook-Ghee Hahn , Dae-Seok Byeon
发明人： Wook-Ghee Hahn , Dae-Seok Byeon
IPC分类号： G05F1/10 , H03L7/00
CPC分类号： H02M3/07 , H02M1/14
摘要： The present invention disclosed herein is a high voltage generator circuit. The high voltage generator circuit includes a charge pump and a pump clock signal generator. The pump clock signal is gated to the charge pump when the high voltage is below a target voltage. After the high voltage reaches the target voltage, the high voltage cyclically falls below the target voltage. After the high voltage reaches the target voltage, a pump clock generator block circuit limits the transmission of the pump clock signal so that only N clock signals are gate to the charge pump each cycle, where N is the number one or greater.
摘要翻译：本文公开的本发明是高压发生器电路。高压发生器电路包括电荷泵和泵时钟信号发生器。当高电压低于目标电压时，泵时钟信号被选通到电荷泵。高电压达到目标电压后，高压周期性下降到目标电压以下。在高电压达到目标电压之后，泵时钟发生器电路限制泵时钟信号的传输，从而每个周期只有N个时钟信号被选通到电荷泵，其中N是一个或更多个。

99. 发明申请

US20070076488A1 NON-VOLATILE MEMORY DEVICE CAPABLE OF CHANGING INCREMENT OF PROGRAM VOLTAGE ACCORDING TO MODE OF OPERATION 有权
标题翻译：根据运行模式改变程序升压的非易失性存储器件
公开(公告)号：US20070076488A1
公开(公告)日：2007-04-05
申请号：US11561807
申请日：2006-11-20
申请人： Dong-Hyuk Chae , Dae-Seok Byeon
发明人： Dong-Hyuk Chae , Dae-Seok Byeon
IPC分类号： G11C11/34
CPC分类号： G11C16/30 , G11C16/04 , G11C16/3454 , G11C16/3459 , G11C29/12005 , G11C29/50 , G11C29/50004 , G11C2029/1202
摘要： A non-volatile memory device includes a word line voltage generator circuit for generating a word line voltage to be supplied to a selected row in response to step control signals, and a program controller for generating the step control signals so that an increment of the word line voltage is varied according to the mode of operation, namely, a test mode or normal mode. Thus test time can be shortened.
摘要翻译：非易失性存储器件包括字线电压发生器电路，用于响应于步进控制信号产生要提供给所选行的字线电压;以及程序控制器，用于产生步进控制信号，使得字的增量线路电压根据操作模式，即测试模式或正常模式而变化。因此可以缩短测试时间。

100. 发明申请

US20060087899A1 Wordline voltage generating circuit including a voltage dividing circuit for reducing effects of parasitic capacitance 有权
标题翻译：字线电压产生电路包括用于减小寄生电容的影响的分压电路
公开(公告)号：US20060087899A1
公开(公告)日：2006-04-27
申请号：US11177842
申请日：2005-07-08
申请人： Dong-Hyuk Chae , Dae-Seok Byeon
发明人： Dong-Hyuk Chae , Dae-Seok Byeon
IPC分类号： G11C5/14
CPC分类号： G11C8/08
摘要： Disclosed is a voltage dividing circuit reducing effects of a parasitic capacitance and a wordline voltage generating circuit including that. The voltage dividing circuit according to an aspect of the present invention includes a first resistor, a plurality of second resistors, and a selection means. The first resistor is connected between an output voltage node and a dividing voltage node. The plurality of second resistors are connectable between the dividing voltage node and a ground. The second resistors are sequentially selected in response to a step control signal and connected to ground. In order to reduce the sum of a parasitic capacitance existing in the second resistors, the resistors are arranged in groups, and the selection means connects only that group that contains a selected resistor to the dividing voltage node.
摘要翻译：公开了一种降低寄生电容的影响的分压电路和包括其的字线电压发生电路。根据本发明的一个方面的分压电路包括第一电阻器，多个第二电阻器和选择装置。第一个电阻连接在输出电压节点和分压电压节点之间。多个第二电阻器可以在分压电压节点和地之间连接。第二电阻器响应于步进控制信号被顺序选择并连接到地。为了减少存在于第二电阻器中的寄生电容的总和，电阻器被分组布置，并且选择装置仅将包含选定电阻器的组件连接到分压电压节点。

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