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91. 发明授权

US6069782A ESD damage protection using a clamp circuit 有权
标题翻译：使用钳位电路进行ESD损坏保护
公开(公告)号：US6069782A
公开(公告)日：2000-05-30
申请号：US140619
申请日：1998-08-26
申请人： Chuen-Der Lien , Tak Kwong Wong , Tzong-Kwang Yeh
发明人： Chuen-Der Lien , Tak Kwong Wong , Tzong-Kwang Yeh
IPC分类号： H01L27/02 , H02H9/00
CPC分类号： H01L27/0248
摘要： A circuit for protecting the internal circuitry of a semiconductor chip from increased power supply voltages due to electrostatic discharge events is presented. The circuit comprises a trigger circuit including a resistor and diode array coupled between a power line and a ground line and a discharge circuit which, when turned on by an output signal of the trigger circuit, conducts the excess charge on the power line to ground.
摘要翻译：提出了一种用于保护半导体芯片的内部电路免受由于静电放电事件引起的电源电压的电路。该电路包括触发电路，该触发电路包括耦合在电力线和地线之间的电阻器和二极管阵列，以及放电电路，当触发电路的输出信号导通时，放电电路将电力线上的过量电荷传导到地。

92. 发明授权

US5966035A High voltage tolerable input buffer 失效
标题翻译：高耐压输入缓冲器
公开(公告)号：US5966035A
公开(公告)日：1999-10-12
申请号：US127701
申请日：1998-07-31
申请人： Chuen-Der Lien
发明人： Chuen-Der Lien
IPC分类号： H03K19/003 , H03K5/153
CPC分类号： H03K19/00315
摘要： An input buffer includes an n-channel FET having a drain region coupled to the V.sub.cc voltage supply, a source region coupled to the output terminal and a gate electrode coupled to the input terminal. A bias circuit maintains a voltage at the source of the n-channel FET which is greater than the V.sub.SS supply voltage when a logic low voltage is applied to the input terminal.
摘要翻译：输入缓冲器包括具有耦合到Vcc电压源的漏极区域的n沟道FET，耦合到输出端子的源极区域和耦合到输入端子的栅极电极。当向输入端子施加逻辑低电压时，偏置电路保持在n沟道FET的源极处的电压大于VSS电源电压。

93. 发明授权

US5910922A Method for testing data retention in a static random access memory using isolated V.sub.cc supply 失效
标题翻译：使用隔离Vcc电源在静态随机存取存储器中测试数据保留的方法
公开(公告)号：US5910922A
公开(公告)日：1999-06-08
申请号：US906448
申请日：1997-08-05
申请人： Alan H. Huggins , William L. Devanney , Chuen-Der Lien
发明人： Alan H. Huggins , William L. Devanney , Chuen-Der Lien
IPC分类号： G11C5/14 , G11C29/50 , G11C7/00
CPC分类号： G11C29/028 , G11C29/50 , G11C29/50016 , G11C5/147 , G11C11/41 , G11C2029/5004
摘要： A circuit and a method for providing a power supply voltage to a memory circuit during a memory data retention test are provided. In such a circuit, a first power supply terminal and a second power supply terminal are provided together with a plurality of circuit elements, which are coupled to form a current path between the first and second power supply terminals, such that each circuit element contributes a predetermined voltage drop between the first and second power supply terminals when a current flows in said current path. In addition, a shunt device having a control terminal and coupled across one or more of said circuit elements is provided. The control terminal receives a control signal, such that when the control signal is asserted, the shunt device equalizes a voltage across said one or more of said circuit elements. The memory circuit draws its power supply voltage from the second power supply terminal.
摘要翻译：提供了一种在存储器数据保持测试期间向存储器电路提供电源电压的电路和方法。在这种电路中，第一电源端子和第二电源端子与多个电路元件一起提供，多个电路元件被耦合以在第一和第二电源端子之间形成电流路径，使得每个电路元件贡献一个当电流在所述电流路径中流动时，第一和第二电源端子之间的预定电压降。此外，提供了具有控制端子并且耦合在一个或多个所述电路元件上的分流装置。控制终端接收控制信号，使得当控制信号被断言时，分路装置使跨所述一个或多个所述电路元件的电压相等。存储电路从第二电源端吸取电源电压。

94. 发明授权

US5804477A Method of making a 6-transistor compact static ram cell 失效
标题翻译：制造6晶体管紧凑型静电压电池的方法
公开(公告)号：US5804477A
公开(公告)日：1998-09-08
申请号：US804764
申请日：1997-02-24
申请人： Chuen-Der Lien
发明人： Chuen-Der Lien
IPC分类号： H01L21/8238 , H01L21/8244 , H01L27/11
CPC分类号： H01L27/11 , H01L21/823878 , H01L27/1104
摘要： A 6-T SRAM cell having a MOS transistor with source/drain regions having an absence of heavily doped portions characteristic of prior art lightly doped drain (LDD) MOS devices is fabricated. Forming the MOS transistor with an absence of heavily doped portions of source/drain regions allows the width of the MOS gate layer, the width of the MOS source/drain regions and the width of the field oxide region between active regions of the SRAM cell to be reduced compared to the prior art. Accordingly, the present SRAM cell occupies less chip area than a prior art SRAM cell. Further, forming the MOS transistor without heavily doped portions of source/drain regions improves latch-up immunity and decreases write cycle time of the present SRAM cell.
摘要翻译：制造具有MOS晶体管的6-T SRAM单元，源极/漏极区域不存在现有技术的轻掺杂漏极（LDD）MOS器件的特征的重掺杂部分。在不存在源极/漏极区域的重掺杂部分的情况下形成MOS晶体管允许MOS栅极层的宽度，MOS源极/漏极区域的宽度以及SRAM单元的有源区域之间的场氧化物区域的宽度到与现有技术相比减少。因此，本SRAM单元占用比现有技术的SRAM单元小的芯片面积。此外，形成不具有源极/漏极区域的重掺杂部分的MOS晶体管改善了闩锁抗扰性并且减小了当前SRAM单元的写周期时间。

95. 发明授权

US5793088A Structure for controlling threshold voltage of MOSFET 失效
标题翻译：控制MOSFET阈值电压的结构
公开(公告)号：US5793088A
公开(公告)日：1998-08-11
申请号：US664440
申请日：1996-06-18
申请人： Jeong Yeol Choi , Chung-Jen Chien , Chung Chyung Han , Chuen-Der Lien
发明人： Jeong Yeol Choi , Chung-Jen Chien , Chung Chyung Han , Chuen-Der Lien
IPC分类号： H01L21/266 , H01L21/336 , H01L21/8238 , H01L27/092 , H01L29/10 , H01L29/76 , H01L29/94 , H01L31/062 , H01L31/113
CPC分类号： H01L29/6659 , H01L21/266 , H01L21/8238 , H01L27/0928 , H01L29/1033 , H01L29/1045 , H01L29/1083 , H01L29/6656
摘要： A method and structure for controlling the threshold voltage of a MOSFET is provided. The method compensates for the edge effect associated with prior art halo implants by providing an edge threshold voltage implant (the VT implant) which passes impurities through dielectric spacers, through the underlying source/drain regions and into the edges of the halo regions which lie in the channel. The VT implant reduces junction capacitance and does not degrade punchthrough voltage.
摘要翻译：提供了用于控制MOSFET的阈值电压的方法和结构。该方法通过提供边缘阈值电压注入（VT注入）来补偿与现有技术的光晕植入物相关的边缘效应，该边缘阈值电压注入（VT注入）使杂质通过电介质间隔物穿过下面的源极/漏极区域并进入位于这个频道。 VT注入降低结电容，不会降低穿通电压。

96. 发明授权

US5790452A Memory cell having asymmetrical source/drain pass transistors and method for operating same 失效
标题翻译：具有不对称源极/漏极传输晶体管的存储单元及其操作方法
公开(公告)号：US5790452A
公开(公告)日：1998-08-04
申请号：US649896
申请日：1996-05-02
申请人： Chuen-Der Lien
发明人： Chuen-Der Lien
IPC分类号： G11C11/412 , H01L27/11
CPC分类号： G11C11/412 , H01L27/1112 , Y10S257/903 , Y10S257/904 , Y10S257/906
摘要： A memory cell having an asymmetrical transistor which provides access to a data storage circuit of the memory cell. The asymmetrical transistor exhibits a forward threshold voltage when forward biased and a reverse threshold voltage when reverse biased. The forward threshold voltage is less than the reverse threshold voltage. The asymmetrical transistor is connected such that during write-disturb mode, the asymmetrical transistor is reverse biased to provide a relatively high reverse threshold voltage. This high reverse threshold voltage minimizes subthreshold current leakage during write-disturb mode, thereby reducing the possibility of data corruption. During read mode, the asymmetrical transistor is forward biased to provide a relatively low forward threshold voltage. This low forward threshold voltage maximizes the read voltage applied to the data storage circuit through the asymmetrical transistor, thereby improving the stability of the memory cell.
摘要翻译：具有非对称晶体管的存储单元，其提供对存储单元的数据存储电路的访问。当正向偏置时，非对称晶体管呈现正向阈值电压，而在反向偏置时呈现反向阈值电压。正向阈值电压小于反向阈值电压。连接非对称晶体管使得在写入 - 干扰模式期间，非对称晶体管被反向偏置以提供相对较高的反向阈值电压。该高反向阈值电压在写入 - 干扰模式期间最小化亚阈值电流泄漏，从而减少数据损坏的可能性。在读取模式期间，非对称晶体管被正向偏置以提供相对低的正向阈值电压。该低正向阈值电压使通过不对称晶体管施加到数据存储电路的读取电压最大化，从而提高存储单元的稳定性。

97. 发明授权

US5745404A ISRAM layout and structure 失效
标题翻译： ISRAM布局和结构
公开(公告)号：US5745404A
公开(公告)日：1998-04-28
申请号：US567443
申请日：1995-12-05
申请人： Chuen-Der Lien , Kyle W. Terrill
发明人： Chuen-Der Lien , Kyle W. Terrill
IPC分类号： H01L27/11 , G11C11/00
CPC分类号： H01L27/1112 , Y10S257/903 , Y10S257/904
摘要： A triple-poly process forms a static random access memory (SRAM) which has a compact four-transistor SRAM cell layout. The cell layout divides structures among the three layers of polysilicon to reduce the area required for each cell. Additionally, a contact between a pull-up resistor formed in an upper polysilicon layer forms a "strapping" via which cross-couples a gate region and a drain region underlying the strapping via. Pull-up resistors extend across boundaries of cell areas to increase the length and resistance of the pull-up resistors.
摘要翻译：三重多工艺形成具有紧凑的四晶体管SRAM单元布局的静态随机存取存储器（SRAM）。单元格布局在三层多晶硅之间划分结构，以减少每个单元所需的面积。此外，形成在上多晶硅层中的上拉电阻器之间的接触形成“捆扎”，通过该接头将栅极区域和穿通通孔下方的漏极区域交叉。上拉电阻延伸到单元区域的边界，以增加上拉电阻的长度和电阻。

98. 发明授权

US5693975A Compact P-channel/N-channel transistor structure 失效
标题翻译：紧凑的P沟道/ N沟道晶体管结构
公开(公告)号：US5693975A
公开(公告)日：1997-12-02
申请号：US539805
申请日：1995-10-05
申请人： Chuen-Der Lien
发明人： Chuen-Der Lien
IPC分类号： H01L21/8238 , H01L27/092 , H01L29/06 , H01L27/11 , H01L29/04 , H01L29/76
CPC分类号： H01L27/0928 , H01L21/823814 , H01L21/823878 , Y10S257/903
摘要： A structure for a complementary field effect transistor includes a semiconductor body having a first body region of a first conductivity type and an adjoining second body region of an opposite second conductivity type. A buried dielectric region is located in the semiconductor body beneath the upper semiconductor surface and extends into the first and second body regions. A first drain region of the second conductivity type is located in the semiconductor body and adjoins the first body region, the dielectric region and the upper semiconductor surface. A second drain region of the first conductivity type is located in the semiconductor body and adjoins the second body region, the dielectric region and the upper semiconductor surface. The two drain regions are adjacent to one another. The buried dielectric region underlies the two drain regions and contacts portions of both drain regions so as to (a) isolate the first drain region from the second body region and (b) isolate the second drain region from the first body region. The transistor structure can be fabricated according to processes in which formation of the body regions is initiated before or after the dielectric region is formed.
摘要翻译：互补场效应晶体管的结构包括具有第一导电类型的第一体区和相对的第二导电类型的邻接的第二体区的半导体本体。掩埋介电区位于半导体本体的下半导体表面下方并延伸到第一和第二体区内。第二导电类型的第一漏极区位于半导体本体中并与第一体区，电介质区和上半导体表面相邻。第一导电类型的第二漏区位于半导体本体中，并与第二体区，电介质区和上半导体表面相邻。两个漏极区彼此相邻。掩埋介质区域位于两个漏极区域的下方并且接触两个漏极区域的部分，从而（a）使第一漏极区域与第二体区域隔离，并且（b）将第二漏极区域与第一体区域隔离。可以根据在形成电介质区域之前或之后开始体区的形成的工艺来制造晶体管结构。

99. 发明授权

US5643809A Method for making high speed poly-emitter bipolar transistor 失效
标题翻译：制造高速多晶硅双极晶体管的方法
公开(公告)号：US5643809A
公开(公告)日：1997-07-01
申请号：US572449
申请日：1995-12-14
申请人： Chuen-Der Lien
发明人： Chuen-Der Lien
IPC分类号： H01L21/331 , H01L29/10 , H01L29/417 , H01L29/732 , H01L21/265
CPC分类号： H01L29/66272 , H01L29/1004 , H01L29/41708 , H01L29/732 , Y10S148/009 , Y10S148/01
摘要： Spacers are formed on the inside walls of a narrow silicon loss trench of a poly-emitter type bipolar transistor structure so that at most a narrow strip on the bottom of the trench receives high concentration doping when an extrinsic base region of the bipolar transistor is being doped. The narrowness of the exposed silicon surface which is etched to form the silicon loss trench slows vertical etching and thereby facilitates the formation of a shallow trench. The narrowness of the strip on the bottom of the trench which receives high concentration doping causes slow vertical diffusion of dopants. As a result, the highly doped link region which extends downward from the bottom of the trench does not extend downward much farther than the base region. A high cutoff frequency is therefore achievable by reducing the distance between the bottom of the base region and the top of the buried layer without decreasing the base-to-collector breakdown voltage.
摘要翻译：间隔物形成在多发射体型双极晶体管结构的窄硅损失沟槽的内壁上，使得当双极晶体管的非本征基极区为正时，沟槽底部的至少一个窄条接收高浓度掺杂掺杂。被蚀刻以形成硅损耗沟槽的暴露的硅表面的狭窄减慢了垂直蚀刻，从而有利于形成浅沟槽。接收高浓度掺杂的沟槽底部的条纹狭窄导致掺杂剂的慢垂直扩散。结果，从沟槽底部向下延伸的高度掺杂的链路区域不会比基极区域向下延伸得更远。因此，通过减小基极区域的底部和埋层的顶部之间的距离而不降低基极到集电极击穿电压，可以实现高截止频率。

100. 发明授权

US5574305A Walled-emitter transistor 失效
标题翻译：壁发射极晶体管
公开(公告)号：US5574305A
公开(公告)日：1996-11-12
申请号：US272277
申请日：1994-07-08
申请人： Chuen-Der Lien , Kyle W. Terrill
发明人： Chuen-Der Lien , Kyle W. Terrill
IPC分类号： H01L21/331 , H01L21/762 , H01L29/70
CPC分类号： H01L29/66272 , H01L21/76216 , Y10S148/01 , Y10S148/011 , Y10S148/102 , Y10S148/124
摘要： An embodiment of the present invention is a process for semiconductor device having a silicon substrate. The process comprises positioning at least one field implant mask and field implanting a silicon substrate around a bipolar active region in a substrate such that boron atoms are blocked out of an active region, and only the field region surrounding said active area is implanted, said implanting such that a predetermined layout area of a semiconductor device does not need to be increased to compensate for a BV.sub.bso problem.
摘要翻译：本发明的实施例是具有硅衬底的半导体器件的工艺。该方法包括定位至少一个场注入掩模，并且在衬底中的双极有源区周围注入硅衬底，使得硼原子被阻挡在有源区之外，并且仅植入围绕所述有源区的场区，所述注入使得半导体器件的预定布局区域不需要增加以补偿BVbso问题。

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