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91. 发明授权

US07259050B2 Semiconductor device and method of making the same 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：US07259050B2
公开(公告)日：2007-08-21
申请号：US10834474
申请日：2004-04-29
申请人： Chien-Hao Chen , Chia-Lin Chen , Tze Liang Lee , Shih-Chang Chen , Ju-Wang Hsu
发明人： Chien-Hao Chen , Chia-Lin Chen , Tze Liang Lee , Shih-Chang Chen , Ju-Wang Hsu
IPC分类号： H01L21/338
CPC分类号： H01L29/6653 , H01L29/6656 , H01L29/6659 , H01L29/7833 , H01L29/7842 , H01L29/7843
摘要： A semiconductor device comprises a substrate, a gate disposed on the substrate, and a source and drain formed in the substrate on both sides of the gate. The device further comprises a thin spacer having a first layer and a second layer formed on the sidewalls of the gate, wherein the first and second layers have comparable wet etch rates of at least 10 Å per minute using the same etchant.
摘要翻译：半导体器件包括衬底，设置在衬底上的栅极和形成在栅极两侧的衬底中的源极和漏极。该器件还包括具有形成在栅极的侧壁上的第一层和第二层的薄间隔物，其中使用相同的蚀刻剂，第一层和第二层具有至少每分钟至少10埃的湿蚀刻速率。

92. 发明授权

US07176138B2 Selective nitride liner formation for shallow trench isolation 有权
标题翻译：用于浅沟槽隔离的选择性氮化物衬垫形成
公开(公告)号：US07176138B2
公开(公告)日：2007-02-13
申请号：US10970090
申请日：2004-10-21
申请人： Chien-Hao Chen , Vincent S. Chang , Ji-Yi Yang , Chia-Lin Chen , Tze-Liang Lee
发明人： Chien-Hao Chen , Vincent S. Chang , Ji-Yi Yang , Chia-Lin Chen , Tze-Liang Lee
IPC分类号： H01L21/311
CPC分类号： H01L21/76232
摘要： A method for forming a divot free nitride lined shallow trench isolation (STI) feature including providing a substrate including an STI trench extending through an uppermost hardmask layer into a thickness of the substrate exposing the substrate portions; selectively forming a first insulating layer lining the STI trench over said exposed substrate portions only; backfilling the STI trench with a second insulating layer; planarizing the second insulating layer; and, carrying out a wet etching process to remove the uppermost hardmask layer.
摘要翻译：一种用于形成无自由度的氮化物衬底浅沟槽隔离（STI）特征的方法，包括提供包括延伸穿过最上面的硬掩模层的STI沟槽的衬底，暴露衬底部分的衬底的厚度; 仅在所述暴露的衬底部分上选择性地形成衬在STI沟槽上的第一绝缘层; 用第二绝缘层回填STI沟槽; 平面化第二绝缘层; 并进行湿蚀刻处理以去除最上面的硬掩模层。

93. 发明申请

US20070032037A1 Method of forming SOI-like structure in a bulk semiconductor substrate using self-organized atomic migration 有权
标题翻译：使用自组织原子迁移在体半导体衬底中形成SOI样结构的方法
公开(公告)号：US20070032037A1
公开(公告)日：2007-02-08
申请号：US11546768
申请日：2006-10-12
申请人： Ji-Yi Yang , Chien-Hao Chen , Tze-Liang Lee , Shih-Chang Chen , Huan-Just Lin
发明人： Ji-Yi Yang , Chien-Hao Chen , Tze-Liang Lee , Shih-Chang Chen , Huan-Just Lin
IPC分类号： H01L21/76
CPC分类号： H01L21/3247 , H01L21/76232 , H01L21/76283 , H01L27/1203
摘要： Bulk silicon is transformed into an SOI-like structure by annealing. Trenches are formed in a bulk substrate to define device sites. The lower portions of the trenches are annealed at low pressure in a hydrogen atmosphere. This transforms the lower trench portions to expanded, spheroidal voids that extend under the device sites. Neighboring voids each reside about half way under an intervening site. A silicon-consuming process forms a liner on the walls of the voids, with the liners on neighboring voids abutting to isolate the intervening device site from the substrate and other device sites.
摘要翻译：通过退火将体硅转变成SOI样结构。沟槽形成在大量衬底中以限定器件位置。沟槽的下部在氢气气氛中在低压下退火。这将下沟槽部分转变成在器件位置下延伸的膨胀的球状空隙。相邻的空洞每个居住在中间位置的一半左右。消耗硅的过程在空隙的壁上形成衬垫，相邻空隙上的衬垫邻接以将介入的器件位置与衬底和其它器件位置隔离。

94. 发明申请

US20070010073A1 Method of forming a MOS device having a strained channel region 审中-公开
标题翻译：形成具有应变通道区域的MOS器件的方法
公开(公告)号：US20070010073A1
公开(公告)日：2007-01-11
申请号：US11175563
申请日：2005-07-06
申请人： Chien-Hao Chen , Chun-Feng Nieh , Tze-Liang Lee , Shih-Chang Chen , Mong Liang
发明人： Chien-Hao Chen , Chun-Feng Nieh , Tze-Liang Lee , Shih-Chang Chen , Mong Liang
IPC分类号： H01L21/20 , H01L21/4763
CPC分类号： H01L21/26506 , H01L21/324 , H01L21/76828 , H01L21/76829 , H01L21/823412 , H01L21/82345 , H01L21/823807 , H01L21/823842 , H01L29/6659 , H01L29/7833 , H01L29/7843
摘要： A method of forming a semiconductor device comprising providing a substrate comprising a first device region, implanting a source/drain region in the first device region, forming a strained capping layer on the source/drain region, super annealing and crystallizing the source/drain region, and removing substantially all of the strained capping layer is provided. The method further includes pre-amorphizing the source/drain region before the super annealing. The strained capping layer may further be formed on a pre-amorphized gate electrode, and the gate electrode is super annealed. The strain is generated and preserved after the removal of the strained capping layer.
摘要翻译：一种形成半导体器件的方法，包括提供包括第一器件区域的衬底，在第一器件区域中注入源极/漏极区域，在源极/漏极区域上形成应变封盖层，超退火并使源极/漏极区域结晶并且提供基本上所有的应变封盖层的去除。该方法还包括在超退火之前对源极/漏极区进行非晶化。应变封盖层可以进一步形成在非晶化的栅电极上，并且栅电极被超退火。在去除应变封盖层后产生并保存菌株。

95. 发明申请

US20060246672A1 Method of forming a locally strained transistor 有权
标题翻译：形成局部应变晶体管的方法
公开(公告)号：US20060246672A1
公开(公告)日：2006-11-02
申请号：US11119522
申请日：2005-04-29
申请人： Chien-Hao Chen , Donald Chao , Tze-Liang Lee
发明人： Chien-Hao Chen , Donald Chao , Tze-Liang Lee
IPC分类号： H01L21/336 , H01L29/94 , H01L27/108 , H01L29/76 , H01L31/119
CPC分类号： H01L29/78 , H01L29/7843
摘要： A preferred embodiment of the invention provides a semiconductor fabrication method. An embodiment comprises forming a MOS device having sidewall spacers. A highly stressed layer is deposited over the device. The stress is selectively adjusted in that portion of the layer over the gate electrode and the sidewall spacers. Preferably, the stress layer over the gate electrode and over the sidewall spacers is adjusted from a first stress to a second stress, wherein the first stress is one of tensile and compressive, and the second stress is the other of tensile and compressive. Preferred embodiments selectively induce a suitable stress within PMOS and NMOS channel regions for improving their respective carrier mobility. Still other embodiments of the invention comprise a field effect transistor (FET) having a overlying stressed layer, the stressed layer being comprised of different stress regions.
摘要翻译：本发明的优选实施例提供半导体制造方法。一个实施例包括形成具有侧壁间隔物的MOS器件。高应力层沉积在器件上。在栅极电极和侧壁间隔物上的层的该部分中选择性地调节应力。优选地，栅极上方和侧壁间隔物上的应力层从第一应力调整到第二应力，其中第一应力是拉伸和压缩之一，第二应力是拉伸和压缩中的另一个。优选实施例在PMOS和NMOS沟道区域内选择性地诱发适当的应力，以改善它们各自的载流子迁移率。本发明的其它实施例包括具有上覆应力层的场效应晶体管（FET），所述应力层由不同的应力区域组成。

96. 发明申请

US20060099771A1 Selective nitride liner formation for shallow trench isolation 有权
标题翻译：用于浅沟槽隔离的选择性氮化物衬垫形成
公开(公告)号：US20060099771A1
公开(公告)日：2006-05-11
申请号：US10970090
申请日：2004-10-21
申请人： Chien-Hao Chen , Vincent Chang , Ji-Yi Yang , Chia-Lin Chen , Tze-Liang Lee
发明人： Chien-Hao Chen , Vincent Chang , Ji-Yi Yang , Chia-Lin Chen , Tze-Liang Lee
IPC分类号： H01L21/76
CPC分类号： H01L21/76232
摘要： A method for forming a divot free nitride lined shallow trench isolation (STI) feature including providing a substrate including an STI trench extending through an uppermost hardmask layer into a thickness of the substrate exposing the substrate portions; selectively forming a first insulating layer lining the STI trench over said exposed substrate portions only; backfilling the STI trench with a second insulating layer; planarizing the second insulating layer; and, carrying out a wet etching process to remove the uppermost hardmask layer.
摘要翻译：一种用于形成无自由度的氮化物衬底浅沟槽隔离（STI）特征的方法，包括提供包括延伸穿过最上面的硬掩模层的STI沟槽的衬底，暴露衬底部分的衬底的厚度; 仅在所述暴露的衬底部分上选择性地形成衬在STI沟槽上的第一绝缘层; 用第二绝缘层回填STI槽; 平面化第二绝缘层; 并进行湿蚀刻处理以去除最上面的硬掩模层。

97. 发明申请

US20060099745A1 Method for forming integrated advanced semiconductor device using sacrificial stress layer 有权
标题翻译：使用牺牲应力层形成集成先进半导体器件的方法
公开(公告)号：US20060099745A1
公开(公告)日：2006-05-11
申请号：US10981925
申请日：2004-11-05
申请人： Ju-Wang Hsu , Ming-Huan Tsai , Chien-Hao Chen , Yi-Chun Huang
发明人： Ju-Wang Hsu , Ming-Huan Tsai , Chien-Hao Chen , Yi-Chun Huang
IPC分类号： H01L21/84 , H01L21/00
CPC分类号： H01L29/7842 , H01L21/823807 , H01L21/823835 , H01L21/823864 , H01L21/823878 , H01L29/7843 , Y10S438/938
摘要： An integrated advanced method for forming a semiconductor device utilizes a sacrificial stress layer as part of a film stack that enables spatially selective silicide formation in the device. The low-resistance portion of the device to be silicided includes NMOS transistors and PMOS transistors. The stressed film may be a tensile or compressive nitride film. An annealing process is carried out prior to the silicide formation process. During the annealing process, the stressed nitride film preferentially remains over either the NMOS transistors or PMOS transistors, but not both, to optimize device performance. A tensile nitride film remains over the NMOS transistors but not the PMOS transistors while a compressive nitride film remains over the PMOS transistors but not the NMOS transistors, during anneal.
摘要翻译：用于形成半导体器件的集成先进方法利用牺牲应力层作为薄膜堆叠的一部分，其能够在器件中形成空间选择性硅化物。要被硅化的器件的低电阻部分包括NMOS晶体管和PMOS晶体管。应力膜可以是拉伸或压缩氮化物膜。在硅化物形成工艺之前进行退火处理。在退火过程中，应力氮化物膜优先保留在NMOS晶体管或PMOS晶体管之上，但不能同时保持在两者上，以优化器件性能。在退火期间，拉伸氮化物膜保留在NMOS晶体管上，而不是PMOS晶体管，而压电氮化物膜保留在PMOS晶体管上，而不保留在NMOS晶体管上。

98. 发明申请

US20060094194A1 Advanced disposable spacer process by low-temperature high-stress nitride film for sub-90NM CMOS technology 审中-公开
标题翻译：用于低于90NM CMOS技术的低温高应力氮化膜的高级一次性间隔工艺
公开(公告)号：US20060094194A1
公开(公告)日：2006-05-04
申请号：US10982115
申请日：2004-11-04
申请人： Chien-Hao Chen , Chia-Lin Chen , Tze-Liang Lee , Shih-Chang Chen
发明人： Chien-Hao Chen , Chia-Lin Chen , Tze-Liang Lee , Shih-Chang Chen
IPC分类号： H01L21/336
CPC分类号： H01L21/26513 , H01L21/26506 , H01L21/2658 , H01L29/6653 , H01L29/6659 , H01L29/7833 , H01L29/7843
摘要： A method of forming a semiconductor device comprises providing a gate electrode having exposed side walls formed in a substrate, forming dummy spacers on the gate electrode exposed side walls, performing a first implant to form source and drain implants, forming a capping layer over the gate electrode, the dummy sidewall spacers, and the source and drain, performing a first anneal, and removing the capping layer and the dummy sidewall spacers.
摘要翻译：一种形成半导体器件的方法包括提供栅电极，其具有形成在衬底中的暴露的侧壁，在栅极电极暴露的侧壁上形成虚设间隔物，执行第一注入以形成源极和漏极注入，在栅极上形成覆盖层电极，虚拟侧壁间隔物以及源极和漏极，执行第一退火，以及去除覆盖层和虚设侧壁间隔物。

99. 发明申请

US20050196927A1 Process for integration of a high dielectric constant gate insulator layer in a CMOS device 有权
公开(公告)号：US20050196927A1
公开(公告)日：2005-09-08
申请号：US11119951
申请日：2005-05-02
申请人： Ming-Fang Wang , Chien-Hao Chen , Liang-Gi Yao , Shih-Chang Chen
发明人： Ming-Fang Wang , Chien-Hao Chen , Liang-Gi Yao , Shih-Chang Chen
IPC分类号： H01L21/8238 , H01L21/336
CPC分类号： H01L21/823857 , H01L21/823807 , H01L21/823814 , H01L29/665 , Y10S257/90
摘要： A CMOS device structure, and a method of fabricating the CMOS device, featuring a gate insulator layer comprised of a high k metal oxide layer, has been developed. The process features formation of recessed, heavily doped source/drain regions, and of vertical, polysilicon LDD spacers, prior to deposition of the high k metal oxide layer. Removal of a silicon nitride shape, previously used as a mask for definition of the recessed regions, which in turn are used for accommodation of the heavily doped source/drain regions, provides the space to be occupied by the high k metal oxide layer. The integrity of the high k, gate insulator layer, butted by the vertical polysilicon spacers, and overlying a channel region provided by the non-recessed portion of the semiconductor substrate, is preserved via delayed deposition of the metal oxide layer, performed after high temperature anneals such as the activation anneal for heavily doped source/drain regions, as well as the anneal used for metal silicide formation.

100. 发明申请

US20050136583A1 Advanced strained-channel technique to improve CMOS performance 审中-公开
标题翻译：先进的应变通道技术，以提高CMOS性能
公开(公告)号：US20050136583A1
公开(公告)日：2005-06-23
申请号：US10744746
申请日：2003-12-23
申请人： Chien-Hao Chen , Chia-Lin Chen , Tze-Liang Lee , Shih-Chang Chen
发明人： Chien-Hao Chen , Chia-Lin Chen , Tze-Liang Lee , Shih-Chang Chen
IPC分类号： H01L21/8238 , H01L21/3205 , H01L21/4763
CPC分类号： H01L29/7842 , H01L21/823807 , H01L21/823842
摘要： A method of improving CMOS device performance, comprising the following steps. A structure having a gate electrode formed thereover and a channel formed thereunder is provided. The gate electrode having an initial lower width and an initial upper width. A capping layer having a tensile stress is formed over the structure and the gate electrode. The gate electrode is annealed to achieve tensile stress in the channel.
摘要翻译：一种提高CMOS器件性能的方法，包括以下步骤。提供了具有形成在其上的栅电极和在其下形成的沟道的结构。栅电极具有初始下宽度和初始上宽度。在结构和栅电极上形成具有拉伸应力的覆盖层。栅电极退火以在通道中实现拉伸应力。

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