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    • 95. 发明授权
    • Semiconductor memory device and method for manufacturing the same
    • 半导体存储器件及其制造方法
    • US06791147B1
    • 2004-09-14
    • US09431762
    • 1999-11-01
    • Junichi KarasawaKunio WatanabeTakeshi Kumagai
    • Junichi KarasawaKunio WatanabeTakeshi Kumagai
    • H01L2976
    • H01L27/11H01L21/823892H01L27/0928
    • A semiconductor memory device has a peripheral circuit area and a memory cell area on a main surface thereof. The semiconductor memory device includes a first well formed in the peripheral circuit area, a second well of a first conductivity type formed in the memory cell area, a third well of a second conductivity type formed in the memory cell area, and a device isolation structure formed in the memory cell area for isolating an element formed in the second well from an element formed in the third well. The second well of the first conductivity type has a depth shallower than a depth of the first well. The third well of the second conductivity type is equal in depth to the second well. The second and third wells are formed down to a level lower than the device isolation structure.
    • 半导体存储器件在其主表面上具有外围电路区域和存储单元区域。 半导体存储器件包括形成在外围电路区域中的第一阱,形成在存储单元区域中的第一导电类型的第二阱,形成在存储单元区域中的第二导电类型的第三阱,以及器件隔离结构 形成在用于将形成在第二阱中的元件与形成在第三阱中的元件隔离的存储单元区域中。 第一导电类型的第二阱具有比第一阱的深度浅的深度。 第二导电类型的第三阱与第二阱的深度相等。 第二和第三阱形成为低于器件隔离结构的水平。
    • 96. 发明授权
    • Semiconductor memory device and method of fabricating the same
    • 半导体存储器件及其制造方法
    • US06534864B1
    • 2003-03-18
    • US09428821
    • 1999-10-28
    • Kazuo TanakaTakashi KumagaiJunichi KarasawaKunio Watanabe
    • Kazuo TanakaTakashi KumagaiJunichi KarasawaKunio Watanabe
    • H01L2348
    • H01L27/11H01L27/1104Y10S257/903
    • A semiconductor memory device (SRAM) comprises memory cells, each of which includes two load transistors, two driver transistors and two transfer transistors. The SRAM cell includes a semiconductor substrate in which the transistors are formed, a first interlayer dielectric formed on the semiconductor substrate, first contact portions formed in the first interlayer dielectric and first wiring layers (node wiring layers and pad layers) formed on the first interlayer dielectric. The first contact portions and the first wiring layers include metal layers made of refractory metal and a refractory metal nitride layers. This semiconductor memory device of the present invention is capable of enhancing an integration degree of wiring layers and achieving a microfabrication.
    • 半导体存储器件(SRAM)包括存储单元,每个存储单元包括两个负载晶体管,两个驱动晶体管和两个转移晶体管。 SRAM单元包括其中形成晶体管的半导体衬底,形成在半导体衬底上的第一层间电介质,形成在第一层间电介质中的第一接触部分和形成在第一层间电介质上的第一布线层(节点布线层和衬垫层) 电介质。 第一接触部分和第一布线层包括由难熔金属制成的金属层和难熔金属氮化物层。 本发明的半导体存储器件能够提高布线层的集成度并实现微细加工。
    • 97. 发明授权
    • Semiconductor device and method of fabricating the same
    • 半导体装置及其制造方法
    • US06459139B2
    • 2002-10-01
    • US09727705
    • 2000-12-04
    • Kunio WatanabeKazuhiko Okawa
    • Kunio WatanabeKazuhiko Okawa
    • H01L2900
    • H01L27/0251
    • The semiconductor device has an insulated-gate field-effect transistor (MOS transistor), a bipolar transistor, and a Zener diode. The MOS transistor is formed in a well of a first conductive type (p-type) and has a gate insulation layer, a gate electrode, side wall insulation layers, and second conductive type (n-type) of source and drain regions. The bipolar transistor has the drain region as a collector region, the well as a base region, and an n-type impurity-diffusion layer isolated from the drain region as an emitter region. The Zener diode is formed by the junction of an n-type impurity-diffusion layer continuous with the drain region and a p-type impurity-diffusion layer. The source and drain regions have a silicide layer formed on the surface thereof. A protection layer is formed on the surface of the n-type impurity-diffusion layer of the Zener diode.
    • 半导体器件具有绝缘栅场效应晶体管(MOS晶体管),双极晶体管和齐纳二极管。 MOS晶体管形成在第一导电类型(p型)的阱中,并且具有栅极绝缘层,栅电极,侧壁绝缘层和第二导电类型(n型)源极和漏极区。 双极晶体管具有漏极区域作为集电极区域,阱作为基极区域,以及与漏极区域隔离的n型杂质扩散层作为发射极区域。 齐纳二极管由与漏极区连续的n型杂质扩散层和p型杂质扩散层的结形成。 源区和漏区在其表面上形成硅化物层。 在齐纳二极管的n型杂质扩散层的表面上形成保护层。
    • 98. 发明授权
    • Semiconductor memory device and method of fabricating the same
    • 半导体存储器件及其制造方法
    • US06232670B1
    • 2001-05-15
    • US09361043
    • 1999-07-26
    • Takashi KumagaiJunichi KarasawaKazuo TanakaKunio Watanabe
    • Takashi KumagaiJunichi KarasawaKazuo TanakaKunio Watanabe
    • H01L2711
    • H01L27/1104
    • First and second memory cells of an SRAM comprises first, second, and third conductive layers. The first conductive layer is a gate electrode for a first load transistor and a first driver transistor. The second conductive layer diverges from the first conductive layer on a field oxide region and is electrically connected to a second driver transistor active region. The third conductive layer is a gate electrode for a second load transistor and a second driver transistor. The third conductive layer is electrically connected to a first load transistor active region. The pattern of the first, second, and third conductive layers of the second memory cell is a rotated pattern of the first, second, and third conductive layers in the first memory cell at an angle of 180 degrees around an axis perpendicular to the main surface of a semiconductor substrate.
    • SRAM的第一和第二存储单元包括第一,第二和第三导电层。 第一导电层是用于第一负载晶体管和第一驱动晶体管的栅电极。 第二导电层从场氧化物区域上的第一导电层发散,并且电连接到第二驱动器晶体管有源区。 第三导电层是用于第二负载晶体管的栅电极和第二驱动晶体管。 第三导电层电连接到第一负载晶体管有源区。 第二存储单元的第一,第二和第三导电层的图案是第一存储单元中的第一,第二和第三导电层的旋转图案,围绕垂直于主表面的轴以180度的角度 的半导体衬底。