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91. 发明授权

US06432812B1 Method of coupling capacitance reduction 有权
标题翻译：耦合电容降低的方法
公开(公告)号：US06432812B1
公开(公告)日：2002-08-13
申请号：US09906331
申请日：2001-07-16
申请人： Charles E. May
发明人： Charles E. May
IPC分类号： H01L214763
CPC分类号： H01L23/5222 , H01L21/32136 , H01L21/7682 , H01L2924/0002 , H01L2924/00
摘要： A method for reducing the coupling capacitance between adjacent electrically conductive interconnect lines of an integrated circuit. An electrically conductive layer is deposited and etched to produce electrically conductive interconnect lines having negatively sloped sidewalls. An insulating layer is deposited on the electrically conductive interconnect lines using a directional deposition to create a void between and directly adjacent electrically conductive interconnect lines. The void has a substantially lower dielectric constant than the material of the insulating layer, which reduces the coupling capacitance between adjacent electrically conductive interconnect lines.
摘要翻译：一种用于减小集成电路的相邻导电互连线之间的耦合电容的方法。沉积和蚀刻导电层以产生具有负斜边的导电互连线。使用定向沉积在导电互连线上沉积绝缘层，以在直接相邻的导电互连线之间产生空隙。该空隙具有比绝缘层的材料基本上更低的介电常数，这降低了相邻导电互连线之间的耦合电容。

92. 发明授权

US06410967B1 Transistor having enhanced metal silicide and a self-aligned gate electrode 有权
标题翻译：晶体管具有增强的金属硅化物和自对准栅电极
公开(公告)号：US06410967B1
公开(公告)日：2002-06-25
申请号：US09173273
申请日：1998-10-15
申请人： Frederick N. Hause , Mark I. Gardner , Charles E. May
发明人： Frederick N. Hause , Mark I. Gardner , Charles E. May
IPC分类号： H01L2972
CPC分类号： H01L29/66583 , H01L21/26586 , H01L29/41775 , H01L29/6653 , H01L29/66545 , H01L29/6659 , H01L29/66606
摘要： A transistor and a method for making a transistor are described. A metal layer is formed upon a semiconductor substrate, and a masking layer is formed upon the metal layer. The masking layer is patterned to form an opening therein, and portions of the metal layer not covered by the masking layer are removed. A gate dielectric layer is formed within the opening upon the semiconductor substrate; in an embodiment, spacers are also formed upon opposed sidewall surfaces of the masking layer. A conductive material is then deposited upon the dielectric material to form a gate conductor. The masking material is then removed, source and drain and lightly doped drain impurity areas are formed in the semiconductor substrate, and the metal layer is annealed to form a silicide in close proximity to the channel region. By depositing the metal layer prior to forming the gate conductor, the process described herein allows formation of a metal silicide adjacent or in close proximity to the channel region of the transistor. The process also allows formation of a metal gate conductor self-aligned with lightly doped drain or source-drain impurity areas.
摘要翻译：描述晶体管和制造晶体管的方法。在半导体衬底上形成金属层，在金属层上形成掩模层。图案化掩模层以在其中形成开口，并且去除未被掩模层覆盖的金属层的部分。在半导体衬底的开口内形成栅介质层; 在一个实施例中，间隔物也形成在掩蔽层的相对的侧壁表面上。然后将导电材料沉积在电介质材料上以形成栅极导体。然后去除掩模材料，在半导体衬底中形成源极和漏极以及轻掺杂的漏极杂质区域，并且将金属层退火以形成靠近沟道区的硅化物。通过在形成栅极导体之前沉积金属层，本文所述的工艺允许形成与晶体管的沟道区相邻或紧邻的金属硅化物。该工艺还允许形成与轻掺杂漏极或源极 - 漏极杂质区域自对准的金属栅极导体。

93. 发明授权

US06294397B1 Drop-in test structure and abbreviated integrated circuit process flow for characterizing production integrated circuit process flow, topography, and equipment 失效
标题翻译：插入式测试结构和简化的集成电路工艺流程，用于表征生产集成电路工艺流程，地形和设备
公开(公告)号：US06294397B1
公开(公告)日：2001-09-25
申请号：US09262574
申请日：1999-03-04
申请人： Richard W. Jarvis , Iraj Emami , Charles E. May
发明人： Richard W. Jarvis , Iraj Emami , Charles E. May
IPC分类号： H01L2166
CPC分类号： H01L22/20 , H01L22/34
摘要： A drop-in test structure fabricated upon a virtual integrated circuit elevational profile and a method for using the drop-in test structure for characterizing an integrated circuit production methodology and integrated circuit fabrication equipment are described. According to an embodiment, the test structure may be fabricated upon an elevational profile corresponding elevationally to a complete or substantially complete production integrated circuit topography. According to an alternative embodiment, the test structure may be fabricated upon an elevational profile corresponding elevationally to a partially complete production topography. The test structure and method may be used to characterize the underlying elevational profile and to identify both systematic and random defects either as part of routine monitoring or in response to the observance of defective chips using other monitoring. The test structure and method may also be used to characterize the effects of intentional modifications to existing processing parameters and equipment and to characterize the performance of new processes and equipment.
摘要翻译：描述了基于虚拟集成电路高度轮廓制造的插入测试结构以及使用用于表征集成电路制造方法和集成电路制造设备的插入式测试结构的方法。根据一个实施例，测试结构可以在垂直于完全或基本上完整的生产集成电路形貌的高度轮廓上制造。根据替代实施例，测试结构可以在垂直于部分完整的生产地形对应的高度轮廓上制造。测试结构和方法可用于表征潜在的高度剖面，并将系统和随机缺陷识别为常规监测的一部分，或者响应于使用其他监测对缺陷芯片的遵循。测试结构和方法也可用于表征对现有加工参数和设备的故意修改的影响，并表征新工艺和设备的性能。

94. 发明授权

US06274442B1 Transistor having a nitrogen incorporated epitaxially grown gate dielectric and method of making same 失效
标题翻译：具有氮的外延生长栅电介质的晶体管及其制造方法
公开(公告)号：US06274442B1
公开(公告)日：2001-08-14
申请号：US09116417
申请日：1998-07-15
申请人： Mark I. Gardner , H. Jim Fulford, Jr. , Charles E. May
发明人： Mark I. Gardner , H. Jim Fulford, Jr. , Charles E. May
IPC分类号： H01L21336
CPC分类号： H01L21/28202 , H01L29/513 , H01L29/518
摘要： An integrated circuit fabrication process is provided for incorporating barrier atoms, preferably nitrogen atoms, within a barrier layer. The barrier layer is interposed between the gate dielectric and the semiconductor substrate. The barrier layer serves to inhibit the passage of dopants from the gate conductor into the channel area. The barrier layer is preferably a nitrogen doped silicon epitaxial layer. The barrier layer may be composed of two layers, a silicon epitaxial layer and a nitrogen doped epitaxial layer formed upon the silicon epitaxial layer.
摘要翻译：提供集成电路制造方法，用于在屏障层内并入屏障原子，优选氮原子。阻挡层介于栅电介质和半导体衬底之间。阻挡层用于抑制掺杂剂从栅极导体进入沟道区的过程。阻挡层优选为氮掺杂硅外延层。阻挡层可以由两层构成，硅外延层和形成在硅外延层上的氮掺杂外延层。

95. 发明授权

US06261909B1 Semiconductor device having ultra shallow junctions and a reduced channel length and method for making same 有权
标题翻译：具有超浅结的半导体器件和减小的沟道长度及其制造方法
公开(公告)号：US06261909B1
公开(公告)日：2001-07-17
申请号：US09225389
申请日：1999-01-05
申请人： Mark I. Gardner , H. Jim Fulford , Charles E. May
发明人： Mark I. Gardner , H. Jim Fulford , Charles E. May
IPC分类号： H01L21336
CPC分类号： H01L29/66583 , H01L29/66613 , H01L29/7834
摘要： The present invention is directed to a method of forming a transistor having very shallow junctions and a reduced channel length, and a transistor incorporating same. In general, the method comprises forming a first process layer above a semiconducting substrate, and forming a second process layer comprised of an oxidation resistant material above the first process layer. The method continues with the formation of an opening in the first and second process layers and oxidation of the substrate lying within the opening to form a third process layer. Next, a second opening is formed in the third process layer, and a plurality of sidewall spacers are formed in the second opening. The method concludes with the formation of a gate dielectric above the substrate and between the sidewall spacers, the formation of a gate conductor above the gate dielectric, and the formation of a plurality of source and drain regions in the substrate. The transistor is comprised of a recess formed in the substrate, a gate dielectric positioned above the substrate lying within the recess, the interface between said gate dielectric and said substrate being positioned beneath the surface of said substrate. The transistor further comprises a gate conductor positioned above the gate dielectric, a plurality of sidewall spacers positioned adjacent the gate conductor, and a plurality of source/drain regions formed in the substrate.
摘要翻译：本发明涉及一种形成具有非常浅的结和减小的沟道长度的晶体管的方法，以及并入其的晶体管。通常，该方法包括在半导体衬底上形成第一工艺层，以及形成由第一工艺层上方的耐氧化材料构成的第二工艺层。该方法继续在第一和第二处理层中形成开口并且位于开口内的基板的氧化以形成第三处理层。接下来，在第三处理层中形成第二开口，并且在第二开口中形成多个侧壁间隔物。该方法的结论是在衬底之上和侧壁间隔物之间形成栅极电介质，在栅极电介质上形成栅极导体，以及在衬底中形成多个源极和漏极区域。晶体管由形成在基板中的凹槽，位于凹槽内的基板上方的栅介质构成，所述栅极电介质和所述基板之间的界面位于所述基板的表面之下。晶体管还包括位于栅极电介质上方的栅极导体，邻近栅极导体定位的多个侧壁间隔件，以及形成在基板中的多个源极/漏极区域。

96. 发明授权

US06261908B1 Buried local interconnect 失效
标题翻译：埋地方互联
公开(公告)号：US06261908B1
公开(公告)日：2001-07-17
申请号：US09123177
申请日：1998-07-27
申请人： Frederick N. Hause , Mark I. Gardner , Charles E. May
发明人： Frederick N. Hause , Mark I. Gardner , Charles E. May
IPC分类号： H01L21336
CPC分类号： H01L23/535 , H01L21/76895 , H01L2924/0002 , H01L2924/00
摘要： A method of fabricating a buried local interconnect in a substrate and an integrated circuit incorporating the same are provided. The method includes the steps forming a trench in the substrate and forming a first insulating layer in the trench. A conductor layer is formed on the first insulating layer. A portion of the conductor layer is removed to define a local interconnect layer and a second insulating layer is formed in the trench covering the local interconnect layer. The method provides for a local interconnect layer buried beneath a dielectric layer of an integrated circuit, such as a shallow trench isolation layer. Areas of a substrate above the silicon-silicon dioxide interface formerly reserved for local interconnect layers in conventional processing may now be used for additional conductor lines.
摘要翻译：提供了一种在衬底中制造掩埋局部互连的方法和包括其的集成电路。该方法包括在衬底中形成沟槽并在沟槽中形成第一绝缘层的步骤。导体层形成在第一绝缘层上。去除导体层的一部分以限定局部互连层，并且在覆盖局部互连层的沟槽中形成第二绝缘层。该方法提供了埋在诸如浅沟槽隔离层的集成电路的介电层下面的局部互连层。以前用于常规处理中的局部互连层的硅 - 二氧化硅界面上方的衬底区域现在可用于附加的导体线。

97. 发明授权

US06251800B1 Ultrathin deposited gate dielectric formation using low-power, low-pressure PECVD for improved semiconductor device performance 失效
标题翻译：使用低功率，低压PECVD的超薄沉积栅介质形成，以改善半导体器件性能
公开(公告)号：US06251800B1
公开(公告)日：2001-06-26
申请号：US09227513
申请日：1999-01-06
申请人： Sey-Ping Sun , Mark I. Gardner , Charles E. May
发明人： Sey-Ping Sun , Mark I. Gardner , Charles E. May
IPC分类号： H01L2131
CPC分类号： H01L21/28185 , C23C16/402 , H01L21/02164 , H01L21/02211 , H01L21/02274 , H01L21/0228 , H01L21/02332 , H01L21/02337 , H01L21/28194 , H01L21/31612
摘要： An ultrathin gate dielectric and a method for forming the same are provided. The gate dielectric is believed to allow enhanced performance of semiconductor devices including transistors and dual-gate memory cells. A low-power, low-pressure plasma-enhanced chemical vapor deposition (PECVD) method employing silane and nitrous oxide sources is used to deposit the dielectric. As compared to conventional PECVD deposition, the method uses lower silane and nitrous oxide flow rates, a more dilute silane in nitrogen mixture, a lower chamber pressure, and a lower radio frequency power density. These settings allow plasma conditions to stabilize so that deposition may be performed in time increments at least as short as 0.1 second, so that oxide thicknesses at least as small as one angstrom may be controllably deposited. The oxide is preferably deposited in portions at multiple substrate mounting positions in a deposition chamber. Combination of oxide portions in this manner is believed to reduce the density of pinholes in the oxide, and the low-power, low-pressure deposition conditions are further believed to reduce plasma damage to the oxide and reduce the density of trap states in the oxide. A rapid thermal anneal of the oxide may be performed after deposition, and may improve the quality of the interface between the oxide and the underlying semiconductor substrate.
摘要翻译：提供一种超薄栅极电介质及其形成方法。认为栅极电介质允许包括晶体管和双栅极存储器单元的半导体器件的增强的性能。使用采用硅烷和一氧化二氮源的低功率，低压等离子体增强化学气相沉积（PECVD）方法沉积电介质。与传统的PECVD沉积相比，该方法使用较低的硅烷和一氧化二氮流率，氮混合物中更稀的硅烷，较低的室压力和较低的射频功率密度。这些设置允许等离子体条件稳定，使得可以以至少短至0.1秒的时间增量执行沉积，使得至少小至一埃的氧化物厚度可以可控地沉积。优选在沉积室中的多个基板安装位置处部分地沉积氧化物。认为以这种方式组合氧化物部分可以降低氧化物中针孔的密度，并且进一步认为低功率，低压沉积条件可减少对氧化物的等离子体损伤并降低氧化物中陷阱态的密度。可以在沉积之后进行氧化物的快速热退火，并且可以提高氧化物和下面的半导体衬底之间的界面的质量。

98. 发明授权

US06245638B1 Trench and gate dielectric formation for semiconductor devices 有权
标题翻译：用于半导体器件的沟槽和栅极电介质形成
公开(公告)号：US06245638B1
公开(公告)日：2001-06-12
申请号：US09128235
申请日：1998-08-03
申请人： Mark I. Gardner , H. Jim Fulford , Charles E. May
发明人： Mark I. Gardner , H. Jim Fulford , Charles E. May
IPC分类号： H01L2176
CPC分类号： H01L21/76224 , H01L21/823462 , H01L21/823481 , Y10S148/05
摘要： Semiconductor device fabrication techniques which integrate the formation of trench isolation areas and gate insulating layers are provided. The fabrication techniques include forming one or more sacrificial layers, such as nitrided oxide layers, over regions of the substrate adjacent to a trench isolation region. The sacrificial layers are then removed prior to gate insulating layer formation. The formation of the sacrificial layers improves the trench structure and also improves the substrate surface for the subsequent formation of the gate insulating layer and gate electrode.
摘要翻译：提供集成沟槽隔离区域和栅极绝缘层的形成的半导体器件制造技术。制造技术包括在与沟槽隔离区相邻的衬底的区域上形成一个或多个牺牲层，例如氮化氧化物层。然后在形成栅极绝缘层之前去除牺牲层。牺牲层的形成改善了沟槽结构，并且还改善了衬底表面，以便随后形成栅极绝缘层和栅电极。

99. 发明授权

US06242317B1 High quality isolation structure formation 有权
标题翻译：高品质的隔离结构形成
公开(公告)号：US06242317B1
公开(公告)日：2001-06-05
申请号：US09264103
申请日：1999-03-08
申请人： Mark I. Gardner , Thien T. Nguyen , Charles E. May
发明人： Mark I. Gardner , Thien T. Nguyen , Charles E. May
IPC分类号： H01L2176
CPC分类号： H01L21/76224
摘要： A method is provided for fabricating an isolation structure, the method including forming a first dielectric layer above a structure and forming an opening in the first dielectric layer and the structure, the opening having sidewalls and a bottom. The method also includes forming a second dielectric layer within the opening on a first portion of the sidewalls and above the bottom of the opening. The method further includes forming a third dielectric layer within the opening adjacent the second dielectric layer and on a second portion of the sidewalls of the opening. The method also further includes passivating bonds in the third dielectric layer to reduce charge-trapping in the third dielectric layer, forming dielectric spacers within the opening adjacent the third dielectric layer and forming a dielectric filler within the opening adjacent the dielectric spacers and above the third dielectric layer.
摘要翻译：提供了一种用于制造隔离结构的方法，所述方法包括在结构上形成第一介电层，并在第一介电层和结构中形成开口，该开口具有侧壁和底部。该方法还包括在侧壁的第一部分和开口的底部之上的开口内形成第二电介质层。该方法还包括在邻近第二电介质层的开口内和在开口的侧壁的第二部分上形成第三电介质层。该方法还包括钝化第三电介质层中的键，以减少第三电介质层中的电荷捕获，在与第三电介质层相邻的开口内形成电介质间隔物，并在邻近电介质间隔物的开口内形成电介质填料，电介质层。

100. 发明授权

US06207485B1 Integration of high K spacers for dual gate oxide channel fabrication technique 失效
标题翻译：用于双栅极氧化物沟道制造技术的高K间隔物的集成
公开(公告)号：US06207485B1
公开(公告)日：2001-03-27
申请号：US09002725
申请日：1998-01-05
申请人： Mark I. Gardner , H. James Fulford , Charles E. May
发明人： Mark I. Gardner , H. James Fulford , Charles E. May
IPC分类号： H01L218238
CPC分类号： H01L21/28185 , H01L21/28202 , H01L21/28211 , H01L29/42368 , H01L29/518 , H01L29/66583
摘要： A semiconductor device has gate with a first material having a first dielectric constant adjacent the semiconductor substrate and a second material having a second dielectric constant adjacent the semiconductor substrate. A conductor, such as polysilicon, is then placed on the gate so that the first and second materials are sandwiched between the conductor and the semiconductor substrate. Since the dielectric constants of the two materials are different, the gate acts like a gate having a single dielectric with at least two thicknesses. This is due to the fact that each material has a dielectric constant that is different. One dielectric constant is larger than the other dielectric constant. The higher dielectric constant material is comprised of two spacers at the sidewalls of the gate. A layer of silicon dioxide is positioned on the semiconductor substrate between the spacers. The thickness of the spacers can be adjusted to optimize the performance of the semiconductor device.
摘要翻译：半导体器件具有栅极，第一材料具有邻近半导体衬底的第一介电常数和邻近半导体衬底的具有第二介电常数的第二材料。然后将诸如多晶硅的导体放置在栅极上，使得第一和第二材料夹在导体和半导体衬底之间。由于两种材料的介电常数不同，栅极的作用就像具有至少两个厚度的单个电介质的栅极。这是由于每种材料的介电常数不同。一个介电常数大于另一介电常数。较高介电常数材料由栅极侧壁上的两个间隔物组成。二氧化硅层位于半导体衬底上的间隔物之间。可以调整间隔件的厚度以优化半导体器件的性能。

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