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91. 发明授权

US5440156A Metal oxide semiconductor field effect transistor cell adaptable for use in an integrator 失效
标题翻译：适用于积分器的金属氧化物半导体场效应晶体管单元
公开(公告)号：US5440156A
公开(公告)日：1995-08-08
申请号：US986764
申请日：1992-12-08
申请人： Guoliang Shou , Weikang Yang , Wiwat Wongwirawipat , Sunao Takatori , Makoto Yamamoto
发明人： Guoliang Shou , Weikang Yang , Wiwat Wongwirawipat , Sunao Takatori , Makoto Yamamoto
IPC分类号： H01L21/8234 , H01L27/06 , H01L27/088 , H03F3/16 , H01L27/08 , G06G7/18 , H01L29/00 , H03K17/687
CPC分类号： H01L27/0629
摘要： A MOSFET wherein cell includes a MOSFET transistor having a gate connected to an input voltage signal for integration, a source grounded through a high resistance, and a drain connected to a power source. An output capacitor is connected to the source of the MOSFET transistor to complete the MOSFET cell.
摘要翻译：一种MOSFET，其中单元包括具有连接到用于积分的输入电压信号的栅极的MOSFET晶体管，通过高电阻接地的源极和连接到电源的漏极。输出电容器连接到MOSFET晶体管的源极以完成MOSFET单元。

92. 发明授权

US5396442A Multiplication circuit for multiplying analog inputs by digital inputs 失效
标题翻译：乘法电路，用于通过数字输入将模拟输入相乘
公开(公告)号：US5396442A
公开(公告)日：1995-03-07
申请号：US137738
申请日：1993-10-19
申请人： Guoliang Shou , Weikang Yang , Sunao Takatori , Makoto Yamamoto
发明人： Guoliang Shou , Weikang Yang , Sunao Takatori , Makoto Yamamoto
IPC分类号： G06J1/00 , H03M1/80
CPC分类号： G06J1/00 , H03M1/804
摘要： A multiplication circuit for multiplying an analog input by a digital input. The digital input has a plurality of bits. The circuit has a circuit input terminal for receiving the analog input and a circuit output terminal for outputting the results of multiplication of the analog input by the digital input. The circuit also has a plurality of capacitances and a plurality of switching devices.
摘要翻译：乘法电路，用于将模拟输入乘以数字输入。数字输入具有多个位。电路具有用于接收模拟输入的电路输入端子和用于输出通过数字输入的模拟输入相乘结果的电路输出端子。该电路还具有多个电容和多个开关装置。

93. 发明授权

US5394107A Absolute value circuit 失效
标题翻译：绝对值电路
公开(公告)号：US5394107A
公开(公告)日：1995-02-28
申请号：US111870
申请日：1993-08-26
申请人： Guoliang Shou , Sunao Takatori , Makoto Yamamoto
发明人： Guoliang Shou , Sunao Takatori , Makoto Yamamoto
IPC分类号： G01R19/22 , G06G7/25 , H03K5/00
CPC分类号： G01R19/22 , G06G7/25
摘要： An absolute value circuit for analog type processing combines an analog inverter circuit and a maximum circuit. The inverter circuit uses an operational amplifier comprised of CMOS inverters which are connected in a cascade with a gain of 1. The maximum circuit includes a pair of nMOS transistors, the source follower outputs of which are connected to a common output.
摘要翻译：用于模拟型处理的绝对值电路组合了模拟逆变器电路和最大电路。逆变器电路使用由CMOS反相器组成的运算放大器，其以1的增益级联连接。最大电路包括一对nMOS晶体管，其源极跟随器输出端连接到公共输出端。

94. 发明授权

US5363205A Image compressing method compressing an image into a compressed image and error coefficients 失效
标题翻译：图像压缩方法将图像压缩成压缩图像和误差系数
公开(公告)号：US5363205A
公开(公告)日：1994-11-08
申请号：US105058
申请日：1993-08-12
申请人： Guoliang Shou , Sunao Takatori , Makoto Yamamoto
发明人： Guoliang Shou , Sunao Takatori , Makoto Yamamoto
IPC分类号： H03M7/30 , H04N1/41 , H04N1/411 , H04N7/14 , H04N7/18 , H04N7/26 , H04N1/415 , H04N1/417 , H04N7/13
CPC分类号： H04N19/63
摘要： An image compression method which successively diminishes in size the image to form a compressed image. The compression is done by dividing an image into partial areas with equal size, calculating a mean pixel value in each area, and substituting the mean pixel value into the diminished image. The image is then re-enlarged in the same way, and the enlarged image is compared against the original image to determine error values. The error values and the diminished images are used to represent a compressed version of the original image.
摘要翻译：图像压缩方法，其连续地缩小图像以形成压缩图像。通过将图像划分为相同尺寸的部分区域来进行压缩，计算每个区域中的平均像素值，并将平均像素值代入缩小的图像。然后以相同的方式重新放大图像，并将放大的图像与原始图像进行比较以确定误差值。错误值和减少的图像用于表示原始图像的压缩版本。

95. 发明授权

US06252899B1 Complex despreading system 失效
标题翻译：复杂解扩系统
公开(公告)号：US06252899B1
公开(公告)日：2001-06-26
申请号：US09055346
申请日：1998-04-06
申请人： Chanming Zhou , Guoliang Shou
发明人： Chanming Zhou , Guoliang Shou
IPC分类号： H04L2730
CPC分类号： H04B1/7093
摘要： A compact and easily-assembled circuit for a complex despreading system, arranged such that the circuit does not contain pairs of adders at the output area. The configuration of the circuit enables the addition and subtraction of different signal components to occur before the multiplication stage and not at a pair of adders located at the output area The complex despreader system employs a complex matched filter at a receiver for despreading received signals with a QPSK system in the primary modulation and a BPSK system in the secondary modulation modulated at a transmitter. The input area of each matched filter of I and Q channels includes a pair of adders. One adder generates a first signal having a positive in-phase and a positive quadrature component. The other adder generates a second signal having a negative in-phase component and a positive quadrature component. Next, an I-channel multiplication circuit multiplies both components of the first signal by a spread code then adds the multiplication results together. Likewise, a Q-channel multiplication and addition circuit multiplies the components of the second signal by a spread code and then adds the multiplication results together.
摘要翻译：一种用于复杂解扩系统的紧凑且容易组装的电路，其布置成使得该电路在输出区域不包含加法器对。电路的配置使得不同信号分量的相加和减法在乘法阶段之前发生，而不是在位于输出区的一对加法器处。复数解扩器系统在接收机处采用复匹配滤波器来解扩接收信号一次调制中的QPSK系统和在发射机调制的二次调制中的BPSK系统。 I和Q通道的每个匹配滤波器的输入区域包括一对加法器。一个加法器产生具有正同相和正正交分量的第一信号。另一个加法器产生具有负同相分量和正正交分量的第二信号。接下来，I信道乘法电路将第一信号的两个分量乘以扩展码，然后将乘法结果相加。同样，Q信道乘法和加法电路将第二信号的分量乘以扩展码，然后将相乘结果相加。

96. 发明授权

US5789962A Multiplication circuit 失效
标题翻译：乘法电路
公开(公告)号：US5789962A
公开(公告)日：1998-08-04
申请号：US638330
申请日：1996-04-26
申请人： Guoliang Shou , Kazunori Motohashi , Jian Luo , Sunao Takatori , Makoto Yamamoto
发明人： Guoliang Shou , Kazunori Motohashi , Jian Luo , Sunao Takatori , Makoto Yamamoto
IPC分类号： G06J1/00 , G06F7/44
CPC分类号： G06J1/00
摘要： A multiplication circuit has two capacitive couplings connected first and second inverting amplifiers, respectively. Two steps of multiplication are performed by this circuit. Input is multiplied by a multiplier of a product of multipliers of the successive multiplication circuits, so the total multiplier can be rather large with similar capacitances to that of the conventional circuit.
摘要翻译：乘法电路分别具有连接第一和第二反相放大器的两个电容耦合。该电路执行两步乘法运算。输入乘以连续乘法电路的乘法乘积乘法器，因此与常规电路的乘法电容相似，总乘法器可能相当大。

97. 发明授权

US5751184A Low electrical power consumption filter circuit 失效
标题翻译：低功耗滤波电路
公开(公告)号：US5751184A
公开(公告)日：1998-05-12
申请号：US732895
申请日：1996-10-17
申请人： Guoliang Shou , Makoto Yamamoto , Sunao Takatori
发明人： Guoliang Shou , Makoto Yamamoto , Sunao Takatori
IPC分类号： H03H11/12 , H03K5/00
CPC分类号： H03H11/1217
摘要： A low electric power consumption filter circuit includes an amplifying portion including an odd number of serial MOS inverters. A grounded capacitance is connected between an output of the amplifying portion and ground. A pair of balancing resistances connect an output of the MOS inverter to a supply voltage and ground at a previous stage of the last MOS inverter. A feedback impedance connects an output of the amplifying portion to its input. An input impedance is connected to the input of the amplifying portion.
摘要翻译：低功耗滤波电路包括具有奇数个串联MOS反相器的放大部分。接地电容连接在放大部分的输出和地之间。一对平衡电阻将MOS逆变器的输出连接到最后一个MOS反相器的前一级的电源电压和接地。反馈阻抗将放大部分的输出连接到其输入。输入阻抗连接到放大部分的输入端。

98. 发明授权

US5748131A A/D converting circuit 失效
标题翻译： A / D转换电路
公开(公告)号：US5748131A
公开(公告)日：1998-05-05
申请号：US710307
申请日：1996-09-17
申请人： Kazunori Motohashi , Guoliang Shou , Makoto Yamamoto , Sunao Takatori
发明人： Kazunori Motohashi , Guoliang Shou , Makoto Yamamoto , Sunao Takatori
IPC分类号： H03M1/14 , H03M1/16 , H03M1/44 , H03M1/80 , H03M1/12
CPC分类号： H03M1/168 , H03M1/804
摘要： The present invention has an object to provide an A/D converting circuit with improved accuracy in an output. In this invention, the initial electric charge is given to a capacitive coupling for outputting in a quantizing circuit so as to cancel the dispersion of thresholds of MOS inverter in the quantizing circuit, the supply voltage of the first and the second inverters is higher than the supply voltage of an inverter for quantizing, as well as the initial electric charge is given to a capacitance for input in order to limit the function of the quantizing circuit within the linear area of the first and the second inverters.
摘要翻译：本发明的目的是提供一种具有改进的输出精度的A / D转换电路。在本发明中，初始电荷被赋予用于在量化电路中输出的电容耦合，以抵消量化电路中MOS反相器的阈值的偏差，第一和第二反相器的电源电压高于用于量化的逆变器的电源电压以及初始电荷被赋予用于输入的电容，以便限制第一和第二反相器的线性区域内的量化电路的功能。

99. 发明授权

US5602499A Multistage switching circuit 失效
标题翻译：多级开关电路
公开(公告)号：US5602499A
公开(公告)日：1997-02-11
申请号：US619416
申请日：1996-03-21
申请人： Guoliang Shou , Sunao Takatori , Makoto Yamamoto
发明人： Guoliang Shou , Sunao Takatori , Makoto Yamamoto
IPC分类号： G06G7/12 , H03K17/693 , H03M1/36 , H03M7/16 , H03K5/24
CPC分类号： H03K17/693 , H03M1/361 , H03M7/165
摘要： An analog type multistage switching circuit with a small circuit size and a small consumed electric power to having a plurality of thresholding circuits arranged in parallel to which an input voltage and a reference voltage are impressed through capacitive couplings which add the input voltage and reference voltage with weighting.
摘要翻译：一种具有小电路尺寸和小消耗电功率的模拟型多级开关电路，具有并联布置的多个阈值电路，通过电容耦合向输入电压和参考电压施加输入电压和参考电压，所述电容耦合将输入电压和参考电压与加权

100. 发明授权

US5568080A Computational circuit 失效
标题翻译：计算电路
公开(公告)号：US5568080A
公开(公告)日：1996-10-22
申请号：US467827
申请日：1995-06-06
申请人： Guoliang Shou , Sunao Takatori , Makoto Yamamoto
发明人： Guoliang Shou , Sunao Takatori , Makoto Yamamoto
IPC分类号： G06G7/06 , G06G7/14 , G06G7/26 , G06J1/00 , G06N3/063 , G11C27/02 , G06F7/44 , G06G7/16
CPC分类号： G11C27/024 , G06G7/06 , G06G7/14 , G06G7/26 , G06J1/00 , G06N3/0635
摘要： A computational circuit that includes a selector for providing an input to one of a plurality of sample/hold circuits. The outputs of the sample/hold circuits are provided to a multiplexer. The output of the multiplexer is provided to a computational portion, such as a multiplier.
摘要翻译：一种计算电路，包括用于向多个采样/保持电路之一提供输入的选择器。采样/保持电路的输出被提供给多路复用器。多路复用器的输出被提供给计算部分，例如乘法器。

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