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91. 发明授权

US07117466B2 System and method for correlated process pessimism removal for static timing analysis 失效
标题翻译：静态时序分析相关过程悲观消除的系统和方法
公开(公告)号：US07117466B2
公开(公告)日：2006-10-03
申请号：US10665273
申请日：2003-09-18
申请人： Kerim Kalafala , Peihua Qi , David J. Hathaway , Alexander J. Suess , Chandramouli Visweswariah
发明人： Kerim Kalafala , Peihua Qi , David J. Hathaway , Alexander J. Suess , Chandramouli Visweswariah
IPC分类号： G06F17/50
CPC分类号： G06F17/5031
摘要： A method of removing pessimism in static timing analysis is described. Delays are expressed as a function of discrete parameter settings allowing for both local and global variation to be taken in to account. Based on a specified target slack, each failing timing test is examined to determine a consistent set of parameter settings which produces the worst possible slack. The analysis is performed on a path basis. By considering only parameters which are in common to a particular data/clock path-pair, the number of process combinations that need to be explored is reduced when compared to analyzing all combinations of the global parameter settings. Further, if parameters are separable and linear, worst-case variable assignments for a particular clock/data path pair can be computed in linear time by independently assigning each parameter value. In addition, if available, the incremental delay change with respect to each physically realizable process variable may be used to project the worst-case variable assignment on a per-path basis without the need for performing explicit corner enumeration.
摘要翻译：描述了静态时序分析中消除悲观情绪的方法。延迟表示为离散参数设置的函数，允许将本地和全局变量都用于账户。根据指定的目标松弛，检查每个失败的定时测试，以确定一组一致的参数设置，从而产生最差的松弛。分析以路径为基础进行。通过仅考虑与特定数据/时钟路径对共同的参数，与分析全局参数设置的所有组合相比，需要探索的进程组合的数量减少。此外，如果参数是可分离的和线性的，则通过独立地分配每个参数值，可以在线性时间内计算特定时钟/数据路径对的最差情况变量分配。另外，如果可用，可以使用相对于每个物理上可实现的过程变量的增量延迟变化来在每个路径基础上投射最坏情况的变量赋值，而不需要执行明确的角点枚举。

92. 发明授权

US07093208B2 Method for tuning a digital design for synthesized random logic circuit macros in a continuous design space with optional insertion of multiple threshold voltage devices 失效
标题翻译：用于在连续设计空间中调整合成随机逻辑电路宏的数字设计的方法，并可选择插入多个阈值电压器件
公开(公告)号：US07093208B2
公开(公告)日：2006-08-15
申请号：US10842589
申请日：2004-05-10
申请人： Patrick M. Williams , Ee K. Cho , David J. Hathaway , Mei-Ting Hsu , Lawrence K. Lange , Gregory A. Northrop , Chandramouli Visweswariah , Cindy ShuiKing Washburn , Jun Zhou
发明人： Patrick M. Williams , Ee K. Cho , David J. Hathaway , Mei-Ting Hsu , Lawrence K. Lange , Gregory A. Northrop , Chandramouli Visweswariah , Cindy ShuiKing Washburn , Jun Zhou
IPC分类号： G06F17/50
CPC分类号： G06F17/505
摘要： A Digital Design Method which may be automated is for obtaining timing closure in the design of large, complex, high-performance digital integrated circuits. The methodincludes the use of a tuner on random logic macros that adjusts transistor sizes in a continuous domain. To accommodate this tuning, logic gates are mapped to parameterized cells for the tuning and then back to fixed gates after the tuning. Tuning is constrained in such a way as to minimize “binning errors” when the design is mapped back to fixed cells. Further, the critical sections of the circuit are marked in order to make the optimization more effective and to fit within the problem-size constraints of the tuner. A specially formulated objective function is employed during the tuning to promote faster global timing convergence, despite possibly incorrect initial timing budgets. The specially formulated objective function targets all paths that are failing timing, with appropriate weighting, rather than just targeting the most critical path. Finally, the addition of multiple threshold voltage gates allows for increased performance while limiting leakage power.
摘要翻译：可以自动化的数字设计方法是在大型，复杂，高性能数字集成电路的设计中获得定时关闭。该方法包括在随机逻辑宏中使用调谐器来调整连续域中的晶体管尺寸。为了适应这种调谐，逻辑门被映射到用于调谐的参数化单元，然后在调谐之后返回到固定门。调整受限于将设计映射回固定单元格时最小化“合并错误”。此外，电路的关键部分被标记以便使优化更有效并且适应调谐器的问题尺寸约束。在调整期间采用了特别制定的目标函数，以促进更快的全局时序收敛，尽管可能不正确的初始时间预算。特别制定的目标函数针对所有失败时机的路径，以适当的权重，而不是仅针对最关键的路径。最后，添加多个阈值电压门允许提高性能，同时限制漏电功率。

93. 发明授权

US07003747B2 Method of achieving timing closure in digital integrated circuits by optimizing individual macros 失效
标题翻译：通过优化单个宏来实现数字集成电路中的时序闭合的方法
公开(公告)号：US07003747B2
公开(公告)日：2006-02-21
申请号：US10435824
申请日：2003-05-12
申请人： Jun Zhou , David J. Hathaway , Chandramouli Visweswariah , Patrick M. Williams
发明人： Jun Zhou , David J. Hathaway , Chandramouli Visweswariah , Patrick M. Williams
IPC分类号： G06F17/50
CPC分类号： G06F17/5031 , G06F17/505 , G06F2217/84
摘要： Disclosed is a method for enhanced efficiency and effectiveness in achieving timing closure of large, complex, high-performance digital integrated circuits. Circuit macros are re-optimized and re-tuned in the timing closure loop by means of a reformulated objective function that allows the optimizer to improve the slack of all signals rather than just the most critical one(s). The incentive to improve the timing of a sub-critical signal is a diminishing function of the criticality of the signal. Thus all signals are improved during the optimization, with the highest incentive to improve on the most critical signals, leading to faster and more effective overall timing closure.
摘要翻译：公开了一种用于提高大型，复杂，高性能数字集成电路的定时闭合的效率和有效性的方法。电路宏通过重新配置的目标函数在时序闭合循环中重新优化和重新调整，允许优化器改善所有信号的松弛，而不仅仅是最关键的。改善次临界信号时序的动机是信号临界性的递减函数。因此，在优化期间，所有信号都得到改进，最高激励措施可以改善最关键的信号，从而实现更快更有效的整体时序收敛。

94. 发明申请

US20050091298A1 Affinity-based clustering of vectors for partitioning the columns of a matrix 有权
标题翻译：用于分割矩阵列的矢量的基于亲和度聚类
公开(公告)号：US20050091298A1
公开(公告)日：2005-04-28
申请号：US10696511
申请日：2003-10-28
申请人： Kerim Kalafala , Vasant Rao , Chandramouli Visweswariah
发明人： Kerim Kalafala , Vasant Rao , Chandramouli Visweswariah
IPC分类号： G06F12/00
CPC分类号： G06F17/5031 , G06K9/6226 , G06K9/6247
摘要： A method and computer program product for partitioning the columns of a matrix A. The method includes providing the matrix A in a memory device of a computer system. The matrix A has n columns and m rows, wherein n is an integer of at least 3, and wherein m is an integer of at least 1. The method further includes executing an algorithm by a processor of the computer system. Executing the algorithm includes partitioning the n columns of the matrix A into a closed group of p clusters, wherein p is a positive integer of at least 2 and less than n, wherein the partitioning includes an affinity-based merging of clusters of the matrix A, and wherein each cluster is a collection of one or more columns of A.
摘要翻译：一种用于分割矩阵A的列的方法和计算机程序产品。该方法包括将矩阵A提供到计算机系统的存储器设备中。矩阵A具有n列和m行，其中n是至少为3的整数，并且其中m是至少为1的整数。该方法还包括由计算机系统的处理器执行算法。执行算法包括将矩阵A的n列划分成闭合的p个群集，其中p是至少为2且小于n的正整数，其中分区包括基于关系的矩阵A的簇的合并，并且其中每个聚类是A的一列或多列的集合。

95. 发明授权

US06321362B1 Method of reformulating static circuit optimization problems for reduced size, degeneracy and redundancy 失效
标题翻译：重构静态电路优化问题的方法是减小尺寸，简并性和冗余性
公开(公告)号：US06321362B1
公开(公告)日：2001-11-20
申请号：US09286758
申请日：1999-04-06
申请人： Andrew R. Conn , Chandramouli Visweswariah
发明人： Andrew R. Conn , Chandramouli Visweswariah
IPC分类号： G06F1750
CPC分类号： G06F17/505
摘要： A method of pruning an initial timing graph for static optimization of a digital circuit includes examining a first group of nodes, which in turn include at least a first one of the nodes in the initial timing graph, to determine whether every node in the first group is prunable. The method further includes pruning the first group by pruning every node therein, if every node therein is prunable, and if the pruning would be beneficial. Furthermore, the method includes repeating the examining and pruning steps for a substantial number of additional groups of nodes, so as to create a pruned timing graph having enhanced numerical qualities and/or compactness compared to an initial timing graph. The pruning can be conducted on groups of more than one node at a time, or on only individual nodes at one time. Reduced size, and the benefits thereof, can be determined by a comparison of the number of nodes and number of directed edges before pruning, with the number of nodes and the number of directed edges after pruning, by summing the quantities before pruning and comparing the sum to the summed quantities after pruning, with or without weighting. Preferably, multistep pruning can be employed to first perform all pruning operations with a gain of a certain value, and to continue for gains of lower values. In an alternative method, an explicit representation of the problem as a timing graph is not employed, but the circuit optimization problem is restated in an analogous manner by pruning arrival times and manipulating constraints.
摘要翻译：修剪用于数字电路的静态优化的初始时序图的方法包括检查第一组节点，其又包括初始定时图中的至少第一节点，以确定第一组中的每个节点是可修剪的该方法还包括通过修剪第一组来修剪其中的每个节点，如果其中的每个节点都是可修剪的，以及如果修剪将是有益的。此外，该方法包括对大量附加的节点组重复检查和修剪步骤，以便与初始定时图相比创建具有增强的数字质量和/或紧凑性的修剪的时序图。修剪可以一次在多个节点的组上进行，也可以一次在单独的节点上进行。缩小尺寸及其优点可以通过对剪枝前的节点数量和有向边缘数量的比较以及剪枝后的节点数量和定向边缘数量进行比较，通过对修剪前的数量进行求和，并比较总和到修剪后的总量，有或没有加权。优选地，可以采用多步修剪来首先以增加一定值进行所有修剪操作，并继续获得更低的值。在替代方法中，不采用作为时序图的问题的显式表示，但是通过修剪到达时间和操纵约束以类似的方式重述电路优化问题。

96. 发明授权

US5999714A Method for incorporating noise considerations in automatic circuit optimization 失效
标题翻译：将噪声考虑纳入自动电路优化的方法
公开(公告)号：US5999714A
公开(公告)日：1999-12-07
申请号：US56430
申请日：1998-04-07
申请人： Andrew Roger Conn , Rudolf Adriaan Haring , Chandramouli Visweswariah
发明人： Andrew Roger Conn , Rudolf Adriaan Haring , Chandramouli Visweswariah
IPC分类号： G06F17/50 , G06F9/455
CPC分类号： G06F17/5036 , G06F17/5063
摘要： A method of incorporating noise considerations during circuit optimization includes the steps of: specifying a circuit schematic to be optimized; specifying at least one noise criterion as a noise measurement, including the signal to be checked for noise, the sub-interval of time of interest, and the maximum allowable noise deviation; providing each noise criterion as either a semi-infinite constraint or a semi-infinite objective function; specifying at least one variable of the optimization; converting the semi-infinite noise constraints and the semi-infinite noise objective functions into time-integral equality constraints; optionally, if required, providing additional optimization criteria other than noise as, for each such criterion, either objective functions or constraints; creating a merit function to be minimized to solve the optimization problem; simulating the circuit in the time-domain; computing the values of the objective functions and constraints; efficiently computing the gradients of the merit function of the optimizer (including contributions of all objective functions and constraints and the time-integrals representing noise considerations) preferably by means of a single adjoint analysis; iteratively providing the constraint values, the objective function values and the gradients of the merit function to a nonlinear optimizer; and continuing the optimization iterations to convergence.
摘要翻译：在电路优化期间引入噪声考虑的方法包括以下步骤：指定要优化的电路原理图; 将至少一个噪声标准指定为噪声测量，包括要检查噪声的信号，感兴趣的时间的次间隔和最大允许噪声偏差; 将每个噪声标准提供为半无限约束或半无限目标函数; 指定优化的至少一个变量; 将半无限噪声约束和半无限噪声目标函数转换为时间积分等式约束; 可选地，如果需要，提供除噪声之外的附加优化标准，对于每个这样的标准，目标函数或约束; 创建优化函数以最小化以解决优化问题; 在时域模拟电路; 计算目标函数和约束的值; 优选地通过单个伴随分析来优化优化器的优值函数的梯度（包括所有目标函数和约束的贡献以及表示噪声考虑的时间积分）; 将优化函数的约束值，目标函数值和梯度迭代地提供给非线性优化器; 并继续优化迭代来收敛。

97. 发明授权

US08775988B2 Decentralized dynamically scheduled parallel static timing analysis 失效
标题翻译：分散式动态调度并行静态时序分析
公开(公告)号：US08775988B2
公开(公告)日：2014-07-08
申请号：US13150445
申请日：2011-06-01
申请人： Mark A. Lavin , David J. Hathaway , Kerim Kalafala , Jeffrey S. Piaget , Chandramouli Visweswariah
发明人： Mark A. Lavin , David J. Hathaway , Kerim Kalafala , Jeffrey S. Piaget , Chandramouli Visweswariah
IPC分类号： G06F17/50 , G06F9/455
CPC分类号： G06F17/504 , G06F2217/84
摘要： A method for performing a parallel static timing analysis in which multiple processes independently update a timing graph without requiring communication through a central coordinator module. Local processing queues are used to reduce locking overhead without causing excessive load imbalance. A parallel analysis is conducted on a circuit design represented by a timing graph formed by a plurality of interconnected nodes, the method including: using a computer for creating a shared work queue of ready to process independent nodes; assigning the independent nodes from the work queue to at least two parallel computation processes, simultaneously performing node analysis computations thereof; and modifying the circuit design by updating values of the processed independent nodes obtained from the node analysis, the at least two parallel computation processes independently updating the shared work queue to process a new plurality of independent nodes.
摘要翻译：一种用于执行并行静态时序分析的方法，其中多个进程独立地更新时序图，而不需要通过中央协调器模块进行通信。本地处理队列用于减少锁定开销，而不会导致过大的负载不平衡。对由多个互连节点形成的时序图表示的电路设计进行并行分析，该方法包括：使用计算机创建准备处理独立节点的共享工作队列; 将独立节点从工作队列分配到至少两个并行计算过程，同时执行其节点分析计算; 以及通过更新从所述节点分析获得的经处理的独立节点的值来修改所述电路设计，所述至少两个并行计算处理独立地更新所述共享工作队列以处理新的多个独立节点。

98. 发明授权

US08732642B2 Method for achieving an efficient statistical optimization of integrated circuits 有权
标题翻译：实现集成电路有效统计优化的方法
公开(公告)号：US08732642B2
公开(公告)日：2014-05-20
申请号：US13564751
申请日：2012-08-02
申请人： Chandramouli Visweswariah , Eric Fluhr , Stephen G. Shuma , Debjit Sinha , Michael H. Wood
发明人： Chandramouli Visweswariah , Eric Fluhr , Stephen G. Shuma , Debjit Sinha , Michael H. Wood
IPC分类号： G06F9/455
CPC分类号： G06F17/5031
摘要： Method for performing timing closure of integrated circuits in the presence of manufacturing and environmental variations. The starting design is analyzed using statistical static timing analysis to determine timing violations. Each timing violation in its statistical canonical form is examined. In a first aspect of the invention, the canonical failing slack is inspected to determine what type of move is most likely to fix the timing violation taking into account all relevant manufacturing and environmental variations. In a second aspect of the invention, pre-characterized moves such as insertion of delay pad cells are evaluated for their ability to fix the timing violation without triggering timing, and the best move or set of moves is selected.
摘要翻译：在存在制造和环境变化的情况下执行集成电路的定时关闭的方法。使用统计静态时序分析来分析起始设计，以确定时序违规。检查其统计规范形式的每个时间违规。在本发明的第一方面，检查规范的故障松弛以确定哪种类型的移动最有可能在考虑到所有相关的制造和环境变化的情况下修复定时违规。在本发明的第二方面中，评估了诸如插入延迟垫单元之类的预先表征的移动能够固定定时违反而不触发定时，并且选择最佳移动或移动集合。

99. 发明授权

US08707233B2 Systems and methods for correlated parameters in statistical static timing analysis 失效
标题翻译：统计静态时序分析中相关参数的系统和方法
公开(公告)号：US08707233B2
公开(公告)日：2014-04-22
申请号：US13190083
申请日：2011-07-25
申请人： Eric A. Foreman , Peter A. Habitz , David J. Hathaway , Jeffrey G. Hemmett , Natesan Venkateswaran , Chandramouli Visweswariah , Vladimir Zolotov
发明人： Eric A. Foreman , Peter A. Habitz , David J. Hathaway , Jeffrey G. Hemmett , Natesan Venkateswaran , Chandramouli Visweswariah , Vladimir Zolotov
IPC分类号： G06F9/455 , G06F17/50
CPC分类号： G06F17/5031 , G06F17/5081
摘要： Systems and methods for accommodating correlated parameters in SSTA are provided. The method includes determining a correlation between at least two parameters. The method further includes calculating a new parameter or a new parameter set based on the correlation between the at least two parameters. The method further includes performing the SSTA such that the new parameter or the new parameter set is propagated into the SSTA. The method further includes projecting slack using the correlation between the at least two parameters and using a processor.
摘要翻译：提供了适应SSTA相关参数的系统和方法。该方法包括确定至少两个参数之间的相关性。该方法还包括基于至少两个参数之间的相关性计算新参数或新参数集。该方法还包括执行SSTA，使得新参数或新参数集传播到SSTA中。该方法还包括使用至少两个参数之间的相关性并使用处理器来投影松弛。

100. 发明授权

US08689158B2 System and method for performing static timing analysis in the presence of correlations between asserted arrival times 失效
标题翻译：在断言到达时间之间存在相关性的情况下执行静态时序分析的系统和方法
公开(公告)号：US08689158B2
公开(公告)日：2014-04-01
申请号：US12944059
申请日：2010-11-11
申请人： Kerim Kalafala , Jennifer E. Basile , David J. Hathaway , Jeffrey G. Hemmett , Peihua Qi , Natesan Venkateswaran , Chandramouli Visweswariah , Vladimir Zolotov
发明人： Kerim Kalafala , Jennifer E. Basile , David J. Hathaway , Jeffrey G. Hemmett , Peihua Qi , Natesan Venkateswaran , Chandramouli Visweswariah , Vladimir Zolotov
IPC分类号： G06F17/50
CPC分类号： G06F17/504 , G06F2217/84
摘要： A method of applying common path credit in a static timing analysis in the presence of correlations between asserted arrival times, comprising the steps of using a computer, identifying one or more pairs of asserted arrival times for which one or more correlations exist; propagating to each of the one or more pairs of asserted arrival times a timing value dependent on the one or more correlations; and performing a subsequent common path pessimism removal analysis for at least one test during which a timing value dependent on the one or more correlations between asserted arrival times is used to compute an adjusted test slack.
摘要翻译：一种在断言到达时间之间的相关性存在的静态时序分析中应用公共路径信用的方法，包括以下步骤：使用计算机识别存在一个或多个相关性的一个或多个断言到达时间对; 将所述一个或多个断言到达时间对中的每一个传播到取决于所述一个或多个相关性的定时值; 以及对至少一个测试执行随后的公共路径悲观消除分析，在该测试期间，使用取决于所述到达时间之间的一个或多个相关性的定时值来计算经调整的测试松弛。

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