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1. 发明授权

US06321362B1 Method of reformulating static circuit optimization problems for reduced size, degeneracy and redundancy 失效
标题翻译：重构静态电路优化问题的方法是减小尺寸，简并性和冗余性
公开(公告)号：US06321362B1
公开(公告)日：2001-11-20
申请号：US09286758
申请日：1999-04-06
申请人： Andrew R. Conn , Chandramouli Visweswariah
发明人： Andrew R. Conn , Chandramouli Visweswariah
IPC分类号： G06F1750
CPC分类号： G06F17/505
摘要： A method of pruning an initial timing graph for static optimization of a digital circuit includes examining a first group of nodes, which in turn include at least a first one of the nodes in the initial timing graph, to determine whether every node in the first group is prunable. The method further includes pruning the first group by pruning every node therein, if every node therein is prunable, and if the pruning would be beneficial. Furthermore, the method includes repeating the examining and pruning steps for a substantial number of additional groups of nodes, so as to create a pruned timing graph having enhanced numerical qualities and/or compactness compared to an initial timing graph. The pruning can be conducted on groups of more than one node at a time, or on only individual nodes at one time. Reduced size, and the benefits thereof, can be determined by a comparison of the number of nodes and number of directed edges before pruning, with the number of nodes and the number of directed edges after pruning, by summing the quantities before pruning and comparing the sum to the summed quantities after pruning, with or without weighting. Preferably, multistep pruning can be employed to first perform all pruning operations with a gain of a certain value, and to continue for gains of lower values. In an alternative method, an explicit representation of the problem as a timing graph is not employed, but the circuit optimization problem is restated in an analogous manner by pruning arrival times and manipulating constraints.
摘要翻译：修剪用于数字电路的静态优化的初始时序图的方法包括检查第一组节点，其又包括初始定时图中的至少第一节点，以确定第一组中的每个节点是可修剪的该方法还包括通过修剪第一组来修剪其中的每个节点，如果其中的每个节点都是可修剪的，以及如果修剪将是有益的。此外，该方法包括对大量附加的节点组重复检查和修剪步骤，以便与初始定时图相比创建具有增强的数字质量和/或紧凑性的修剪的时序图。修剪可以一次在多个节点的组上进行，也可以一次在单独的节点上进行。缩小尺寸及其优点可以通过对剪枝前的节点数量和有向边缘数量的比较以及剪枝后的节点数量和定向边缘数量进行比较，通过对修剪前的数量进行求和，并比较总和到修剪后的总量，有或没有加权。优选地，可以采用多步修剪来首先以增加一定值进行所有修剪操作，并继续获得更低的值。在替代方法中，不采用作为时序图的问题的显式表示，但是通过修剪到达时间和操纵约束以类似的方式重述电路优化问题。

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