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91. 发明申请

US20070070769A1 CIRCUIT AND METHOD FOR CONTROLLING A STANDBY VOLTAGE LEVEL OF A MEMORY 有权
标题翻译：用于控制存储器的待机电压电平的电路和方法
公开(公告)号：US20070070769A1
公开(公告)日：2007-03-29
申请号：US11162847
申请日：2005-09-26
申请人： George Braceras , John Fifield , Harold Pilo
发明人： George Braceras , John Fifield , Harold Pilo
IPC分类号： G11C5/14
CPC分类号： G11C11/417 , G11C5/147
摘要： A memory is provided which can be operated at an active rate of power consumption in an active operational mode and at a predetermined reduced rate of power consumption in a standby operational mode. The memory includes a current generating circuit which is operable to supply a predetermined magnitude of current to a sample power supply input terminal of a sample memory cell representative of memory cells of the memory, the predetermined magnitude of current corresponding to the predetermined reduced rate of power consumption. A voltage follower circuit is operable to output a standby voltage level equal to a voltage level at the sample power supply input terminal when the predetermined magnitude of current is supplied thereto. A memory cell array of the memory is operable to store data. In the standby operational mode, a switching circuit is operable to supply power at the standby voltage level to a power supply input terminal of the memory cell array. This permits data to remain stored in the memory during the standby mode. During an active operational mode, the switching circuit is operable to connect the power supply input terminal at the power supply to supply power at the active voltage level to the memory cell array. During the active operational mode, data can be stored into the memory cell array and retrieved from the memory cell array.
摘要翻译：提供一种存储器，其可以在主动操作模式中以在备用操作模式中以预定的降低的功率消耗速率以有效的功率消耗速率操作。存储器包括电流产生电路，其可操作以向代表存储器的存储器单元的采样存储单元的采样电源输入端提供预定大小的电流，与预定的降低的功率比相对应的预定电流值消费。电压跟随器电路可操作以当提供预定电流大小时输出等于采样电源输入端的电压电平的备用电压电平。存储器的存储单元阵列可操作以存储数据。在待机操作模式中，切换电路可操作以将备用电压电平的电力提供给存储单元阵列的电源输入端。这在待机模式期间允许数据保存在存储器中。在有效操作模式期间，开关电路可操作地连接电源处的电源输入端，以将有源电压电平的电力提供给存储单元阵列。在主动操作模式期间，可将数据存储到存储单元阵列中并从存储单元阵列检索。

92. 发明申请

US20060171189A1 SRAM CELL USING TUNNEL CURRENT LOADING DEVICES 失效
标题翻译：使用隧道电流负载装置的SRAM单元
公开(公告)号：US20060171189A1
公开(公告)日：2006-08-03
申请号：US10906056
申请日：2005-02-01
申请人： Wagdi Abadeer , John Fifield , Harold Pilo
发明人： Wagdi Abadeer , John Fifield , Harold Pilo
IPC分类号： G11C11/00
CPC分类号： H01L27/1104 , G11C11/412
摘要： An SRAM cell with gate tunneling load devices. The SRAM cell uses PFET wordline transistors and NFET cross-coupled transistors. The PFET wordline transistors are fully conductive during read operations, thus a full voltage level is passed through the PFET to the high node of the cell from the bitline. Tunnel current load devices maintain the high node of the cell at full voltage level during standby state.
摘要翻译：具有栅极隧道负载装置的SRAM单元。 SRAM单元使用PFET字线晶体管和NFET交叉耦合晶体管。 PFET字线晶体管在读取操作期间是完全导电的，因此，整个电压电平从位线通过PFET到电池的高节点。隧道电流负载设备在待机状态下将电池的高节点保持在全电压电平。

93. 发明授权

US06989685B1 Method and system for maintaining uniform module junction temperature during burn-in 有权
标题翻译：在老化期间保持模块结温均匀的方法和系统
公开(公告)号：US06989685B1
公开(公告)日：2006-01-24
申请号：US10711040
申请日：2004-08-19
申请人： Kevin C. Andersen , John A. Fifield , Harold Pilo
发明人： Kevin C. Andersen , John A. Fifield , Harold Pilo
IPC分类号： G01R31/26
CPC分类号： G01R31/2874 , G01R31/2856
摘要： A method for controlling the burn-in temperature of a semiconductor chip includes determining a DC current of the chip, and determining a difference between the DC current and a target current, the target current being selected to produce a desired chip temperature. An operating frequency of the chip is calculated, based on the determined difference between the DC current and the target current, so as generate an additional AC component of current to attain the target current.
摘要翻译：用于控制半导体芯片的老化温度的方法包括：确定芯片的直流电流，确定直流电流与目标电流之间的差值，选择目标电流以产生所需的芯片温度。基于确定的直流电流和目标电流之间的差来计算芯片的工作频率，从而产生额外的电流分量以获得目标电流。

94. 发明授权

US06944090B2 Method and circuit for precise timing of signals in an embedded DRAM array 失效
标题翻译：用于嵌入式DRAM阵列中信号精确定时的方法和电路
公开(公告)号：US06944090B2
公开(公告)日：2005-09-13
申请号：US10604184
申请日：2003-06-30
申请人： Darren L. Anand , John A. Fifield , Harold Pilo
发明人： Darren L. Anand , John A. Fifield , Harold Pilo
IPC分类号： G11C29/02 , G11C8/00
CPC分类号： G11C29/50012 , G11C11/401 , G11C29/02 , G11C2029/0401 , G11C2029/1204
摘要： A method and circuit for timing the start of a precharge period in an eDRAM. The circuit including: a delayed lock loop circuit for receiving a clock signal and generating a control signal for adjusting an internal delay of the clock signal; and means for generating a delayed clock signal in response to the control signal. The means for generating the delayed clock signal is a multiple stage delay circuit, each stage of the multiple delay stage circuit connected in series and each stage individually responsive to the control signal.
摘要翻译：一种用于定时在eDRAM中预充电期间开始的方法和电路。该电路包括：延迟锁定环电路，用于接收时钟信号并产生用于调整时钟信号的内部延迟的控制信号; 以及用于响应于控制信号产生延迟的时钟信号的装置。用于产生延迟时钟信号的装置是多级延迟电路，多级延迟级电路的每级串联连接，每级分别响应控制信号。

95. 发明申请

US20050041480A1 METHOD FOR TRANSPARENT UPDATES OF OUTPUT DRIVER IMPEDANCE 失效
标题翻译：输出驱动器阻抗的透明更新方法
公开(公告)号：US20050041480A1
公开(公告)日：2005-02-24
申请号：US10604867
申请日：2003-08-22
申请人： Phillip Corson , Harold Pilo
发明人： Phillip Corson , Harold Pilo
IPC分类号： G11C5/00 , G11C7/00 , G11C7/10 , G11C7/22 , G11C11/419
CPC分类号： G11C7/1069 , G11C7/1051 , G11C7/22 , G11C7/222 , G11C11/419 , G11C2207/2254
摘要： Disclosed is a method and structure that controls an output driver by generating an output data path clock signal from a system clock signal and timing the programmable impedance of the output driver according to the output data path clock signal. The method/structure controls the timing of the line driver circuits according to the output data path clock signal. By timing the programmable impedance according to the output data path clock signal, the timing of delivery of an impedance control signal is coordinated with the timing of delivery of data. The method/structure also performs impedance updates on the output driver more frequently during initialization cycles than in cycles that occur after the initialization cycles expire using at least two differently timed clock dividers and a counter.
摘要翻译：公开了一种通过从系统时钟信号产生输出数据路径时钟信号并根据输出数据路径时钟信号对输出驱动器的可编程阻抗进行定时来控制输出驱动器的方法和结构。该方法/结构根据输出数据路径时钟信号来控制线路驱动电路的定时。通过根据输出数据路径时钟信号对可编程阻抗进行定时，将阻抗控制信号的传递时序与数据传送的时序协调。该方法/结构还在初始化周期期间更频繁地对输出驱动器进行阻抗更新，而不是在使用至少两个不同时间的时钟分频器和计数器的初始化周期到期后发生的周期。

96. 发明授权

US06501675B2 Alternating reference wordline scheme for fast DRAM 有权
标题翻译：快速DRAM的交替参考字线方案
公开(公告)号：US06501675B2
公开(公告)日：2002-12-31
申请号：US09854987
申请日：2001-05-14
申请人： Harold Pilo , Robert E. Busch
发明人： Harold Pilo , Robert E. Busch
IPC分类号： G11C1124
CPC分类号： G11C8/14 , G11C7/14 , G11C11/4099
摘要： A fast DRAM memory uses ground-sensing as opposed to traditional Vdd/2 sensing. A selected DRAM cell connects to a bit-line true (BLT) or a bit-line complement (BLC). At the start of each cycle the BLT and BLC are restored to ground potential. A pair of alternating reference cells are provided for each bit-line. When a selected DRAM cell is connected either BLT or BLC the first reference cell in the pair is connected to the other bitline to provide a reference voltage to the other bitline which can be compared to the voltage provided by the selected DRAM cell. On a subsequent cycle using the same bitline the second reference cell in the pair is used. Thus it is not necessary to wait for the first reference cell to recharge prior to beginning the next cycle. Switching between the first and second reference cells in the pair alternates in this manner resulting in faster cycle time. The write-back of the reference cells can be hidden since an alternate cell is available for next cycle's reference bitline generation.
摘要翻译：快速DRAM存储器使用地面感测，而不是传统的Vdd / 2感测。所选择的DRAM单元连接到位线真（BLT）或位线补码（BLC）。在每个循环开始时，BLT和BLC恢复到地电位。为每个位线提供一对交替参考单元。当所选择的DRAM单元连接到BLT或BLC时，该对中的第一参考单元连接到另一位线，以向可与所选择的DRAM单元提供的电压进行比较的另一位线提供参考电压。在使用相同位线的后续周期中，使用该对中的第二参考单元。因此，在开始下一个周期之前，不需要等待第一个参考单元进行充电。该对中的第一和第二参考单元之间的切换以这种方式交替地产生更快的周期时间。可以隐藏参考单元的回写，因为替代单元可用于下一循环的参考位线生成。

97. 发明授权

US06449200B1 Duty-cycle-efficient SRAM cell test 失效
标题翻译：占空比高效的SRAM单元测试
公开(公告)号：US06449200B1
公开(公告)日：2002-09-10
申请号：US09907325
申请日：2001-07-17
申请人： Erik A. Nelson , Harold Pilo
发明人： Erik A. Nelson , Harold Pilo
IPC分类号： G11C700
CPC分类号： G11C29/28 , G11C29/34
摘要： A method and structure for the invention includes an integrated memory structure having a built-in test portion. The integrated memory structure has memory cells, bitlines and wordlines connected to the memory cells, wordline decoders connected to a plurality of the wordlines, bitline restore devices connected to the bitlines for charging the bitlines during read and write operations, and a clock circuit connected to the wordlines. During a test mode the wordline decoders simultaneously select multiple wordlines that the bitline restore devices maintain in an active state and the clock circuit maintains th multiple wordlines and the bitline restore devices in an active state for a period in excess of a normal read cycle. The invention also includes transistors which are connected to the memory cells. The transistors include bitline contacts which are stressed during the test mode.
摘要翻译：本发明的方法和结构包括具有内置测试部分的集成存储器结构。集成存储器结构具有连接到存储器单元的存储单元，位线和字线，连接到多个字线的字线解码器，连接到位线的位线恢复器件，用于在读和写操作期间对位线充电;以及时钟电路，字线。在测试模式期间，字线解码器同时选择位线恢复装置维持在活动状态的多个字线，并且时钟电路将多个字线和位线恢复装置维持在超过正常读周期的周期内处于活动状态。本发明还包括连接到存储单元的晶体管。晶体管包括在测试模式期间受应力的位线触点。

98. 发明授权

US06219288B1 Memory having user programmable AC timings 失效
标题翻译：具有用户可编程交流定时的存储器
公开(公告)号：US06219288B1
公开(公告)日：2001-04-17
申请号：US09519392
申请日：2000-03-03
申请人： Geordie M. Braceras , Steven H. Lamphier , Harold Pilo
发明人： Geordie M. Braceras , Steven H. Lamphier , Harold Pilo
IPC分类号： G11C700
CPC分类号： G11C11/417 , G11C7/1045 , G11C7/22
摘要： A SRAM module provides programmability of AC timings such that an end user can adjust or “tweak” the AC timings to maximize system performance. A variable delay circuit is placed in the path between a signal (e.g., data signal or address signal)and the SRAM set-up and hold register which allows the user to shift the setup-and-hold window by selected increments. The delay circuit can either advance or retard the AC timings. A delay program controlling the delay circuit is selected in one of two ways; either by a default AC timing program stored in a ROM device and preset by the manufacturer, or by a private JTAG instruction and AC programming data input by the user through the JTAG state machine provided on the SRAM chip. Once the optimum delay (or advance) is selected to optimize the SRAM to the cache system this user program may be permanently burned into the default ROM such that the optimum timings are used thereafter as the default.
摘要翻译： SRAM模块提供AC定时的可编程性，使得最终用户可以调整或“调整”AC定时以最大化系统性能。可变延迟电路被放置在信号（例如，数据信号或地址信号）和SRAM建立和保持寄存器之间的路径中，该寄存器允许用户按照选定的增量来移动建立和保持窗口。延迟电路可以提前或延迟交流定时。以两种方式之一选择控制延迟电路的延迟程序; 通过存储在ROM设备中并由制造商预设的默认AC定时程序，或通过由SRAM芯片上提供的JTAG状态机由用户输入的专用JTAG指令和AC编程数据。一旦选择了最佳延迟（或提前）来优化到高速缓存系统的SRAM，该用户程序可以被永久地烧录到默认ROM中，使得此后使用最佳定时作为默认值。

99. 发明授权

US5978929A Computer unit responsive to difference between external clock period and circuit characteristic period 失效
标题翻译：计算机单元响应外部时钟周期和电路特性周期之间的差异
公开(公告)号：US5978929A
公开(公告)日：1999-11-02
申请号：US822912
申请日：1997-03-20
申请人： Jim Covino , Harold Pilo
发明人： Jim Covino , Harold Pilo
IPC分类号： G11C7/22 , G11C11/413 , G06F1/04
CPC分类号： G11C7/22 , G11C11/413 , G11C7/04
摘要： An integrated circuit such as a SRAM is connected to receive externally generated clock cycles. A delay period is generated within the circuit which is independent of the rate of the clock cycles. The rate of the clock cycles is compared to a delay period and the operation of the integrated circuit is varied depending on the comparison. The integrated circuit adapts itself to changes in operating temperature, applied voltages, process variations which result in structural or materials differences between devices, and changes in the rate of externally generated clock cycles.
摘要翻译：连接诸如SRAM的集成电路以接收外部产生的时钟周期。在电路内产生与时钟周期的速率无关的延迟周期。将时钟周期的速率与延迟时间进行比较，并且根据比较来改变集成电路的操作。集成电路适应于工作温度，施加电压，工艺变化的变化，导致器件之间的结构或材料差异以及外部产生的时钟周期速率的变化。

100. 发明授权

US5666078A Programmable impedance output driver 失效
标题翻译：可编程阻抗输出驱动器
公开(公告)号：US5666078A
公开(公告)日：1997-09-09
申请号：US597655
申请日：1996-02-07
申请人： Steven H. Lamphier , Harold Pilo , Michael J. Schneiderwind , Fred J. Towler
发明人： Steven H. Lamphier , Harold Pilo , Michael J. Schneiderwind , Fred J. Towler
IPC分类号： H03K19/0185
CPC分类号： H03K19/018585
摘要： An output driver circuit is disclosed that generates an accurate and predictable output impedance driver value corresponding to a programmable external impedance. The output driver circuit includes an external resistance device, voltage comparator device, control logic, an evaluate circuit and off-chip driver (OCD) circuit. Voltage from the external resistance device (VZQ) is compared with voltage created from the evaluate circuit (VEVAL) by the voltage comparator device, which indicates to the control logic whether VEVAL is greater than or less than VZQ. The control logic will adjust the evaluate circuit accordingly with a count until the two voltages are basically equal (i.e., the count is alternating between two adjacent binary count values). At which time the control logic operates the OCD with the lower of the two adjacent count values to produce a proper and predictable driving impedance.
摘要翻译：公开了一种输出驱动器电路，其产生对应于可编程外部阻抗的精确和可预测的输出阻抗驱动器值。输出驱动电路包括外部电阻器件，电压比较器器件，控制逻辑器件，评估电路和片外驱动器（OCD）电路。将来自外部电阻装置（VZQ）的电压与电压比较器装置从评估电路（VEVAL）产生的电压进行比较，该控制逻辑指示VEVAL是否大于或小于VZQ。控制逻辑将根据计数相应地调整评估电路，直到两个电压基本相等（即计数在两个相邻的二进制计数值之间交替）。此时，控制逻辑以两个相邻计数值的较低者操作OCD以产生适当且可预测的驱动阻抗。

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