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91. 发明授权

US5909696A Method and apparatus for caching system management mode information with other information 失效
标题翻译：用其他信息缓存系统管理模式信息的方法和装置
公开(公告)号：US5909696A
公开(公告)日：1999-06-01
申请号：US656922
申请日：1996-06-04
申请人： Dennis Reinhardt , James P. Kardach , John W. Horigan , Neil Songer , Andrew F. Glew
发明人： Dennis Reinhardt , James P. Kardach , John W. Horigan , Neil Songer , Andrew F. Glew
IPC分类号： G06F9/48 , G06F12/02 , G06F12/06 , G06F12/08 , G06F12/14 , G06F13/14
CPC分类号： G06F12/1491 , G06F12/0802 , G06F12/0284 , G06F12/1441 , G06F12/1475
摘要： A novel method and apparatus to cache System Management Mode (SMM) data with other data to improve performance and reduce latency of SMM handler routines. This method and apparatus allows SMM data and non-SMM data to be distinguished in the cache without requiring extra cache bits which can add to the cost of implementation. Since SMM data and non-SMM data can coexist in the cache, there is no need for time consuming cache flush cycles when switching between the two modes. Since SMM data can be cached, performance of SMM routines are improved. This method and apparatus defines the SMRAM address range to be a range of addresses representable by the tag, but not directly corresponding to installed main memory. When accesses are made to SMRAM addresses, they are redirected to an unused portion of main memory. Protection mechanisms may be implemented to limit access to these SMRAM addresses when not in SMM.
摘要翻译：一种用于将系统管理模式（SMM）数据与其他数据进行缓存的新方法和装置，以提高性能并减少SMM处理程序的等待时间。该方法和装置允许在高速缓存中区分SMM数据和非SMM数据，而不需要增加执行成本的额外的缓存位。由于SMM数据和非SMM数据可以在高速缓存中共存，因此在两种模式之间切换时不需要耗时的高速缓存刷新周期。由于可以缓存SMM数据，因此提高了SMM例程的性能。该方法和装置将SMRAM地址范围定义为标签可表示的地址范围，但不直接对应于已安装的主存储器。当对SMRAM地址进行访问时，它们被重定向到主存储器的未使用部分。当不在SMM中时，可以实施保护机制来限制对这些SMRAM地址的访问。

92. 发明授权

US5881262A Method and apparatus for blocking execution of and storing load operations during their execution 失效
标题翻译：用于在其执行期间阻止执行和存储加载操作的方法和装置
公开(公告)号：US5881262A
公开(公告)日：1999-03-09
申请号：US928924
申请日：1997-09-12
申请人： Jeffery M. Abramson , Haitham Akkary , Andrew F. Glew , Glenn J. Hinton , Kris G. Konigsfeld , Paul D. Madland
发明人： Jeffery M. Abramson , Haitham Akkary , Andrew F. Glew , Glenn J. Hinton , Kris G. Konigsfeld , Paul D. Madland
IPC分类号： G06F9/312 , G06F9/38 , G06F13/00
CPC分类号： G06F9/3017 , G06F9/30043 , G06F9/3816 , G06F9/3824 , G06F9/3834 , G06F9/3836 , G06F9/3842
摘要： A method and apparatus for performing load operations in a computer system. The present invention includes a method and apparatus for dispatching the load operation to be executed. The present invention halts the execution of the load operation when a dependency exists between the load operation and another memory operation currently pending in the system. When the dependency no longer exists, the present invention redispatches the load operation so that it completes.
摘要翻译：一种用于在计算机系统中执行加载操作的方法和装置。本发明包括一种用于调度要执行的加载操作的方法和装置。本发明在加载操作和系统中当前待处理的另一个存储器操作之间存在依赖关系时，停止加载操作的执行。当依赖关系不再存在时，本发明重新分派加载操作使其完成。

93. 发明授权

US5809271A Method and apparatus for changing flow of control in a processor 失效
标题翻译：改变处理器中控制流程的方法和装置
公开(公告)号：US5809271A
公开(公告)日：1998-09-15
申请号：US518563
申请日：1995-08-23
申请人： Robert P. Colwell , Atiq Bajwa , Michael A. Fetterman , Andrew F. Glew , Glenn J. Hinton , David B. Papworth
发明人： Robert P. Colwell , Atiq Bajwa , Michael A. Fetterman , Andrew F. Glew , Glenn J. Hinton , David B. Papworth
IPC分类号： G06F9/32 , G06F9/38 , G06F9/26
CPC分类号： G06F9/3865 , G06F9/322 , G06F9/3844
摘要： A simplified method and apparatus for handling the change of instruction control flow in a microprocessor is provided. Rather than attempting to implement a change in the instruction flow immediately, the processor first recognizes that flow is to be redirected from a predicted instruction flow to a correct instruction flow according to a flow control indicator. The flow control indicator may be attached to instructions flowing down the pipeline or inserted as a separate instruction in the pipeline. The pipeline is cleared of state created by instructions that do not follow the correct instruction flow, i.e., instructions that were erroneously fetched after the instruction causing the change in flow. The change in flow as indicated by the flow control indicator is implemented later in the pipeline.
摘要翻译：提供了一种用于处理微处理器中指令控制流程变化的简化方法和装置。处理器不是试图立即实现指令流程的改变，而是根据流量控制指示符首先识别流程将从预测指令流重定向到正确的指令流。流量控制指示器可以附接到沿着流水线向下流动的指令或作为管道中的单独指令插入。管道被清除由不遵循正确指令流程的指令创建的状态，即在引起流量变化的指令之后被错误地取出的指令。流量控制指示器所示的流量变化在后面的流水线中实现。

94. 发明授权

US5796637A Apparatus and method for filtering event signals 失效
标题翻译：用于过滤事件信号的装置和方法
公开(公告)号：US5796637A
公开(公告)日：1998-08-18
申请号：US708929
申请日：1996-09-06
申请人： Andrew F. Glew , Sumeet Agrawal , Kamla P. Huck , Patrick G. Franklin
发明人： Andrew F. Glew , Sumeet Agrawal , Kamla P. Huck , Patrick G. Franklin
IPC分类号： G06F11/34 , G06F17/00
CPC分类号： G06F11/348
摘要： A system for filtering multiple event signals from multiple event-generating sources. A selection circuit receives the multiple event signals and selects one of the event signals. A filter circuit is coupled to the selection circuit and receives the selected event signal from the selection circuit. The filter circuit produces a filtered event signal. A counter receives the filtered event signal from the filter circuit and is incremented in response to the filtered event signal. The filter circuit includes a comparison logic circuit and an edge detection logic circuit.
摘要翻译：用于从多个事件生成源过滤多个事件信号的系统。选择电路接收多个事件信号并选择一个事件信号。滤波器电路耦合到选择电路并从选择电路接收所选择的事件信号。滤波器电路产生滤波的事件信号。计数器从滤波器电路接收滤波后的事件信号，并根据滤波后的事件信号递增。滤波电路包括比较逻辑电路和边缘检测逻辑电路。

95. 发明授权

US5778407A Methods and apparatus for determining operating characteristics of a memory element based on its physical location 失效
标题翻译：基于其物理位置来确定存储元件的操作特性的方法和装置
公开(公告)号：US5778407A
公开(公告)日：1998-07-07
申请号：US667241
申请日：1996-06-21
申请人： Andrew F. Glew , Glenn J. Hinton , David B. Papworth , Michael Alan Fetterman , Robert P. Colwell , Frederick Jay Pollack
发明人： Andrew F. Glew , Glenn J. Hinton , David B. Papworth , Michael Alan Fetterman , Robert P. Colwell , Frederick Jay Pollack
IPC分类号： G06F12/08 , G06F12/10 , G06F12/06
CPC分类号： G06F12/0888 , G06F12/1027 , G06F2212/206
摘要： A circuit comprising a number of range registers and complimentary decoding/matching circuits is provided to a processor for determining the memory type of a physical address, thereby allowing memory operating characteristics to be determined as soon as the physical address is available in an execution stage preceding cache access. Additionally, a memory type field is provided to each address translation lookaside buffer entry of the data and instruction memory subsystem for storing the determined memory type, and the memory type determination circuit is disposed in the page miss handler, thereby allowing memory type to be determined at the same time when the physical address is determined.
摘要翻译：包括多个范围寄存器和互补解码/匹配电路的电路被提供给处理器，用于确定物理地址的存储器类型，由此一旦物理地址在前面的执行阶段可用就允许确定存储器操作特性缓存访问。此外，存储器类型字段被提供给用于存储确定的存储器类型的数据和指令存储器子系统的每个地址转换后备缓冲器条目，并且存储器类型确定电路被布置在页面未命中处理器中，从而允许确定存储器类型同时确定物理地址。

96. 发明授权

US5778245A Method and apparatus for dynamic allocation of multiple buffers in a processor 失效
标题翻译：用于在处理器中动态分配多个缓冲器的方法和装置
公开(公告)号：US5778245A
公开(公告)日：1998-07-07
申请号：US204861
申请日：1994-03-01
申请人： David B. Papworth , Andrew F. Glew , Glenn J. Hinton , Robert P. Colwell , Michael A. Fetterman , Shantanu R. Gupta , James S. Griffith
发明人： David B. Papworth , Andrew F. Glew , Glenn J. Hinton , Robert P. Colwell , Michael A. Fetterman , Shantanu R. Gupta , James S. Griffith
IPC分类号： G06F9/38 , G06F9/50 , G06F15/82
CPC分类号： G06F9/5016 , G06F9/3836 , G06F9/384 , G06F9/3855 , G06F9/3857 , G06F9/3885
摘要： A method and apparatus for dynamically allocating entries of microprocessor resources to particular instructions in an efficient manner to efficiently utilize buffer size and resources. The pipelined and superscalar microprocessor is capable of speculatively executing instructions and also out-of-order processing. Resources within the microprocessor include a store buffer, a load buffer, a reorder buffer and a reservation station. The reorder buffer contains a larger set of physical registers and also contains information related to speculative instructions and the reservation station comprises information related to instructions pending execution. The load buffer is only allocated to load instructions and is valid for an instruction from allocation pipestage to instruction retirement. The store buffer is only allocated to store instructions and is valid for an instruction from allocation to store performance. The reservation station is allocated to most instructions and is valid for an instruction from allocation to instruction dispatch. The reorder buffer is allocated to all instructions and is valid for a given instruction from allocation to retirement. The load buffer, store buffer, and reorder buffer are sequentially allocated while the reservation station is not. Resource allocation is performed dynamically (as needed by the operation) rather than as a full set of resources attached to each operation. Using the above allocation scheme, efficient usage of the microprocessor resources is accomplished.
摘要翻译：一种用于以有效方式动态地将微处理器资源的条目分配给特定指令以有效利用缓冲器大小和资源的方法和装置。流水线和超标量微处理器能够推测性地执行指令并进行无序处理。微处理器内的资源包括存储缓冲器，加载缓冲器，重新排序缓冲器和保留站。重排序缓冲器包含较大的一组物理寄存器，并且还包含与推测指令相关的信息，并且保留站包括与待执行的指令相关的信息。加载缓冲区仅分配给加载指令，对从分配管理到指令退出的指令有效。存储缓冲区仅被分配用于存储指令，并且对于分配的指令有效以存储性能。保留站被分配给大多数指令，并且对于从分配到指令分派的指令是有效的。重新排序缓冲区被分配给所有指令，并且对于从分配到退休的给定指令是有效的。在保留站不存在的情况下顺序地分配负载缓冲器，存储缓冲器和重排序缓冲器。动态执行资源分配（根据操作需要），而不是作为每个操作附加的一整套资源。使用上述分配方案，可以实现微处理器资源的高效利用。

97. 发明授权

US5751996A Method and apparatus for processing memory-type information within a microprocessor 失效
标题翻译：用于处理微处理器内的存储器类型信息的方法和装置
公开(公告)号：US5751996A
公开(公告)日：1998-05-12
申请号：US767799
申请日：1996-12-17
申请人： Andrew F. Glew , Glenn J. Hinton
发明人： Andrew F. Glew , Glenn J. Hinton
IPC分类号： G06F9/312 , G06F9/38 , G06F12/08
CPC分类号： G06F9/30043 , G06F12/0804 , G06F12/0888 , G06F9/3824 , G06F9/3842 , G06F9/3857
摘要： A memory-type value identifying the type of memory contained with a range of memory locations is explicitly stored within a microprocessor. Prior to processing a memory micro-instruction such as a load or store, the memory-type is determined for the memory location identified by the memory micro-instruction. Once the memory-type is known the memory micro-instruction is processed in accordance with any one of a number of processing protocols including write-through processing, write-back processing, write-protect processing, restricted-cacheability processing, uncacheable speculatable write-combining processing, or uncacheable processing. By providing memory-type information explicitly within the microprocessor, the type of memory identified by a micro-instruction is known before the micro-instruction is processed. Accordingly, the protocol by which the micro-instruction is processed may be efficiently tailored to the memory-type. For example, if the memory location identified by the micro-instruction is known to be uncacheable, a data cache unit is bypassed and external memory is accessed directly. In an exemplary embodiment, the microprocessor is an out-of-order microprocessor capable of generating speculative memory micro-instruction. Also, the microprocessor may be only one of a number of microprocessors within a multiprocessor system.
摘要翻译：识别包含有存储器位置范围的存储器类型的存储器类型值被明确地存储在微处理器内。在处理诸如加载或存储之类的存储器微指令之前，为由存储器微指令识别的存储器位置确定存储器类型。一旦已知存储器类型，存储器微指令根据多种处理协议中的任何一种被处理，包括直写处理，回写处理，写保护处理，限制高速缓存处理，不可缓存的可写入写入 - 组合处理或不可缓解的处理。通过在微处理器内显式提供存储器类型信息，在微指令被处理之前，已经知道由微指令识别的存储器类型。因此，处理微指令的协议可以有效地针对存储器类型进行定制。例如，如果由微指令识别的存储器位置已知是不可缓存的，则旁路数据高速缓存单元，并直接访问外部存储器。在示例性实施例中，微处理器是能够产生推测存储器微指令的无序微处理器。此外，微处理器可能只是多处理器系统内的多个微处理器之一。

98. 发明授权

US5740393A Instruction pointer limits in processor that performs speculative out-of-order instruction execution 失效
标题翻译：处理器中的指令指针限制，执行推测性无序指令执行
公开(公告)号：US5740393A
公开(公告)日：1998-04-14
申请号：US723286
申请日：1996-09-30
申请人： Rohit A. Vidwans , Darrell D. Boggs , Michael A. Fetterman , Andrew F. Glew
发明人： Rohit A. Vidwans , Darrell D. Boggs , Michael A. Fetterman , Andrew F. Glew
IPC分类号： G06F9/38 , G06F9/30
CPC分类号： G06F9/3842 , G06F9/3836 , G06F9/384 , G06F9/3855 , G06F9/3857 , G06F9/3863
摘要： A method for enforcing an instruction pointer limit in a processor, wherein a retire circuit determines a speculative instruction pointer for a set of retiring instruction during a retirement operation. The retire circuit also determines whether each speculative instruction pointer exceeds the instruction pointer limit. The retire circuit commits the result data value of each instruction to the architectural state if the speculative instruction pointer for the result data value does not exceed the instruction pointer limit.
摘要翻译：一种用于在处理器中执行指令指针限制的方法，其中退出电路在退休操作期间确定一组退休指令的推测指令指针。退出电路还确定每个推测指令指针是否超过指令指针限制。如果结果数据值的推测指令指针不超过指令指针限制，则退出电路将每条指令的结果数据值提交到架构状态。

99. 发明授权

US5727176A Data processor with circuitry for handling pointers associated with a register exchange operation 失效
标题翻译：具有用于处理与寄存器交换操作相关联的指针的电路的数据处理器
公开(公告)号：US5727176A
公开(公告)日：1998-03-10
申请号：US611950
申请日：1996-03-06
申请人： David W. Clift , James M. Arnold , Robert P. Colwell , Andrew F. Glew
发明人： David W. Clift , James M. Arnold , Robert P. Colwell , Andrew F. Glew
IPC分类号： G06F9/315 , G06F9/38 , G06F12/02
CPC分类号： G06F9/30032 , G06F9/3836 , G06F9/384 , G06F9/3855 , G06F9/3857 , Y10S707/99936
摘要： A data processor includes a plurality of physical registers and a decoder that decodes a stream of instructions into micro-operations which include speculative operations specifying associated logical registers. The data processor further includes a register-alias table having a plurality of addressable entries corresponding to logical registers, specified by the speculative operations. Each entry of the register-alias table contains a register pointer to a corresponding physical register. The processor further includes a retirement register file that maintains register values of non-speculative operations, and a retirement array that maintains a retirement ordering for the retirement register file. Both the register-alias table and retirement array are updated by circuitry that is responsive to a register exchange operation; the circuitry swapping register pointers associated with first and second entries, respectively.
摘要翻译：数据处理器包括多个物理寄存器和将指令流解码为微操作的解码器，其包括指定关联的逻辑寄存器的推测性操作。数据处理器还包括一个寄存器别名表，其具有与由推测操作指定的逻辑寄存器对应的多个可寻址条目。寄存器别名表的每个条目包含一个到相应物理寄存器的寄存器指针。处理器还包括维护非投机操作的注册值的退休登记文件，以及维持退休登记文件的退休顺序的退休数组。寄存器别名表和退出数组都由响应于寄存器交换操作的电路来更新; 电路交换与第一和第二条目相关联的寄存器指针。

100. 发明授权

US5671444A Methods and apparatus for caching data in a non-blocking manner using a plurality of fill buffers 失效
标题翻译：使用多个填充缓冲器以非阻塞方式高速缓存数据的方法和装置
公开(公告)号：US5671444A
公开(公告)日：1997-09-23
申请号：US731545
申请日：1996-10-15
申请人： Haitham Akkary , Jeffrey M. Abramson , Andrew F. Glew , Glenn J. Hinton , Kris G. Konigsfeld , Paul D. Madland , Mandar S. Joshi , Brent E. Lince
发明人： Haitham Akkary , Jeffrey M. Abramson , Andrew F. Glew , Glenn J. Hinton , Kris G. Konigsfeld , Paul D. Madland , Mandar S. Joshi , Brent E. Lince
IPC分类号： G06F12/08 , G06F13/00
CPC分类号： G06F12/0859 , G06F12/0831
摘要： A data cache and a plurality of companion fill buffers having corresponding tag matching circuitry are provided to a computer system. Each fill buffer independently stores and tracks a replacement cache line being filled with data returning from main memory in response to a cache miss. When the cache fill is completed, the replacement cache line is output for the cache tag and data arrays of the data cache if the memory locations are cacheable and the cache line has not been snoop hit while the cache fill was in progress. Additionally, the fill buffers are organized and provided with sufficient address and data ports as well as selectors to allow the fill buffers to respond to subsequent processor loads and stores, and external snoops that hit their cache lines while the cache fills are in progress. As a result, the cache tag and data arrays of the data cache can continue to serve subsequent processor loads and stores, and external snoops, while one or more cache fills are in progress, without ever having to stall the processor.
摘要翻译：具有对应的标签匹配电路的数据高速缓存和多个伴随填充缓冲器被提供给计算机系统。每个填充缓冲器独立地存储和跟踪填充有响应于高速缓存未命中从主存储器返回的数据的替换高速缓存行。当缓存填充完成时，如果内存位置是可高速缓存的，并且缓存填充正在进行时，缓存线尚未被窥探，则会为高速缓存标签和数据高速缓存的数据阵列输出替换高速缓存行。此外，填充缓冲区被组织并提供有足够的地址和数据端口以及选择器，以允许填充缓冲区响应后续处理器负载和存储，以及在高速缓存填充正在进行时触发其缓存行的外部监听。因此，数据高速缓存的高速缓存标签和数据阵列可以在一个或多个缓存填充正在进行的同时继续提供后续的处理器加载和存储以及外部监听，而无需停止处理器。

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