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1. 发明授权

US5463745A Methods and apparatus for determining the next instruction pointer in an out-of-order execution computer system 失效
标题翻译：用于确定无序执行计算机系统中的下一个指令指针的方法和装置
公开(公告)号：US5463745A
公开(公告)日：1995-10-31
申请号：US174074
申请日：1993-12-22
申请人： Rohit A. Vidwans , Darrell D. Boggs , Michael A. Fetterman , Andrew F. Glew
发明人： Rohit A. Vidwans , Darrell D. Boggs , Michael A. Fetterman , Andrew F. Glew
IPC分类号： G06F9/38
CPC分类号： G06F9/3885 , G06F9/3836 , G06F9/384 , G06F9/3855 , G06F9/3857
摘要： Instructions are fetched and issued by an instruction fetch and issue circuit with the instructions' sizes in program order. An allocate circuit allocates reservation station entries in a reservation station circuit, and reorder buffer entries in a reorder circuit, for the issued instructions in order, storing the instructions' sizes in the allocated reorder buffer entries. The reservation and dispatch circuit dispatches the issued instructions to the execution circuits for execution when they are ready. The execution circuits store the result data including target addresses of branch instructions into the corresponding reorder buffer entries. During each retirement operation, a retire circuit reads the instruction sizes and the target addresses for a predetermined number of issued instructions from their allocated reorder buffer entries. The retire circuit determines two or more speculative next instruction pointers for each of the issued instructions, factoring into consideration whether the issued instructions are branch instructions or not, and their relative positions to each other. Each of the speculative next instruction pointers indicates what the next instruction pointer for the processor should be for retiring a particular combination of the result data values of the issued instructions under consideration. The retire circuit conditionally updates the next instruction pointer with one of the speculative next instruction pointers, depending on how many, if any, of the instructions can actually retire, and whether any of the actually retiring instructions are branch instructions.
摘要翻译：指令由指令提取和发布电路以指令的大小以程序顺序取出并发出。分配电路在保留站电路中分配保留站条目，并且重新排序重新排序电路中的缓冲区条目，以便按顺序发布指令，将指令的大小存储在所分配的重排序缓冲器条目中。预约和调度电路在准备就绪时将发出的指令发送到执行电路执行。执行电路将包括分支指令的目标地址的结果数据存储到相应的重排序缓冲器条目中。在每个退休操作期间，退出电路从其分配的重排序缓冲器条目读取预定数量的已发布指令的指令大小和目标地址。退出电路为每个发出的指令确定两个或更多个推测下一个指令指针，考虑所发出的指令是否是分支指令，以及它们彼此的相对位置。每个推测下一个指令指针指示处理器的下一个指令指针应该用于退出所考虑的已发出指令的结果数据值的特定组合。退出电路有条件地使用推测下一个指令指针之一更新下一个指令指针，这取决于指令实际可以退出多少（如果有的话），以及是否有任何实际退出的指令是分支指令。

2. 发明授权

US5740393A Instruction pointer limits in processor that performs speculative out-of-order instruction execution 失效
标题翻译：处理器中的指令指针限制，执行推测性无序指令执行
公开(公告)号：US5740393A
公开(公告)日：1998-04-14
申请号：US723286
申请日：1996-09-30
申请人： Rohit A. Vidwans , Darrell D. Boggs , Michael A. Fetterman , Andrew F. Glew
发明人： Rohit A. Vidwans , Darrell D. Boggs , Michael A. Fetterman , Andrew F. Glew
IPC分类号： G06F9/38 , G06F9/30
CPC分类号： G06F9/3842 , G06F9/3836 , G06F9/384 , G06F9/3855 , G06F9/3857 , G06F9/3863
摘要： A method for enforcing an instruction pointer limit in a processor, wherein a retire circuit determines a speculative instruction pointer for a set of retiring instruction during a retirement operation. The retire circuit also determines whether each speculative instruction pointer exceeds the instruction pointer limit. The retire circuit commits the result data value of each instruction to the architectural state if the speculative instruction pointer for the result data value does not exceed the instruction pointer limit.
摘要翻译：一种用于在处理器中执行指令指针限制的方法，其中退出电路在退休操作期间确定一组退休指令的推测指令指针。退出电路还确定每个推测指令指针是否超过指令指针限制。如果结果数据值的推测指令指针不超过指令指针限制，则退出电路将每条指令的结果数据值提交到架构状态。

3. 发明授权

US5687338A Method and apparatus for maintaining a macro instruction for refetching in a pipelined processor 失效
标题翻译：用于维持用于在流水线处理器中进行重写的宏指令的方法和装置
公开(公告)号：US5687338A
公开(公告)日：1997-11-11
申请号：US511296
申请日：1995-08-04
申请人： Darrell D. Boggs , Robert P. Colwell , Michael A. Fetterman , Andrew F. Glew , Ashwani K. Gupta , Glenn J. Hinton , David B. Papworth
发明人： Darrell D. Boggs , Robert P. Colwell , Michael A. Fetterman , Andrew F. Glew , Ashwani K. Gupta , Glenn J. Hinton , David B. Papworth
IPC分类号： G06F9/38 , G06F12/08
CPC分类号： G06F9/3814 , G06F12/0897 , G06F9/3802 , G06F9/3808 , G06F9/3863
摘要： A method and apparatus for instruction refetch in a processor is provided. To ensure that a macro instruction is available for refetching after the processor has handled an event or determined a correct restart address after a branch misprediction, an instruction memory includes an instruction cache for caching macro instructions to be fetched, and a victim cache for caching victims from the instruction cache. To ensure the availability of a macro instruction for refetching, the instruction memory (the instruction cache and victim cache together) always stores a macro instruction that may need to be refetched until the macro instruction is committed to architectural state. A marker micro instruction is inserted into the processor pipeline when an instruction cache line is victimized. The marker specifies an entry in the victim cache occupied by the victimized cache line. When the marker instruction is committed to architectural state, the victim cache entry specified by the marker is deallocated in the victim cache to permit storage of other instruction cache victims.
摘要翻译：提供了一种用于处理器中的指令重写的方法和装置。为了确保宏指令在处理器处理事件之后可用于重新获取指令，或者在分支错误预测之后确定正确的重新启动地址，指令存储器包括用于缓存要获取的宏指令的指令高速缓存，以及用于缓存受害者的受害缓存从指令缓存。为了确保可用的宏指令进行重写，指令存储器（指令高速缓存和受害器缓存在一起）总是存储可能需要重新引导的宏指令，直到宏指令提交到架构状态。当指令高速缓存线受害时，标记微指令被插入到处理器流水线中。标记指定受害缓存行占用的受害缓存中的条目。当标记指令被提交到架构状态时，标记指定的受害者缓存条目被释放在受害缓存中，以允许存储其他指令缓存受害者。

4. 发明授权

US5913050A Method and apparatus for providing address-size backward compatibility in a processor using segmented memory 失效
标题翻译：在使用分段存储器的处理器中提供地址大小向后兼容性的方法和装置
公开(公告)号：US5913050A
公开(公告)日：1999-06-15
申请号：US735048
申请日：1996-10-22
申请人： Darrell D. Boggs , Robert P. Colwell , Michael A. Fetterman , Andrew F. Glew , Glenn J. Hinton , David B. Papworth
发明人： Darrell D. Boggs , Robert P. Colwell , Michael A. Fetterman , Andrew F. Glew , Glenn J. Hinton , David B. Papworth
IPC分类号： G06F9/32 , G06F9/38 , G06F12/06 , G06F9/26
CPC分类号： G06F9/3804 , G06F9/30054
摘要： This invention overcomes the address size backward compatibility problem by first subtracting the segment base address from the linear destination address of a branch instruction to generate a virtual destination address. It is assumed that the branch instruction destination address is n bits long with m most significant bits. It is desired to provide backward compatibility in the n-bit processor for branch instruction code written for processors utilizing instruction address fields of size (n-m) bits. After obtaining the virtual address, if any of the m most significant bits are non-zero, then those m bits are set to zero to thereby generate a corrected virtual address. If such a compatibility correction is necessary, then a clear signal is asserted to flush all state of the processor that resulted from instructions being fetched after the branch instruction was fetched. The corrected virtual address is added back to the segment base address to generate a corrected linear address. The next instruction is fetched at the corrected linear address.
摘要翻译：本发明通过首先从分支指令的线性目的地地址中减去分段基地址来生成虚拟目的地地址来克服地址大小向后兼容性问题。假设分支指令目标地址是n位长，m个最高有效位。期望在n比特处理器中为使用大小（n-m）比特的指令地址字段为处理器编写的分支指令代码提供向后兼容性。在获得虚拟地址之后，如果m个最高有效位中的任何一个非零，则将这些m位设置为零，从而生成校正的虚拟地址。如果需要这种兼容性校正，则清除信号被断言以清除在分支指令被取出之后被取出的指令导致的处理器的所有状态。校正的虚拟地址被加回到段基地址以产生校正的线性地址。下一条指令是在校正的线性地址处获取的。

5. 发明授权

US5974523A Mechanism for efficiently overlapping multiple operand types in a microprocessor 失效
标题翻译：在微处理器中有效重叠多个操作数类型的机制
公开(公告)号：US5974523A
公开(公告)日：1999-10-26
申请号：US709216
申请日：1996-09-06
申请人： Andrew F. Glew , Darrell D. Boggs , Michael A. Fetterman , Glenn J. Hinton , Robert P. Colwell , David B. Papworth
发明人： Andrew F. Glew , Darrell D. Boggs , Michael A. Fetterman , Glenn J. Hinton , Robert P. Colwell , David B. Papworth
IPC分类号： G06F9/30 , G06F9/38
CPC分类号： G06F9/384 , G06F9/30145 , G06F9/30167 , G06F9/3824 , G06F9/3836 , G06F9/3857 , G06F9/3875 , G06F9/3885 , G06F9/3889 , G06F9/3891
摘要： A mechanism for efficiently overlapping multiple operand types is used in a microprocessor which includes a plurality of execution units and a mechanism to provide operations, which include one or more operands, to the plurality of execution units. Each of the plurality of execution units interprets the one or more operands as different types of operands, and the mechanism to provide operations overlaps the different types of operands.
摘要翻译：一种用于有效地重叠多个操作数类型的机制被用于包括多个执行单元的微处理器和一个向多个执行单元提供包括一个或多个操作数的操作的机制。多个执行单元中的每一个将一个或多个操作数解释为不同类型的操作数，并且提供操作的机制与不同类型的操作数重叠。

6. 发明授权

US07200737B1 Processor with a replay system that includes a replay queue for improved throughput 失效
标题翻译：具有重播系统的处理器，包括重播队列，以提高吞吐量
公开(公告)号：US07200737B1
公开(公告)日：2007-04-03
申请号：US09474096
申请日：1999-12-29
申请人： Amit A. Merchant , Darrell D. Boggs , David J. Sager
发明人： Amit A. Merchant , Darrell D. Boggs , David J. Sager
IPC分类号： G06F9/00
CPC分类号： G06F9/383 , G06F9/3838 , G06F9/3842 , G06F9/3851 , G06F9/3863 , G06F9/3869
摘要： A processor is provided that includes an execution unit for executing instructions and a replay system for replaying instructions which have not executed properly. The replay system is coupled to the execution unit and includes a checker for determining whether each instruction has executed properly and a replay queue coupled to the checker for temporarily storing one or more instructions for replay. The replay queue may be used to store a long latency instruction, such as a load in which data must be retrieved from an external memory device. The long latency instruction and possibly one or more dependent instruction are stored in the replay queue until the long latency instruction is ready to be executed (e.g., data for the load instruction has been retrieved from external memory). Once the long latency instruction is ready to be executed, (e.g., the data is available), the long latency instruction may then be unloaded from the replay queue for re-execution.
摘要翻译：提供了一种处理器，其包括用于执行指令的执行单元和用于重放未正确执行的指令的重放系统。重播系统耦合到执行单元，并且包括用于确定每个指令是否已正确执行的检查器和耦合到检查器的重放队列，用于临时存储用于重放的一个或多个指令。重放队列可以用于存储长延迟指令，例如必须从外部存储器件检索数据的负载。长延迟指令和可能的一个或多个相关指令被存储在重放队列中，直到长延迟指令准备好执行（例如，已从外部存储器检索到加载指令的数据）。一旦长延迟指令准备好执行（例如，数据可用），则可以从重放队列卸载长延迟指令以便重新执行。

7. 发明授权

US5559974A Decoder having independently loaded micro-alias and macro-alias registers accessible simultaneously by one micro-operation 失效
标题翻译：解码器具有独立加载的微别名和宏别名寄存器，可通过一个微操作同时访问
公开(公告)号：US5559974A
公开(公告)日：1996-09-24
申请号：US459284
申请日：1995-06-02
申请人： Darrell D. Boggs , Gary L. Brown , Michael M. Hancock , Donald D. Parker
发明人： Darrell D. Boggs , Gary L. Brown , Michael M. Hancock , Donald D. Parker
IPC分类号： G06F9/30 , G06F9/35 , G06F9/38 , G06F9/22
CPC分类号： G06F9/30167 , G06F9/30145 , G06F9/35 , G06F9/3863
摘要： A decoder that includes a micro-alias register to store information from a micro-operation for use by later micro-operations in the micro-operation flow. The decoder includes one or more XLAT PLAs that produces PLA control micro-operations ("Cuops"), a microcode sequencing unit that produces microcode Cuops, and an aliasing mechanism that extracts fields and stores them in macro-alias registers. A multiplexer is provided to select the appropriate Cuop to be stored in a Cuop register. Multiple Cuops may issue each cycle. A multiplexer is coupled to select one of the Cuops and to store predetermined fields in the micro-alias register for use by subsequent Cuops. Micro-alias data and macro-alias data can be utilized simultaneously with a Cuop to form an Auop.
摘要翻译：一种解码器，其包括微型别名寄存器，用于存储来自微操作的信息以供微操作流中的后续微操作使用。解码器包括产生PLA控制微操作（“Cuops”）的一个或多个XLAT PLA，产生微代码Cuops的微代码排序单元，以及提取字段并将其存储在宏别名寄存器中的混叠机制。提供多路复用器以选择要存储在Cuop寄存器中的适当Cuop。多个Cuops可以发出每个周期。多路复用器被耦合以选择Cuops中的一个并且将预定字段存储在微别名寄存器中以供随后的Cuops使用。 Micro-alias数据和宏别名数据可以与Cuop同时使用以形成Auop。

8. 发明授权

US07849465B2 Programmable event driven yield mechanism which may activate service threads 有权
标题翻译：可编程事件驱动的产生机制，可以激活服务线程
公开(公告)号：US07849465B2
公开(公告)日：2010-12-07
申请号：US11134687
申请日：2005-05-19
申请人： Xiang Zou , Hong Wang , Scott Dion Rodgers , Darrell D. Boggs , Bryant Bigbee , Shivanandan Kaushik , Anil Aggarwal , Ittai Anati , Doron Orenstein , Per Hammarlund , John Shen , Larry O. Smith , James B. Crossland , Chris J. Newburn
发明人： Xiang Zou , Hong Wang , Scott Dion Rodgers , Darrell D. Boggs , Bryant Bigbee , Shivanandan Kaushik , Anil Aggarwal , Ittai Anati , Doron Orenstein , Per Hammarlund , John Shen , Larry O. Smith , James B. Crossland , Chris J. Newburn
IPC分类号： G06F9/46 , G06F13/24 , G06F7/38
CPC分类号： G06F9/3851 , G06F9/30087 , G06F9/3009 , G06F9/4843 , G06F11/3409 , G06F11/348 , G06F2201/86 , G06F2201/88 , G06F2201/885
摘要： Method, apparatus, and system for a programmable event driven yield mechanism that may activate other threads. The yield mechanism may allow triggering of a service thread that may execute currently with a main thread upon occurrence of an architecturally-defined condition. The service thread may be activated, in response to the condition, with limited intervention of an operating system. In one embodiment, an apparatus includes execution resources to execute a plurality of instructions and a monitor to detect an architecturally-defined condition. The apparatus may include an event handler to handle a yield event generated when the architecturally-defined condition has been detected. An architectural mechanism, including processor instructions and channel registers, may be utilized to allow user-level code to enable the yield event mechanism. Other embodiments are also described and claimed.
摘要翻译：用于可激活其他线程的可编程事件驱动产量机制的方法，装置和系统。收益机制可以允许在出现体系结构定义的条件时触发可以执行当前与主线程的服务线程。响应于条件，可以在操作系统的有限干预下激活服务线程。在一个实施例中，装置包括执行多个指令的执行资源和监视器以检测体系结构定义的条件。该装置可以包括事件处理程序，用于处理当检测到体系结构定义的条件时产生的产出事件。可以使用包括处理器指令和通道寄存器在内的架构机制来允许用户级代码来实现产出事件机制。还描述和要求保护其他实施例。

9. 发明授权

US06467027B1 Method and system for an INUSE field resource management scheme 有权
标题翻译：用于INUSE现场资源管理方案的方法和系统
公开(公告)号：US06467027B1
公开(公告)日：2002-10-15
申请号：US09475746
申请日：1999-12-30
申请人： Alan B. Kyker , Darrell D. Boggs
发明人： Alan B. Kyker , Darrell D. Boggs
IPC分类号： G06F1200
CPC分类号： G06F9/3812 , G06F12/0875
摘要： A method for maintaining an instruction in a pipelined processor using inuse fields. The method involves receiving a read request for an instruction, sending the instruction in response to the read request and setting an inuse field associated with the instruction to inuse. Alternate embodiments of the method involve transmitting the instruction in response to the read request, receiving a notification of instruction retirement and resetting the inuse field in the ITLB. The method can also be used in the ICACHE in which inuse fields are associated with each instruction stored in the ICACHE. Other embodiments of the method can be used concurrently in the ITLB and the ICACHE as a resource tracking mechanism to maintain resources.
摘要翻译：一种用于使用使用字段来维护在流水线处理器中的指令的方法。该方法包括接收对指令的读取请求，响应于读取请求发送指令并设置与该指令相关联的使用字段以使用。该方法的替代实施例涉及响应于读请求发送指令，接收指令退出通知并重置ITLB中的使用字段。该方法也可以用在ICACHE中，其中使用字段与存储在ICACHE中的每个指令相关联。该方法的其他实施例可以在ITLB和ICACHE中同时使用作为资源跟踪机制来维护资源。

10. 发明授权

US07219349B2 Multi-threading techniques for a processor utilizing a replay queue 有权
标题翻译：使用重放队列的处理器的多线程技术
公开(公告)号：US07219349B2
公开(公告)日：2007-05-15
申请号：US10792154
申请日：2004-03-02
申请人： Amit A. Merchant , Darrell D. Boggs , David J. Sager
发明人： Amit A. Merchant , Darrell D. Boggs , David J. Sager
IPC分类号： G06F9/46 , G06F9/40 , G06F15/76
CPC分类号： G06F9/383 , G06F9/3838 , G06F9/3842 , G06F9/3851 , G06F9/3863 , G06F9/3869
摘要： A processor is provided that includes an execution unit for executing instructions and a replay system for replaying instructions which have not executed properly. The replay system is coupled to the execution unit and includes a checker for determining whether each instruction has executed properly and a plurality of replay queues or replay queue sections coupled to the checker for temporarily storing one or more instructions for replay. In one embodiment, thread-specific replay queue sections may each be used to store a long latency instruction for each thread until the long latency instruction is ready to be executed (e.g., data for a load instruction has been retrieved from external memory). By storing the long latency instruction and its dependents in a replay queue section for one thread which has stalled, execution resources are made available for improving the speed of execution of other threads which have not stalled.
摘要翻译：提供了一种处理器，其包括用于执行指令的执行单元和用于重放未正确执行的指令的重放系统。重播系统耦合到执行单元，并且包括用于确定每个指令是否已正确执行的检查器和耦合到检验器的多个重播队列或重放队列部分，用于临时存储用于重放的一个或多个指令。在一个实施例中，线程特定的重播队列部分可以各自用于存储每个线程的长等待时间指令，直到长等待时间指令准备执行（例如，已经从外部存储器检索到加载指令的数据）。通过将延迟时间长的指令及其依赖项存储在已停播的一个线程的重放队列部分中，执行资源可用于提高未停滞的其他线程的执行速度。

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