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91. 发明授权

US06399462B1 Method and structure for isolating integrated circuit components and/or semiconductor active devices 失效
标题翻译：用于隔离集成电路部件和/或半导体有源器件的方法和结构
公开(公告)号：US06399462B1
公开(公告)日：2002-06-04
申请号：US08885046
申请日：1997-06-30
申请人： Krishnaswamy Ramkumar , Sang S. Kim , Sharmin Sadoughi , Pamela Trammel , Avner Shelem
发明人： Krishnaswamy Ramkumar , Sang S. Kim , Sharmin Sadoughi , Pamela Trammel , Avner Shelem
IPC分类号： H01L2176
CPC分类号： H01L21/7621
摘要： A method of forming a field oxide or isolation region in a semiconductor die. A nitride layer (over an oxide layer disposed over a substrate) is patterned and subsequently etched so that the nitride layer has a nearly vertical sidewall. The oxide layer and the substrate in the isolation region are etched to form a recess in the substrate having a sloped surface with respect to the nearly vertical sidewall of the nitride layer. A field oxide is then grown in the recess using a high pressure, dry oxidizing atmosphere. The sloped sidewall of the substrate effectively moves the face of the exposed substrate away from the edge of the nitride layer sidewall. Compared to non-sloped techniques, the oxidation appears to start with a built-in offset from the patterned etch. This leads to a reduction of oxide encroachment and a nearly non-existent bird's beak. The desirable range of slopes for the substrate sidewall is approximately 50°-80° with respect to a nearly planar surface of the substrate in the recess.
摘要翻译：一种在半导体管芯中形成场氧化物或隔离区域的方法。对氮化物层（在衬底上方的氧化物层上方）进行构图并随后进行蚀刻，使得氮化物层具有几乎垂直的侧壁。蚀刻隔离区域中的氧化物层和衬底，以在衬底中形成相对于氮化物层的几乎垂直侧壁具有倾斜表面的凹部。然后使用高压，干燥的氧化气氛将场氧化物生长在凹陷中。衬底的倾斜侧壁有效地将暴露的衬底的表面远离氮化物层侧壁的边缘移动。与非倾斜技术相比，氧化似乎从图案化蚀刻的内置偏移开始。这导致氧化物侵蚀的减少和几乎不存在的鸟的喙。相对于凹部中的基板的几乎平坦的表面，衬底侧壁的期望的斜率范围大约为50°-80°。

92. 发明授权

US08691648B1 Methods for fabricating semiconductor memory with process induced strain 有权
标题翻译：用工艺诱导应变制造半导体存储器的方法
公开(公告)号：US08691648B1
公开(公告)日：2014-04-08
申请号：US13168711
申请日：2011-06-24
申请人： Igor Polishchuk , Sagy Levy , Krishnaswamy Ramkumar , Jeong Soo Byun
发明人： Igor Polishchuk , Sagy Levy , Krishnaswamy Ramkumar , Jeong Soo Byun
IPC分类号： H01L21/336
CPC分类号： H01L21/28282 , H01L29/66833 , H01L29/792
摘要： Non-volatile semiconductor memories and methods of fabricating the same to improve performance thereof are provided. In one embodiment, the method includes: (i) forming a gate for a non-volatile memory transistor on a surface of a substrate overlaying a channel region formed therein, the gate including a charge trapping layer; and (ii) forming a strain inducing structure over the gate of the non-volatile memory transistor to increase charge retention of the charge trapping layer. Preferably, the memory transistor is a silicon-oxide-nitride-oxide-silicon (SONOS) transistor comprising a SONOS gate stack. More preferably, the memory also includes a logic transistor on the substrate, and the step of forming a strain inducing structure comprises the step of forming the strain inducing structure over the logic transistor. Other embodiments are also disclosed.
摘要翻译：提供非易失性半导体存储器及其制造方法以改善其性能。在一个实施例中，该方法包括：（i）在覆盖其中形成的沟道区的衬底的表面上形成用于非易失性存储晶体管的栅极，栅极包括电荷俘获层; 和（ii）在非易失性存储晶体管的栅极上形成应变诱导结构，以增加电荷俘获层的电荷保留。优选地，存储晶体管是包括SONOS栅极堆叠的氧化硅 - 氧化物 - 氮化物 - 氧化物 - 硅（SONOS）晶体管。更优选地，存储器还包括在衬底上的逻辑晶体管，并且形成应变诱导结构的步骤包括在逻辑晶体管上形成应变诱导结构的步骤。还公开了其他实施例。

93. 发明授权

US08680601B2 Nonvolatile charge trap memory device having a deuterated layer in a multi-layer charge-trapping region 有权
标题翻译：在多层电荷捕获区域中具有氘化层的非挥发性电荷陷阱存储器件
公开(公告)号：US08680601B2
公开(公告)日：2014-03-25
申请号：US11904475
申请日：2007-09-26
申请人： Sagy Levy , Fredrick B. Jenne , Krishnaswamy Ramkumar
发明人： Sagy Levy , Fredrick B. Jenne , Krishnaswamy Ramkumar
IPC分类号： H01L27/115 , H01L29/792
CPC分类号： H01L29/792 , H01L21/28282 , H01L29/513 , H01L29/66833
摘要： A nonvolatile charge trap memory device is described. The device includes a substrate having a channel region and a pair of source/drain regions. A gate stack is above the substrate over the channel region and between the pair of source/drain regions. The gate stack includes a multi-layer charge-trapping region having a first deuterated layer. The multi-layer charge-trapping region may further include a deuterium-free charge-trapping layer.
摘要翻译：描述了非易失性电荷陷阱存储器件。该器件包括具有沟道区和一对源极/漏极区的衬底。栅极堆叠在沟道区域上方之间以及在一对源极/漏极区域之间的衬底之上。栅极堆叠包括具有第一氘化层的多层电荷捕获区域。多层电荷俘获区域还可以包括不含氘的电荷俘获层。

94. 发明授权

US08637921B2 Nitridation oxidation of tunneling layer for improved SONOS speed and retention 有权
标题翻译：隧道层的氮化氧化提高了SONOS的速度和保留时间
公开(公告)号：US08637921B2
公开(公告)日：2014-01-28
申请号：US12005813
申请日：2007-12-27
申请人： Sagy Levy , Krishnaswamy Ramkumar , Fredrick B. Jenne
发明人： Sagy Levy , Krishnaswamy Ramkumar , Fredrick B. Jenne
IPC分类号： H01L29/792
CPC分类号： H01L29/792 , H01L21/28282 , H01L21/3143 , H01L29/4234 , H01L29/4916 , H01L29/512 , H01L29/513 , H01L29/518
摘要： A method for forming a tunneling layer of a nonvolatile trapped-charge memory device and the article made thereby. The method includes multiple oxidation and nitridation operations to provide a dielectric constant higher than that of a pure silicon dioxide tunneling layer but with a fewer hydrogen and nitrogen traps than a tunneling layer having nitrogen at the substrate interface. The method provides for an improved memory window in a SONOS-type device. In one embodiment, the method includes an oxidation, a nitridation, a reoxidation and a renitridation. In one implementation, the first oxidation is performed with O2 and the reoxidation is performed with NO.
摘要翻译：一种用于形成非易失性俘获电荷存储装置的隧道层的方法及其制成的制品。该方法包括多次氧化和氮化操作，以提供比纯二氧化硅隧道层更高的介电常数，但是具有比在衬底界面处具有氮的隧穿层更少的氢和氮阱。该方法提供了SONOS型设备中改进的存储器窗口。在一个实施方案中，所述方法包括氧化，氮化，再氧化和再纳入。在一个实施方案中，首先用O 2进行氧化，并用NO进行再氧化。

95. 发明申请

US20130178031A1 INTEGRATION OF NON-VOLATILE CHARGE TRAP MEMORY DEVICES AND LOGIC CMOS DEVICES 有权
标题翻译：非挥发性电荷捕获存储器件和逻辑CMOS器件的集成
公开(公告)号：US20130178031A1
公开(公告)日：2013-07-11
申请号：US13436878
申请日：2012-03-31
申请人： Krishnaswamy Ramkumar , Fredrick Jenne , Sagy Levy
发明人： Krishnaswamy Ramkumar , Fredrick Jenne , Sagy Levy
IPC分类号： H01L21/336
CPC分类号： H01L29/7833 , B82Y10/00 , H01L21/28282 , H01L21/823412 , H01L21/823425 , H01L21/823462 , H01L27/105 , H01L27/1052 , H01L27/11568 , H01L27/11573 , H01L27/11582 , H01L29/665 , H01L29/6656 , H01L29/6659 , H01L29/66833 , H01L29/7836 , H01L29/7843 , H01L29/792 , H01L29/7926
摘要： An embodiment of a method of integrating a non-volatile memory device into a logic MOS flow is described. Generally, the method includes: forming in a first region of a substrate a channel of a memory device from a semiconducting material overlying a surface of the substrate, the channel connecting a source and a drain of the memory device; forming a charge trapping dielectric stack over the channel adjacent to a plurality of surfaces of the channel, wherein the charge trapping dielectric stack includes a blocking layer on a charge trapping layer over a tunneling layer; and forming a MOS device over a second region of the substrate.
摘要翻译：描述了将非易失性存储器件集成到逻辑MOS流中的方法的实施例。通常，该方法包括：在衬底的第一区域中形成存储器件的通道，覆盖衬底表面的半导体材料，连接存储器件的源极和漏极的沟道; 在与所述通道的多个表面相邻的所述通道上形成电荷捕获电介质堆叠，其中所述电荷捕获电介质堆叠包括在隧道层上的电荷捕获层上的阻挡层; 以及在所述衬底的第二区域上形成MOS器件。

96. 发明授权

US08318608B2 Method of fabricating a nonvolatile charge trap memory device 有权
标题翻译：制造非易失性电荷陷阱存储器件的方法
公开(公告)号：US08318608B2
公开(公告)日：2012-11-27
申请号：US12197466
申请日：2008-08-25
申请人： Krishnaswamy Ramkumar , Sagy Levy , Jeong Byun
发明人： Krishnaswamy Ramkumar , Sagy Levy , Jeong Byun
IPC分类号： H01L21/31
CPC分类号： H01L21/28282 , H01L21/3144 , H01L21/3145 , H01L29/4234 , H01L29/66833
摘要： A method for fabricating a nonvolatile charge trap memory device is described. The method includes providing a substrate having a charge-trapping layer disposed thereon. A portion of the charge-trapping layer is then oxidized to form a blocking dielectric layer above the charge-trapping layer by exposing the charge-trapping layer to a radical oxidation process.
摘要翻译：描述了制造非易失性电荷陷阱存储器件的方法。该方法包括提供其上设置有电荷捕获层的衬底。然后通过将电荷捕获层暴露于自由基氧化过程，电荷俘获层的一部分被氧化以形成电荷俘获层上方的阻挡电介质层。

97. 发明授权

US08283261B2 Radical oxidation process for fabricating a nonvolatile charge trap memory device 有权
标题翻译：用于制造非易失性电荷陷阱存储器件的自由基氧化工艺
公开(公告)号：US08283261B2
公开(公告)日：2012-10-09
申请号：US12124855
申请日：2008-05-21
申请人： Krishnaswamy Ramkumar
发明人： Krishnaswamy Ramkumar
IPC分类号： H01L21/31
CPC分类号： H01L21/28282 , H01L21/3144 , H01L21/3145 , H01L29/4234 , H01L29/66833
摘要： A method for fabricating a nonvolatile charge trap memory device is described. The method includes providing a substrate having a charge-trapping layer disposed Thereon. A portion of the charge-trapping layer is then oxidized to form a blocking dielectric layer above the charge-trapping layer by exposing the charge-trapping layer to a radical oxidation process.
摘要翻译：描述了制造非易失性电荷陷阱存储器件的方法。该方法包括提供其上设置有电荷捕获层的衬底。然后通过将电荷捕获层暴露于自由基氧化过程，电荷俘获层的一部分被氧化以形成电荷俘获层上方的阻挡电介质层。

98. 发明授权

US08222688B1 SONOS stack with split nitride memory layer 有权
标题翻译： SONOS堆叠带有划痕的氮化物存储层
公开(公告)号：US08222688B1
公开(公告)日：2012-07-17
申请号：US12767105
申请日：2010-04-26
申请人： Fredrick Jenne , Krishnaswamy Ramkumar
发明人： Fredrick Jenne , Krishnaswamy Ramkumar
IPC分类号： H01L29/792
CPC分类号： H01L21/28282 , G11C16/04 , H01L21/022 , H01L21/02323 , H01L27/11563 , H01L29/4234 , H01L29/513 , H01L29/792
摘要： A semiconductor device includes a substrate, a first oxide layer formed on the substrate, an oxygen-rich nitride layer formed on the first oxide layer, a second oxide layer formed on the oxygen-rich nitride layer, and an oxygen-poor nitride layer formed on the second oxide layer.
摘要翻译：半导体器件包括衬底，形成在衬底上的第一氧化物层，形成在第一氧化物层上的富氧氮化物层，形成在富氧氮化物层上的第二氧化物层和形成的不透氧氮化物层在第二氧化物层上。

99. 发明授权

US08119538B1 Oxide formation in a plasma process 有权
标题翻译：在等离子体工艺中形成氧化物
公开(公告)号：US08119538B1
公开(公告)日：2012-02-21
申请号：US11836683
申请日：2007-08-09
申请人： Jeong Soo Byun , Krishnaswamy Ramkumar
发明人： Jeong Soo Byun , Krishnaswamy Ramkumar
IPC分类号： H01L21/31
CPC分类号： H01L21/28282 , H01L21/02164 , H01L21/02238 , H01L21/02323 , H01L21/02326
摘要： A method of making a semiconductor structure is provided. The method includes forming a dielectric layer using a high density plasma oxidation process. The dielectric layer is on a storage layer and the thickness of the storage layer is reduced during the high density plasma oxidation process.
摘要翻译：提供制造半导体结构的方法。该方法包括使用高密度等离子体氧化工艺形成介电层。电介质层在存储层上，并且在高密度等离子体氧化过程中存储层的厚度减小。

100. 发明授权

US08071453B1 Method of ONO integration into MOS flow 有权
标题翻译： ONO集成到MOS流中的方法
公开(公告)号：US08071453B1
公开(公告)日：2011-12-06
申请号：US12608886
申请日：2009-10-29
申请人： Krishnaswamy Ramkumar , Bo Jin , Fredrick B. Jenne
发明人： Krishnaswamy Ramkumar , Bo Jin , Fredrick B. Jenne
IPC分类号： H01L21/336
CPC分类号： H01L21/768 , H01L27/11568 , H01L29/792
摘要： A method of ONO integration of a non-volatile memory device (e.g. EEPROM, floating gate FLASH and SONOS) into a baseline MOS device (e.g. MOSFET) is described. In an embodiment the bottom two ONO layers are formed prior to forming the channel implants into the MOS device, and the top ONO layer is formed simultaneously with the gate oxide of the MOS device.
摘要翻译：描述了将非易失性存储器件（例如EEPROM，浮动栅极FLASH和SONOS）的ONO集成到基准MOS器件（例如MOSFET）中的方法。在一个实施例中，在将沟道植入物形成MOS器件之前形成底部的两个ONO层，并且顶部ONO层与MOS器件的栅极氧化物同时形成。

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