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    • 92. 发明授权
    • Method of timing criticality calculation for statistical timing optimization of VLSI circuit
    • VLSI电路统计时序优化的定时临界计算方法
    • US08046724B2
    • 2011-10-25
    • US12474547
    • 2009-05-29
    • Hyoun Soo ParkYoung Hwan KimDai Joon HyunWook Kim
    • Hyoun Soo ParkYoung Hwan KimDai Joon HyunWook Kim
    • G06F9/455G06F17/50
    • G06F17/5031G06F17/505
    • Provided is a method of optimizing statistical timing of an integration circuit, the method including applying subtle changes of mean arrival times with respect to each of nodes in a timing graph of an integrated circuit to ADD operations and MAX operations of a block-based statistical static timing analysis (SSTA) method and approximating the corresponding operations; generating Jacobian matrixes between each node by using matrix components including differential coefficients calculated during linear approximation of the operations; calculating changed arrival time values of the circuit by propagating the Jacobian matrixes from a virtual sink node to a virtual source node; and calculating timing yield criticalities, which are variances of timing yield of the circuit due to subtle changes of mean arrival times with respect to each node, based on values obtained by the propagation. Accordingly, timing yield criticality is calculated based on linear approximation of ADD operations and MAX operations of statistical static timing analysis (SSTA), and thus the calculation complexity is linear with respect to the total number of nodes, and critical nodes significantly affecting the timing yield of a circuit can be extracted more accurately.
    • 提供了一种优化集成电路的统计定时的方法,该方法包括对集成电路的定时图中的每个节点应用平均到达时间的微妙变化,以ADD操作和基于块的统计静态的MAX操作 时序分析(SSTA)方法和近似相应的操作; 通过使用包括在操作的线性近似期间计算的微分系数的矩阵分量来生成每个节点之间的雅可比矩阵; 通过将雅可比矩阵从虚拟汇聚节点传播到虚拟源节点来计算电路的改变的到达时间值; 以及基于通过传播获得的值,计算由于平均到达时间相对于每个节点的微妙变化而导致的电路的定时收益率的定时收益率临界。 因此,基于统计静态时序分析(SSTA)的ADD操作和MAX操作的线性近似来计算定时收益关键性,因此计算复杂度相对于总节点数是线性的,关键节点显着影响定时收益 可以更准确地提取电路。
    • 95. 发明申请
    • METHOD OF INCREMENTAL STATISTICAL STATIC TIMING ANALYSIS BASED ON TIMING YIELD
    • 基于时序的增量统计静态时序分析方法
    • US20100306724A1
    • 2010-12-02
    • US12475545
    • 2009-05-31
    • Jinwook KimYoung Hwan KimWook Kim
    • Jinwook KimYoung Hwan KimWook Kim
    • G06F17/50
    • G06F17/5031G06F2217/84
    • Provided is a method of incremental SSTA (statistical static timing analysis) of a digital circuit, the method including a first step in which, when a gate is replaced in the digital circuit, delay propagation is performed from a node of a replaced gate to a virtual sink node based on SSTA; a second step in which, if a changed value of a gate timing yield at each gate which propagates delay toward the virtual sink node is smaller than a predetermined threshold value, delay propagation with respect to a fanout gate of the corresponding gate is stopped; and a third step in which, when a delay with respect to the node of the replaced gate is propagated to the virtual sink node, a new timing yield is calculated at the virtual sink node.
    • 提供了数字电路的增量SSTA(统计静态时序分析)的方法,该方法包括第一步骤,其中当在数字电路中替换门时,从更换的门的节点执行延迟传播 基于SSTA的虚拟汇聚节点; 第二步骤,如果在向虚拟汇聚节点传播延迟的每个门的门定时收益的改变值小于预定阈值,则停止相对于相应门的扇出门的延迟传播; 以及第三步骤,当相对于所替换的门的节点的延迟传播到虚拟宿节点时,在虚拟宿节点处计算新的定时收益。
    • 96. 发明授权
    • Signal generator, signal generation method, and RF communication system using the same
    • 信号发生器,信号发生方法和使用其的RF通信系统
    • US07830213B2
    • 2010-11-09
    • US11523534
    • 2006-09-20
    • Sang-Min HanSeong-soo LeeYoung-hwan KimAlexander S. Dmitriev
    • Sang-Min HanSeong-soo LeeYoung-hwan KimAlexander S. Dmitriev
    • H03B1/00H03B5/24H03B29/00H03C1/00H03K3/03H03K7/00H04L27/00
    • H03G3/3036H04B1/7174H04L27/001
    • A signal generator, a signal generation method, and a communication system using the same are provided. The signal generator includes a plurality of nonlinear elements which are connected in a ring; and a signal distributor which is arranged in the ring to form a closed loop, feeds part of a signal to one of the plurality of the nonlinear elements, and outputs signal generated by one of the plurality of nonlinear elements. The method includes arranging a plurality of nonlinear elements connected in a ring; inputting a signal to one of the nonlinear elements; amplifying the signal; receiving the amplified signal and generating a harmonic component of a frequency; clipping the signal; and feeding part of the signal back to one of the nonlinear elements and outputting a remainder of the signal. The system includes a chaotic signal generator; a signal distributor; a modulator; and a transmission circuit.
    • 提供信号发生器,信号生成方法和使用该信号发生方法的通信系统。 信号发生器包括以环形连接的多个非线性元件; 以及信号分配器,其布置在所述环中以形成闭环,将部分信号馈送到所述多个非线性元件中的一个,并输出由所述多个非线性元件之一产生的信号。 该方法包括布置连接在环中的多个非线性元件; 将信号输入到非线性元件之一; 放大信号; 接收放大的信号并产生频率的谐波分量; 剪辑信号; 并将信号的一部分馈送回非线性元件中的一个,并输出信号的剩余部分。 该系统包括混沌信号发生器; 信号分配器; 调制器 和发送电路。
    • 97. 发明授权
    • Signal transmitting method and apparatus using length division multiple access
    • 使用长度分割多路访问的信号发送方法和装置
    • US07773637B2
    • 2010-08-10
    • US11360524
    • 2006-02-24
    • Jae-hyon KimYoung-hwan KimSu Khiong YongSeong-soo Lee
    • Jae-hyon KimYoung-hwan KimSu Khiong YongSeong-soo Lee
    • H04J3/06
    • H04L27/001
    • A method and apparatus for simplifying a structure needed to delay data in delay units when a reference signal and data are transmitted by using chaotic signals are provided. The method includes delaying data by at least two delay times, wherein each of the delay times occurs sequentially; multiplexing the data, which has been delayed, according to a control signal; and transmitting the data and a reference signal which corresponds to the data at an interval of delay time. The apparatus includes a first delay unit which is configured to delay data for a first delay time; a second delay unit which is configured to delay the data output from the first delay unit for a second delay time; and a multiplexer which is configured to multiplex the data from the first and second delay units according to a control signal.
    • 提供一种用于简化当通过使用混沌信号发送参考信号和数据时以延迟单元延迟数据所需的结构的方法和装置。 该方法包括将数据延迟至少两个延迟时间,其中每个延迟时间顺序地发生; 根据控制信号对已被延迟的数据进行多路复用; 并以延迟时间的间隔发送对应于数据的数据和参考信号。 该装置包括:第一延迟单元,被配置为延迟第一延迟时间的数据; 第二延迟单元,其被配置为将来自所述第一延迟单元的数据延迟第二延迟时间; 以及多路复用器,被配置为根据控制信号来复用来自第一和第二延迟单元的数据。
    • 98. 发明申请
    • SINGLE SUPPLY PASS GATE LEVEL CONVERTER FOR MULTIPLE SUPPLY VOLTAGE SYSTEM
    • 单电源电压电平转换器多电源电压系统
    • US20100156371A1
    • 2010-06-24
    • US12639188
    • 2009-12-16
    • Jiyeon AnYoung Hwan KimHyoun Soo Park
    • Jiyeon AnYoung Hwan KimHyoun Soo Park
    • G05F1/10
    • H03K19/018571
    • The present invention relates to a level converter used in a multiple supply voltage system that is required to design a low-power and high-performance semiconductor, and more particularly, to a single supply pass gate level converter (SPLC) for a multiple supply voltage system, which has low power consumption, operates at high speed, and uses only a single supply voltage. The SPLC includes an input data providing circuit unit which receives an input signal of a low supply voltage; a data inversion circuit unit which receives input data from the input data providing circuit unit and outputs inversed input data; a feedback circuit unit which is fed back by an output of the data inversion circuit unit; and a data output buffer which inverses an output of the data inversion circuit unit and outputs an inversed signal. The input data providing circuit unit, the data inversion circuit unit, the feedback circuit unit, and the data output buffer are all driven by a high supply voltage such that only a single supply voltage which is the high supply voltage is required.
    • 本发明涉及一种用于设计低功率和高性能半导体所需的多电源电压系统中的电平转换器,更具体地说,涉及一种用于多电源电压的单电源通过门电平转换器(SPLC) 系统功耗低,运行速度快,仅使用单电源电压。 SPLC包括输入数据提供电路单元,其接收低电源电压的输入信号; 数据反转电路单元,其从输入数据提供电路单元接收输入数据并输出反相输入数据; 反馈电路单元,由数据反转电路单元的输出反馈; 以及数据输出缓冲器,其反转数据反转电路单元的输出并输出反相信号。 输入数据提供电路单元,数据反转电路单元,反馈电路单元和数据输出缓冲器均由高电源电压驱动,使得仅需要作为高电源电压的单个电源电压。
    • 99. 发明申请
    • Method of Estimating a Leakage Current in a Semiconductor Device
    • 估算半导体器件中泄漏电流的方法
    • US20100058258A1
    • 2010-03-04
    • US12547729
    • 2009-08-26
    • Kyung Tae DoJung-Yun ChoiBong-Hyun LeeYoung-Hwan KimHyo-Sig WonWook Kim
    • Kyung Tae DoJung-Yun ChoiBong-Hyun LeeYoung-Hwan KimHyo-Sig WonWook Kim
    • G06F17/50
    • G06F17/5036
    • In a method of estimating a leakage current in semiconductor device, a chip including a plurality of cells is divided into segments by a grid model. Spatial correlation is determined as spatial correlation between process parameters concerned with the leakage currents in each of the cells. A virtual cell leakage characteristic function of the cell is generated by arithmetically operating actual leakage characteristic functions. A segment leakage characteristic function is generated by arithmetically operating the virtual cell leakage characteristic functions of each cell in the segment. Then, a full chip leakage characteristic function is generated by statistically operating the segment leakage characteristic functions of each segment in the chip. Accordingly, the computational loads of Wilkinson's method for generating the full chip leakage characteristic function may be remarkably reduced.
    • 在估计半导体器件中的漏电流的方法中,包括多个单元的芯片通过栅格模型被划分为段。 空间相关性被确定为与每个单元中的泄漏电流有关的工艺参数之间的空间相关性。 通过算术运算实际漏电特性函数产生单元的虚拟单元泄漏特性函数。 通过对片段中每个单元的虚拟单元泄漏特性函数进行算术运算来产生段泄漏特性函数。 然后,通过统计操作芯片中每个段的段泄漏特性函数来产生全片泄漏特性函数。 因此,威尔金森的用于产生全芯片泄漏特性函数的方法的计算量可以显着降低。