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91. 发明申请

US20200153961A1 METHOD AND APPARATUS FOR DATA CHANNEL AUGMENTED VOICE TELEPHONY SYSTEMS 审中-公开
公开(公告)号：US20200153961A1
公开(公告)日：2020-05-14
申请号：US16740377
申请日：2020-01-10
申请人： Millind Mittal
发明人： Millind Mittal
IPC分类号： H04M3/493 , H04M15/06
摘要： A computerized method of terminating audio telephone calls that provides the other party with more information as to why the telephone call was terminated. This method, which is particularly useful for computerized smartphones equipped with voice and data channel communications methods, automatically provides the user with a variety of different informative text messages that can be selected by the user and sent to the other party at the time that a voice call is terminated.

92. 发明申请

US20190139035A1 SYSTEM AND METHOD OF ELECTRONIC PAYMENT USING PAYEE PROVIDED TRANSACTION IDENTIFICATION CODES 审中-公开
公开(公告)号：US20190139035A1
公开(公告)日：2019-05-09
申请号：US16240300
申请日：2019-01-04
申请人： Millind Mittal
发明人： Millind Mittal
IPC分类号： G06Q20/38 , G06Q20/32
摘要： Computerized payment method using short, temporary, transaction ID (TID) symbols. Payees (merchants) register their unique ID telecommunications devices (e.g. Smartphone and phone number), and financial institution with a payment server. When a payee initiates a financial transaction by requesting a TID from the server for that amount. The server sends a TID to the payee, which the payee then communicates to the payer (customer). The payer turn relays this TID to the server, which validates the transaction using the payer device. The server then releases funds to the payee. The server can preserve audit records, but security is enhanced because the merchant never directly accesses the customer's financial account. GPS coordinates and/or payer provided Group IDs may also be used to reduce the number of symbols used in the TID. For use case convenience, phone numbers may be used as a type of globally unique Group identification (GroupID).

93. 发明申请

US20170279963A1 METHOD AND APPARATUS FOR DATA CHANNEL AUGMENTED VOICE TELEPHONY SYSTEMS 审中-公开
公开(公告)号：US20170279963A1
公开(公告)日：2017-09-28
申请号：US15619470
申请日：2017-06-10
申请人： Millind Mittal
发明人： Millind Mittal
IPC分类号： H04M3/493 , H04M15/06
CPC分类号： H04M3/493 , H04M1/72552 , H04M1/72583 , H04M3/42382 , H04M3/4365 , H04M3/4931 , H04M3/5166 , H04M3/527 , H04M11/08 , H04M15/06 , H04M15/56 , H04M15/8083 , H04M15/8221 , H04M2201/42 , H04M2203/651
摘要： A computerized method of terminating audio telephone calls that provides the other party with more information as to why the telephone call was terminated. This method, which is particularly useful for computerized smartphones equipped with voice and data channel communications methods, automatically provides the user with a variety of different informative text messages that can be selected by the user and sent to the other party at the time that a voice call is terminated.

94. 发明申请

US20150121090A1 Method and Apparatus for Secure Execution Using a Secure Memory Partition 有权
公开(公告)号：US20150121090A1
公开(公告)日：2015-04-30
申请号：US14583062
申请日：2014-12-24
申请人： Millind MITTAL
发明人： Millind MITTAL
IPC分类号： G06F12/14 , G06F21/60
CPC分类号： G06F21/72 , G06F12/1408 , G06F12/1441 , G06F12/1491 , G06F21/60 , G06F21/602 , G06F21/78 , G06F2221/2107 , G06F2221/2125
摘要： A processor capable of secure execution. The processor contains an execution unit and secure partition logic that secures a partition in memory. The processor also contains cryptographic logic coupled to the execution unit that encrypts and decrypts secure data and code.

95. 发明申请

US20150113289A1 Method and Apparatus for Secure Execution Using a Secure Memory Partition 审中-公开
标题翻译：使用安全内存分区进行安全执行的方法和装置
公开(公告)号：US20150113289A1
公开(公告)日：2015-04-23
申请号：US14583054
申请日：2014-12-24
申请人： Millind MITTAL
发明人： Millind MITTAL
IPC分类号： G06F21/72 , G06F21/60
CPC分类号： G06F21/72 , G06F12/1408 , G06F12/1441 , G06F12/1491 , G06F21/60 , G06F21/602 , G06F21/78 , G06F2221/2107 , G06F2221/2125
摘要： A processor capable of secure execution. The processor contains an execution unit and secure partition logic that secures a partition in memory. The processor also contains cryptographic logic coupled to the execution unit that encrypts and decrypts secure data and code.
摘要翻译：能够安全执行的处理器。该处理器包含一个执行单元和安全的分区逻辑，将分区保存在内存中。处理器还包含耦合到执行单元的加密逻辑，其加密和解密安全数据和代码。

96. 发明申请

US20130124834A1 Method and Apparatus for Unpacking Packed Data 有权
公开(公告)号：US20130124834A1
公开(公告)日：2013-05-16
申请号：US13730848
申请日：2012-12-29
申请人： Alexander Peleg , Yaakov Yaari , Millind Mittal , Larry M. Mennemeier , Benny Eitan
发明人： Alexander Peleg , Yaakov Yaari , Millind Mittal , Larry M. Mennemeier , Benny Eitan
IPC分类号： G06F9/30
CPC分类号： G06F9/30036 , G06F7/49921 , G06F9/30025 , G06F9/30032 , G06F9/30109 , G06F9/3013 , G06F9/30145 , G06F9/30149 , G06F9/30167 , G06F9/30181 , G06F9/30192 , G06F9/30196
摘要： An apparatus includes an instruction decoder, first and second source registers and a circuit coupled to the decoder to receive packed data from the source registers and to unpack the packed data responsive to an unpack instruction received by the decoder. A first packed data element and a third packed data element are received from the first source register. A second packed data element and a fourth packed data element are received from the second source register. The circuit copies the packed data elements into a destination register resulting with the second packed data element adjacent to the first packed data element, the third packed data element adjacent to the second packed data element, and the fourth packed data element adjacent to the third packed data element.

97. 发明申请

US20130117538A1 Method and Apparatus for Unpacking Packed Data 有权
公开(公告)号：US20130117538A1
公开(公告)日：2013-05-09
申请号：US13730839
申请日：2012-12-29
申请人： Alexander Peleg , Yaakov Yaari , Millind Mittal , Larry M. Mennemeier , Benny Eitan
发明人： Alexander Peleg , Yaakov Yaari , Millind Mittal , Larry M. Mennemeier , Benny Eitan
IPC分类号： G06F9/30
CPC分类号： G06F9/30036 , G06F7/49921 , G06F9/30025 , G06F9/30032 , G06F9/30109 , G06F9/3013 , G06F9/30145 , G06F9/30149 , G06F9/30167 , G06F9/30181 , G06F9/30192 , G06F9/30196
摘要： An apparatus includes an instruction decoder, first and second source registers and a circuit coupled to the decoder to receive packed data from the source registers and to unpack the packed data responsive to an unpack instruction received by the decoder. A first packed data element and a third packed data element are received from the first source register. A second packed data element and a fourth packed data element are received from the second source register. The circuit copies the packed data elements into a destination register resulting with the second packed data element adjacent to the first packed data element, the third packed data element adjacent to the second packed data element, and the fourth packed data element adjacent to the third packed data element.

98. 发明授权

US08396915B2 Processor for performing multiply-add operations on packed data 失效
公开(公告)号：US08396915B2
公开(公告)日：2013-03-12
申请号：US13603370
申请日：2012-09-04
申请人： Alexander Peleg , Millind Mittal , Larry M. Mennemeier , Benny Eitan , Carole Dulong , Eiichi Kowashi , Wolf C. Witt
发明人： Alexander Peleg , Millind Mittal , Larry M. Mennemeier , Benny Eitan , Carole Dulong , Eiichi Kowashi , Wolf C. Witt
IPC分类号： G06F7/38
CPC分类号： G06F7/60 , G06F7/4812 , G06F7/49921 , G06F7/5324 , G06F7/5338 , G06F7/5443 , G06F9/3001 , G06F9/30036 , G06F9/30112 , G06F15/7817 , G06F17/10 , G06F17/147 , G06F17/16 , G06F2207/3828 , G06T1/20
摘要： A method and apparatus for including in a processor instructions for performing multiply-add operations on packed data. In one embodiment, a processor is coupled to a memory. The memory has stored therein a first packed data and a second packed data. The processor performs operations on data elements in said first packed data and said second packed data to generate a third packed data in response to receiving an instruction. At least two of the data elements in this third packed data storing the result of performing multiply-add operations on data elements in the first and second packed data.

99. 发明授权

US08356020B2 Multi-level compressed look-up tables formed by logical operations to compress selected index bits 有权
标题翻译：通过逻辑运算形成的多级压缩查找表来压缩选定的索引位
公开(公告)号：US08356020B2
公开(公告)日：2013-01-15
申请号：US12190692
申请日：2008-08-13
申请人： Millind Mittal
发明人： Millind Mittal
IPC分类号： G06F7/00
CPC分类号： G06F17/30961 , Y10S707/99942 , Y10S707/99943
摘要： A lookup is performed using multiple levels of compressed stride tables in a multi-bit Trie structure. An input lookup key is divided into several strides including a current stride of S bits. A valid entry in a current stride table is located by compressing the S bits to form a compressed index of D bits into the current stride table. A compression function logically combines the S bits to generate the D compressed index bits. An entry in a prior-level table points to the current stride table and has a field indicating which compression function and mask to use. Compression functions can include XOR, shifts, rotates, and multi-bit averaging. Rather than store all 2S entries, the current stride table is compressed to store only 2D entries. Ideally, the number of valid entries in the current stride table is between 2D−1 and 2D for maximum compression. Storage requirements are reduced.
摘要翻译：在多位Trie结构中使用多级压缩步幅表进行查找。输入查找键被分成包括S位的当前步幅的多个步骤。通过压缩S位来形成当前步幅表中的有效条目，以形成D位的压缩索引到当前步幅表中。压缩函数逻辑组合S位以产生D压缩索引位。前一级表中的条目指向当前步幅表，并具有指示要使用的压缩函数和掩码的字段。压缩功能可以包括XOR，移位，旋转和多位平均。而不是存储所有2S条目，当前步幅表被压缩以仅存储2D条目。理想情况下，当前步幅表中有效条目的数量在2D-1和2D之间用于最大压缩。存储要求降低。

100. 发明申请

US20120331028A1 PROCESSOR FOR PERFORMING MULTIPLY-ADD OPERATIONS ON PACKED DATA 失效
标题翻译：用于在包装数据上执行多重添加操作的处理器
公开(公告)号：US20120331028A1
公开(公告)日：2012-12-27
申请号：US13603370
申请日：2012-09-04
申请人： Alexander D. Peleg , Millind Mittal , Larry M. Mennemeier , Benny Eitan , Carole Dulong , Eiichi Kowashi , Wolf Witt
发明人： Alexander D. Peleg , Millind Mittal , Larry M. Mennemeier , Benny Eitan , Carole Dulong , Eiichi Kowashi , Wolf Witt
IPC分类号： G06F7/38
CPC分类号： G06F7/60 , G06F7/4812 , G06F7/49921 , G06F7/5324 , G06F7/5338 , G06F7/5443 , G06F9/3001 , G06F9/30036 , G06F9/30112 , G06F15/7817 , G06F17/10 , G06F17/147 , G06F17/16 , G06F2207/3828 , G06T1/20
摘要： A method and apparatus for including in a processor instructions for performing multiply-add operations on packed data. In one embodiment, a processor is coupled to a memory. The memory has stored therein a first packed data and a second packed data. The processor performs operations on data elements in said first packed data and said second packed data to generate a third packed data in response to receiving an instruction. At least two of the data elements in this third packed data storing the result of performing multiply-add operations on data elements in the first and second packed data.
摘要翻译：一种用于在处理器中包括用于对压缩数据进行乘法运算的指令的方法和装置。在一个实施例中，处理器耦合到存储器。存储器中存储有第一打包数据和第二打包数据。处理器对所述第一打包数据和所述第二打包数据中的数据元素执行操作，以响应于接收到指令而产生第三打包数据。该第三打包数据中的至少两个数据元素存储对第一和第二打包数据中的数据元素执行加法运算的结果。

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