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    • 91. 发明授权
    • Semiconductor device and manufacturing method thereof
    • 半导体装置及其制造方法
    • US08043902B2
    • 2011-10-25
    • US12512075
    • 2009-07-30
    • Hideto OhnumaShigeharu MonoeShunpei Yamazaki
    • Hideto OhnumaShigeharu MonoeShunpei Yamazaki
    • H01L21/00
    • H01L27/1214H01L27/124H01L27/1288H01L29/66757H01L29/78624
    • The present invention provides a TFT including at least one LDD region in a self-alignment manner without forming a sidewall spacer and increasing the number of manufacturing steps. A photomask or a reticle provided with an assist pattern that is formed of a diffraction grating pattern or a semi-transmitting film and has a function of reducing light intensity is employed in a photolithography step of forming a gate electrode, an asymmetrical resist pattern having a region with a thick thickness and a region with a thickness thinner than that of the above region on one side is formed, a gate electrode having a stepped portion is formed, and an LDD region is formed in a self-alignment manner by injecting an impurity element to the semiconductor layer through the region with a thin thickness of the gate electrode.
    • 本发明提供一种TFT,其以自对准方式提供至少一个LDD区域,而不形成侧壁间隔物并增加制造步骤的数量。 在形成栅电极的光刻步骤中使用具有由衍射光栅图案或半透射膜形成的辅助图案并具有降低光强度的功能的光掩模或掩模版,具有 形成厚度厚的区域和具有比一面上述区域的厚度薄的区域,形成具有台阶部分的栅电极,并且通过注入杂质以自对准方式形成LDD区域 元件通过具有薄的栅电极厚度的区域到半导体层。
    • 93. 发明授权
    • Method for manufacturing semiconductor device
    • 制造半导体器件的方法
    • US08026144B2
    • 2011-09-27
    • US12760573
    • 2010-04-15
    • Hideto Ohnuma
    • Hideto Ohnuma
    • H01L21/336
    • H01L29/66772H01L29/41783H01L29/6675H01L29/78618H01L29/78681
    • In a semiconductor device having a raised source and drain structure, in forming a raised region by etching, etching of an island-like semiconductor film which is an active layer is inhibited. In a method for manufacturing a semiconductor device, an insulating film is formed by oxidizing or nitriding the surface of an island-like semiconductor film, a semiconductor film is formed on a region which is a part of the insulating film, a gate electrode is formed over the insulating film, an impurity element imparting one conductivity type is added to the island-like semiconductor film and the semiconductor film using the gate electrode as a mask, the impurity element is activated by heating the island-like semiconductor film and the semiconductor film, and the part of the insulating film between the island-like semiconductor film and the semiconductor film disappears by heating the island-like semiconductor film and the semiconductor film.
    • 在具有升高的源极和漏极结构的半导体器件中,通过蚀刻形成凸起区域时,抑制作为有源层的岛状半导体膜的蚀刻。 在制造半导体器件的方法中,通过对岛状半导体膜的表面进行氧化或氮化来形成绝缘膜,在作为绝缘膜的一部分的区域上形成半导体膜,形成栅电极 在绝缘膜上,使用栅极电极作为掩模将岛状半导体膜和半导体膜添加到赋予一种导电类型的杂质元素,通过加热岛状半导体膜和半导体膜来激活杂质元素 并且岛状半导体膜与半导体膜之间的绝缘膜的一部分通过加热岛状半导体膜和半导体膜而消失。
    • 95. 发明授权
    • Semiconductor device
    • US07969363B2
    • 2011-06-28
    • US12830195
    • 2010-07-02
    • Kazuya HanaokaHideto OhnumaTeruyuki Fujii
    • Kazuya HanaokaHideto OhnumaTeruyuki Fujii
    • H01Q1/38
    • An object of the present invention is to prevent electrical characteristics of circuit elements from being adversely affected by copper diffusion in a semiconductor device having an integrated circuit and an antenna formed over the same substrate, which uses copper plating for the antenna. Another object is to prevent a defect of a semiconductor device due to poor connection between an antenna and an integrated circuit in a semiconductor device having the integrated circuit and the antenna formed over the same substrate. In a semiconductor device having an integrated circuit 100 and an antenna 101 formed over one substrate 102, when a copper plating layer 108 is used for a conductor of the antenna 101, it is possible to prevent copper diffusion to circuit elements and decrease an adverse effect on electrical characteristics of circuit elements due to the copper diffusion because a base layer 107 of the antenna 101 uses a nitride film of a predetermined metal. Moreover, by the use of nickel nitride as a metal nitride for the base layer of the antenna, poor connection between the antenna and the integrated circuit can be decreased.
    • 96. 发明授权
    • Method of manufacturing a semiconductor device
    • 制造半导体器件的方法
    • US07955912B2
    • 2011-06-07
    • US12823175
    • 2010-06-25
    • Hideto OhnumaIchiro Uehara
    • Hideto OhnumaIchiro Uehara
    • H01L21/84
    • H01L27/1288H01L21/28114H01L21/32136H01L21/32139H01L27/1214H01L29/42384H01L29/66598H01L29/66757H01L29/78621H01L29/78627H01L2029/7863Y10S438/949
    • Formation of LDD structures and GOLD structures in a semiconductor device is conventionally performed in a self aligning manner with gate electrodes as masks, but there are many cases in which the gate electrodes have two layer structures, and film formation processes and etching processes become complex. Further, in order to perform formation of LDD structures and GOLD structures only by processes such as dry etching, the transistor structures all have the same structure, and it is difficult to form LDD structures, GOLD structures, and single drain structures separately for different circuits. By applying a photolithography process for forming gate electrodes to photomasks or reticles, in which supplemental patterns having a function of reducing the intensity of light and composed of diffraction grating patterns or translucent films, are established, GOLD structure, LDD structure, and single drain structure transistors can be easily manufactured for different circuits through dry etching and ion injection process steps.
    • 通常以半导体器件中的LDD结构和GOLD结构的形式,以栅电极作为掩模进行自对准,但是栅电极具有两层结构的情况很多,成膜工艺和蚀刻工艺变得复杂。 此外,为了仅通过诸如干蚀刻的工艺来形成LDD结构和GOLD结构,晶体管结构都具有相同的结构,并且难以分别形成用于不同电路的LDD结构,GOLD结构和单个漏极结构 。 通过应用用于形成栅电极的光刻工艺来形成光掩模或掩模版,其中具有降低光强度并且由衍射光栅图案或半透明膜构成的功能的补充图案,GOLD结构,LDD结构和单漏极结构 通过干蚀刻和离子注入工艺步骤可以容易地为不同的电路制造晶体管。
    • 97. 发明授权
    • Method for manufacturing semiconductor device
    • 制造半导体器件的方法
    • US07951656B2
    • 2011-05-31
    • US12467454
    • 2009-05-18
    • Sho KatoSatoshi ToriumiFumito IsakaHideto Ohnuma
    • Sho KatoSatoshi ToriumiFumito IsakaHideto Ohnuma
    • H01L21/00H01L21/336H01L21/30
    • H01L21/84H01L21/76251
    • A stack including at least an insulating layer, a first electrode, and a first impurity semiconductor layer is provided over a supporting substrate; a first semiconductor layer to which an impurity element imparting one conductivity type is added is formed over the first impurity semiconductor layer; a second semiconductor layer to which an impurity element imparting the one conductivity type is added is formed over the first semiconductor layer under a condition different from that of the first semiconductor layer; crystallinity of the first semiconductor layer and crystallinity of the second semiconductor layer are improved by a solid-phase growth method to form a second impurity semiconductor layer; an impurity element imparting the one conductivity type and an impurity element imparting a conductivity type different from the one conductivity type are added to the second impurity semiconductor layer; and a gate electrode layer is formed via a gate insulating layer.
    • 至少包括绝缘层,第一电极和第一杂质半导体层的叠层设置在支撑基板上; 在所述第一杂质半导体层上形成添加有赋予一种导电类型的杂质元素的第一半导体层; 在与第一半导体层不同的条件下,在第一半导体层上形成添加有赋予一种导电型的杂质元素的第二半导体层; 通过固相生长法提高第一半导体层的结晶度和第二半导体层的结晶度,形成第二杂质半导体层; 赋予一种导电类型的杂质元素和赋予不同于一种导电类型的导电类型的杂质元素添加到第二杂质半导体层; 并且经由栅极绝缘层形成栅极电极层。
    • 99. 发明申请
    • METHOD OF MANUFACTURING SOI SUBSTRATE AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE
    • 制造SOI衬底的方法和制造半导体器件的方法
    • US20110097872A1
    • 2011-04-28
    • US12986582
    • 2011-01-07
    • Shunpei YAMAZAKIHideto OHNUMA
    • Shunpei YAMAZAKIHideto OHNUMA
    • H01L21/3105
    • H01L21/2007H01L21/76254
    • A first substrate of single-crystal silicon within which is formed an embrittled layer and over a surface of which is formed a first insulating film is provided; a second insulating film is formed over a surface of a second substrate; at least one surface of either the first insulating film or the second insulating film is exposed to a plasma atmosphere or an ion atmosphere, and that surface of the first insulating film or the second insulating film is activated; the first substrate and the second substrate are bonded together with the first insulating film and the second insulating film interposed therebetween; a single-crystal silicon film is separated from the first substrate at an interface of the embrittled layer of the first substrate, and a thin film single-crystal silicon film is formed over the second substrate with the first insulating film and the second insulating film interposed therebetween.
    • 提供了单晶硅的第一基板,其中形成有脆化层,并且其表面上形成有第一绝缘膜; 在第二基板的表面上形成第二绝缘膜; 第一绝缘膜或第二绝缘膜的至少一个表面暴露于等离子体气氛或离子气氛中,并且第一绝缘膜或第二绝缘膜的表面被激活; 第一基板和第二基板与第一绝缘膜和第二绝缘膜接合在一起; 在第一衬底的脆化层的界面处将单晶硅膜与第一衬底分离,并且在第二衬底上形成薄膜单晶硅膜,其中第一绝缘膜和第二绝缘膜插入 之间。