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1. 发明申请

US20110172445A1 Novel Antischistosomal Agent 审中-公开
标题翻译：新型抗血吸虫药
公开(公告)号：US20110172445A1
公开(公告)日：2011-07-14
申请号：US13001676
申请日：2009-06-26
申请人： Yusuke Wataya , Hye-Sook Kim , Akiko Hiramoto , Akira Sato , Nobuo Ota , Takashi Kumagai , Rieko Shimogawara , Toshie Taniguchi
发明人： Yusuke Wataya , Hye-Sook Kim , Akiko Hiramoto , Akira Sato , Nobuo Ota , Takashi Kumagai , Rieko Shimogawara , Toshie Taniguchi
IPC分类号： C07D323/00
CPC分类号： C07D323/00 , A61K31/357 , C07D325/00 , Y02A50/423
摘要： An object of the present invention is to provide a novel antischistosomal agent, and more specifically, to provide a novel drug capable of inhibiting a growth of schistosomes in vivo to prevent development of liver dysfunction due to eggs of the schistosomes in the case of infection with the schistosomes. The novel antischistosomal agent includes as an active ingredient a peroxide derivative. Specifically, the novel antischistosomal agent includes as an active ingredient a peroxide derivative represented by the general formula (I): where C represents an alicyclic hydrocarbon ring group which may be substituted, and n represents an integer of 1 to 6.
摘要翻译：本发明的目的是提供一种新的抗血吸虫药，更具体地说，提供一种能够在体内抑制血吸虫生长的新型药物，以防止在感染情况下由于血吸虫卵产生的肝功能障碍的发展血吸虫新型抗血吸虫药包括作为活性成分的过氧化物衍生物。具体地说，新型抗血吸虫药包括作为活性成分的通式（I）表示的过氧化物衍生物：其中C表示可被取代的脂环族烃环基，n表示1〜6的整数。

2. 发明授权

US08896316B2 Device having capacitive loads and abnormality detecting method thereof 有权
标题翻译：具有容性负载的装置及其异常检测方法
公开(公告)号：US08896316B2
公开(公告)日：2014-11-25
申请号：US13582661
申请日：2010-06-17
申请人： Kazutoshi Kurahashi , Takashi Kumagai , Taichiro Tamida , Hajime Nakatani , Daisuke Takauchi
发明人： Kazutoshi Kurahashi , Takashi Kumagai , Taichiro Tamida , Hajime Nakatani , Daisuke Takauchi
IPC分类号： G01R31/00 , C01B13/11 , G01R31/327 , G01R35/00 , G01R19/25 , H01H31/02 , G01R31/02
CPC分类号： C01B13/11 , G01R19/2513 , G01R31/025 , G01R31/3277 , G01R35/00
摘要： In a device having capacitive loads in which a plurality of capacitive loads are connected in parallel, power is supplied from an AC power source to a load group comprising the plurality of capacitive loads, the load group is divided into a plurality of small load groups, and a current detecting sensor for detecting a current which flows in at least one small load group at a side which is closer to the load side than a branch point at which the load group is divided into the plurality of small load groups and a current abnormality detecting part for determining an abnormality of a load by a current detecting signal which is detected by the current detecting sensor are equipped.
摘要翻译：在具有并联连接多个容性负载的容性负载的装置中，从AC电源向包括多个容性负载的负载组提供电力，负载组被分成多个小负载组，以及电流检测传感器，用于检测在负载组被分割成多个小负载组的分支点处，在比靠近负载侧的一侧的至少一个小负载组中流动的电流和电流异常检测由电流检测传感器检测出的电流检测信号确定负载异常的检测部件。

3. 发明申请

US20120319696A1 DEVICE HAVING CAPACITIVE LOADS AND ABNORMALITY DETECTING METHOD THEREOF 有权
标题翻译：具有电容负载的装置及其非正常检测方法
公开(公告)号：US20120319696A1
公开(公告)日：2012-12-20
申请号：US13582661
申请日：2010-06-17
申请人： Kazutoshi Kurahashi , Takashi Kumagai , Taichiro Tamida , Hajime Nakatani , Daisuke Takauchi
发明人： Kazutoshi Kurahashi , Takashi Kumagai , Taichiro Tamida , Hajime Nakatani , Daisuke Takauchi
IPC分类号： G01R19/00 , G01R31/00
CPC分类号： C01B13/11 , G01R19/2513 , G01R31/025 , G01R31/3277 , G01R35/00
摘要： In a device having capacitive loads in which a plurality of capacitive loads are connected in parallel, power is supplied from an AC power source to a load group comprising the plurality of capacitive loads, the load group is divided into a plurality of small load groups, and a current detecting sensor for detecting a current which flows in at least one small load group at a side which is closer to the load side than a branch point at which the load group is divided into the plurality of small load groups and a current abnormality detecting part for determining an abnormality of a load by a current detecting signal which is detected by the current detecting sensor are equipped.
摘要翻译：在具有并联连接多个容性负载的容性负载的装置中，从AC电源向包括多个容性负载的负载组提供电力，负载组被分成多个小负载组，以及电流检测传感器，用于检测在负载组被分割成多个小负载组的分支点处，在比靠近负载侧的一侧的至少一个小负载组中流动的电流和电流异常检测由电流检测传感器检测出的电流检测信号确定负载异常的检测部件。

4. 发明授权

US08159766B2 Data processing system having data reproduction independent of data processing 有权
标题翻译：具有独立于数据处理的数据再现的数据处理系统
公开(公告)号：US08159766B2
公开(公告)日：2012-04-17
申请号：US11434723
申请日：2006-05-17
申请人： Toshiyuki Arai , Takashi Kumagai , Hajime Inai , Hiroaki Sato , Fumitake Yodo , Masami Oyama
发明人： Toshiyuki Arai , Takashi Kumagai , Hajime Inai , Hiroaki Sato , Fumitake Yodo , Masami Oyama
IPC分类号： G11B5/00
CPC分类号： G11B31/00 , G11B20/00007 , G11B20/10527 , G11B27/005 , G11B27/034 , G11B27/105 , G11B27/11 , G11B27/329 , G11B27/34 , G11B2220/213 , G11B2220/2525 , G11B2220/2545 , G11B2220/2562 , H04R5/02
摘要： An information-processing apparatus includes a processing unit that compresses inputted data to produce compressed data of a first compressed format. The information-processing apparatus also includes a storage unit that stores the compressed data in a storage medium. The processing unit decompresses data, stored in the storage medium, of a second compressed format to produce decompressed data. Further, the processing unit controls the storage unit to store the compressed data of the first compressed format in the storage medium while the processing unit simultaneously decompresses the data, stored in the storage medium, of the second compressed format and reproduces the decompressed data. The first compressed format is different than the second compressed format.
摘要翻译：信息处理装置包括：处理单元，其压缩输入的数据以产生第一压缩格式的压缩数据。信息处理装置还包括将压缩数据存储在存储介质中的存储单元。处理单元将存储在存储介质中的数据解压缩第二压缩格式以产生解压缩数据。此外，处理单元控制存储单元将存储介质中的第一压缩格式的压缩数据存储在存储介质中，同时处理单元将存储在存储介质中的数据解压缩第二压缩格式，并再现解压缩数据。第一种压缩格式与第二种压缩格式不同。

5. 发明申请

US20120019566A1 Integrated circuit device and electronic instrument 有权
标题翻译：集成电路器件和电子仪器
公开(公告)号：US20120019566A1
公开(公告)日：2012-01-26
申请号：US13137995
申请日：2011-09-23
申请人： Satoru Ito , Masahiko Moriguchi , Kazuhiro Maekawa , Noboru Itomi , Satoru Kodaira , Junichi Karasawa , Takashi Kumagai , Hisanobu Ishiyama , Takashi Fujise
发明人： Satoru Ito , Masahiko Moriguchi , Kazuhiro Maekawa , Noboru Itomi , Satoru Kodaira , Junichi Karasawa , Takashi Kumagai , Hisanobu Ishiyama , Takashi Fujise
IPC分类号： G09G5/10
CPC分类号： G09G3/3688 , G09G3/2011 , G09G2330/02 , G09G2330/04 , H01L2224/05553
摘要： An integrated circuit device includes first to Nth circuit blocks CB1 to CBN, a first interface region disposed along a fourth side and on the D2 side of the first to Nth circuit blocks CB1 to CBN, and a second interface region disposed along a second side and on the D4 side of the first to Nth circuit blocks CB1 to CBN. A local line LLG formed using a wiring layer lower than an Ith layer is provided between the adjacent circuit blocks as at least one of a signal line and a power supply line. Global lines GLG and GLD formed using the Ith or higher wiring layer are provided along the direction D1 over the circuit block disposed between the nonadjacent circuit blocks as at least one of a signal line and a power supply line.
摘要翻译：集成电路装置包括第一至第N电路块CB1至CBN，沿第一至第N电路块CB1至CBN的第四侧和第二侧设置的第一接口区域以及沿着第二侧设置的第二接口区域，在第一至第N电路块CB1至CBN的D4侧。使用低于第I层的布线层形成的局部线LLG设置在相邻的电路块之间，作为信号线和电源线中的至少一个。使用第I或更高布线层形成的全局线GLG和GLD沿着方向D1设置在布置在不相邻电路块之间的电路块上，作为信号线和电源线中的至少一个。

6. 发明授权

US08054710B2 Integrated circuit device and electronic instrument 有权
标题翻译：集成电路器件和电子仪器
公开(公告)号：US08054710B2
公开(公告)日：2011-11-08
申请号：US11477670
申请日：2006-06-30
申请人： Satoru Ito , Masahiko Moriguchi , Kazuhiro Maekawa , Noboru Itomi , Satoru Kodaira , Junichi Karasawa , Takashi Kumagai , Hisanobu Ishiyama , Takashi Fujise
发明人： Satoru Ito , Masahiko Moriguchi , Kazuhiro Maekawa , Noboru Itomi , Satoru Kodaira , Junichi Karasawa , Takashi Kumagai , Hisanobu Ishiyama , Takashi Fujise
IPC分类号： G11C8/00
CPC分类号： G09G3/3688 , G09G3/2011 , G09G2330/02 , G09G2330/04 , H01L2224/05553
摘要： An integrated circuit device includes first to Nth circuit blocks CB1 to CBN, a first interface region disposed along a fourth side and on the D2 side of the first to Nth circuit blocks CB1 to CBN, and a second interface region disposed along a second side and on the D4 side of the first to Nth circuit blocks CB1 to CBN. A local line LLG formed using a wiring layer lower than an Ith layer is provided between the adjacent circuit blocks as at least one of a signal line and a power supply line. Global lines GLG and GLD formed using the Ith or higher wiring layer are provided along the direction D1 over the circuit block disposed between the nonadjacent circuit blocks as at least one of a signal line and a power supply line.
摘要翻译：集成电路装置包括第一至第N电路块CB1至CBN，沿第一至第N电路块CB1至CBN的第四侧和第二侧设置的第一接口区域以及沿着第二侧设置的第二接口区域，在第一至第N电路块CB1至CBN的D4侧。使用低于第I层的布线层形成的局部线LLG设置在相邻的电路块之间，作为信号线和电源线中的至少一个。使用第I或更高布线层形成的全局线GLG和GLD沿着方向D1设置在布置在不相邻电路块之间的电路块上，作为信号线和电源线中的至少一个。

7. 发明授权

US07986541B2 Integrated circuit device and electronic instrument 有权
标题翻译：集成电路器件和电子仪器
公开(公告)号：US07986541B2
公开(公告)日：2011-07-26
申请号：US11270630
申请日：2005-11-10
申请人： Satoru Kodaira , Noboru Itomi , Shuji Kawaguchi , Takashi Kumagai , Junichi Karasawa , Satoru Ito
发明人： Satoru Kodaira , Noboru Itomi , Shuji Kawaguchi , Takashi Kumagai , Junichi Karasawa , Satoru Ito
IPC分类号： G11C5/06
CPC分类号： G09G3/2007 , G09G2300/0426 , G09G2310/0267 , G09G2310/027 , G11C5/063
摘要： An integrated circuit device has a display memory which stores data for at least one frame displayed in a display panel which has a plurality of scan lines and a plurality of data lines, the display memory includes a plurality of RAM blocks, each of the RAM blocks including a plurality of wordlines, a plurality of bitlines, a plurality of memory cells, and a wordline control circuit, each of the RAM blocks is disposed along a first direction in which the bitlines extend, each of the memory cells has a short side and a long side, the bitlines are formed along a direction in which the long side of the memory cell extends, and the wordlines are formed along a direction in which the short side of the memory cell extends.
摘要翻译：集成电路装置具有显示存储器，其存储显示在具有多条扫描线和多条数据线的显示面板中的至少一帧的数据，显示存储器包括多个RAM块，每个RAM块包括多个字线，多个位线，多个存储器单元和字线控制电路，每个RAM块沿着位线延伸的第一方向设置，每个存储单元具有短边和长边，沿着存储单元的长边延伸的方向形成位线，并且沿着存储单元的短边延伸的方向形成字线。

8. 发明授权

US07924833B2 Packet transfer unit 有权
标题翻译：分组传送单元
公开(公告)号：US07924833B2
公开(公告)日：2011-04-12
申请号：US12385357
申请日：2009-04-06
申请人： Tatsuo Kanetake , Kazuo Sugai , Takashi Kumagai
发明人： Tatsuo Kanetake , Kazuo Sugai , Takashi Kumagai
IPC分类号： H04L12/28 , H04L12/56
CPC分类号： H04L49/552 , H04L49/3009 , H04L49/354
摘要： The present invention relates to a packet transfer unit, which comprises a search key memory that stores a search key for a transfer destination of a packet and verification information generated from the search key, in association with a storage location of transfer information memorized in a transfer information memory, wherein a transfer information acquisition unit searches the search key memory by using the search key generated based on the header information and the verification information generated from the search key, acquires storage location information of the transfer information from the search key memory when a match with the search key and the verification information memorized in the search key memory is found, and acquires the transfer information stored in the transfer information memory based on the acquired storage location information, and wherein a transfer unit transfers the packet based on the acquired transfer information.
摘要翻译：本发明涉及一种分组传送单元，其包括搜索密钥存储器，其存储用于分组的传送目的地的搜索关键字和从搜索关键字生成的验证信息，与存储在传送中的传送信息的存储位置相关联信息存储器，其中传送信息获取单元通过使用基于标题信息生成的搜索关键字和从搜索关键字生成的验证信息来搜索搜索关键字存储器，当搜索关键字存储器找到与搜索关键字相匹配的存储位置信息和存储在搜索关键字存储器中的验证信息，并且基于所获取的存储位置信息获取存储在传送信息存储器中的传送信息，并且其中传送单元基于所获取的传送信息。

9. 发明授权

US07711698B2 Communication system, communication method, distribution apparatus, distribution method and terminal apparatus 有权
标题翻译：通信系统，通信方法，配电设备，配电方式和终端设备
公开(公告)号：US07711698B2
公开(公告)日：2010-05-04
申请号：US11255004
申请日：2005-10-20
申请人： Takashi Kumagai , Izuru Tanaka
发明人： Takashi Kumagai , Izuru Tanaka
IPC分类号： G06F7/00
CPC分类号： H04N7/173 , G06F21/10 , G06Q20/085 , G06Q20/123 , G06Q20/32 , G06Q20/3221 , G06Q30/0283 , G06Q30/0601 , G06Q2220/12 , G11B27/034 , G11B27/11 , G11B27/34 , G11B2220/20 , G11B2220/2525 , G11B2220/41 , G11B2220/65 , H04H60/21 , H04H60/27 , H04N21/2225 , H04N21/254 , H04N21/2543 , H04N21/6125 , H04N21/6175 , H04N21/85403 , H04Q11/04 , H04Q2213/13093 , H04Q2213/13097 , H04Q2213/13103 , H04Q2213/13106 , H04Q2213/13176 , H04Q2213/13204 , H04Q2213/13216 , H04Q2213/13299 , H04Q2213/13333 , H04Q2213/13376 , H04Q2213/13389 , H04Q2213/13399 , Y10S707/944 , Y10S707/99931 , Y10S707/99932 , Y10S707/99936 , Y10S707/99948
摘要： A communication system includes a first storage section for storing a plurality of pieces of contents information, a second storage section for storing a plurality of pieces of contents information, a control section for accessing the contents information stored in the first storage section and the second storage section based on a single set of management information for managing the contents information stored in the first storage section and the second storage section, a communication section for interconnecting the first storage section, the second storage section and the control section for communication, and an accounting setting section for setting an amount of money to be imposed on a predetermined user in response to use of the first storage section or the second storage section.
摘要翻译：一种通信系统，包括用于存储多条内容信息的第一存储部分，用于存储多条内容信息的第二存储部分，用于访问存储在第一存储部分中的内容信息的控制部分和第二存储器基于用于管理存储在第一存储部分和第二存储部分中的内容信息的单组管理信息的部分，用于互连第一存储部分，第二存储部分和用于通信的控制部分的通信部分，以及会计设置部分，用于响应于使用第一存储部分或第二存储部分而设置要对预定用户施加的金额。

10. 发明申请

US20090091580A1 Integrated circuit device and electronic instrument 有权
标题翻译：集成电路器件和电子仪器
公开(公告)号：US20090091580A1
公开(公告)日：2009-04-09
申请号：US12292996
申请日：2008-12-02
申请人： Satoru Kodaira , Noboru Itomi , Shuji Kawaguchi , Takashi Kumagai , Junichi Karasawa , Satoru Ito
发明人： Satoru Kodaira , Noboru Itomi , Shuji Kawaguchi , Takashi Kumagai , Junichi Karasawa , Satoru Ito
IPC分类号： G09G5/39
CPC分类号： G09G3/3685 , G09G3/20 , G09G3/3611 , G09G5/39 , G09G5/395 , G09G2300/0426 , G09G2310/0218 , G09G2310/027 , G09G2310/0278 , G09G2360/12
摘要： An integrated circuit device having a display memory which stores data for at least one frame from among image information displayed in a display panel which has a plurality of scan lines and a plurality of data lines, the display memory including a plurality of wordlines, a plurality of bitlines, a plurality of memory cells, and a wordline control circuit; and the wordline control circuit selecting an identical wordline N times (N is an integer larger than one) from among the wordlines in one horizontal scan period of the display panel.
摘要翻译：一种具有显示存储器的集成电路装置，该显示存储器从显示在具有多个扫描线和多条数据线的显示面板中的图像信息中存储至少一帧的数据，所述显示存储器包括多个字线，多个位线，多个存储单元和字线控制电路; 并且字线控制电路在显示面板的一个水平扫描周期中从字线中选择相同的字线N次（N是大于1的整数）。

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