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1. 发明授权

US08043772B2 Manufacturing method and manufacturing system of semiconductor device 有权
标题翻译：半导体器件的制造方法和制造系统
公开(公告)号：US08043772B2
公开(公告)日：2011-10-25
申请号：US12466695
申请日：2009-05-15
申请人： Toshiharu Miwa , Junko Konishi , Toshihide Kawachi , Shigenori Yamashita , Takeshi Tashiro , Hidekimi Fudo
发明人： Toshiharu Miwa , Junko Konishi , Toshihide Kawachi , Shigenori Yamashita , Takeshi Tashiro , Hidekimi Fudo
IPC分类号： G03F9/00
CPC分类号： G03F7/70641 , G03F7/70625
摘要： In an exposure process forming a predetermined circuit pattern of a semiconductor device on a wafer, a resist dimension of the resist pattern formed on a wafer and a focus position in the exposure process at a past time are measured. A resist dimension and a focus position of a wafer to which the exposure process is secondly performed are estimated by using measurement results of the measured resist dimension and focus position, and a focus offset value is calculated by using estimated values of the estimated resist dimension and focus position. Then, an exposure dose is calculated with considering this focus offset value, and a resist pattern is formed on the wafer to which the exposure process is performed by using the calculated exposure dose and focus offset value.
摘要翻译：在形成晶片上的半导体器件的预定电路图形的曝光工艺中，测量在过去时刻在曝光处理中形成在晶片上的抗蚀剂图案的抗蚀剂尺寸和聚焦位置。通过使用被测量的抗蚀剂尺寸和聚焦位置的测量结果来估计第二次进行曝光处理的晶片的抗蚀剂尺寸和聚焦位置，并且通过使用估计的抗蚀剂尺寸的估计值来计算聚焦偏移值，焦点位置。然后，考虑该聚焦偏移值计算曝光剂量，并且通过使用计算出的曝光剂量和聚焦偏移值，在进行了曝光处理的晶片上形成抗蚀剂图案。

2. 发明授权

US07879516B2 Manufacturing method of semiconductor integrated circuit device 有权
标题翻译：半导体集成电路器件的制造方法
公开(公告)号：US07879516B2
公开(公告)日：2011-02-01
申请号：US12101956
申请日：2008-04-11
申请人： Toshihide Kawachi , Hidekimi Fudo
发明人： Toshihide Kawachi , Hidekimi Fudo
IPC分类号： G03C5/00 , G03F7/00
CPC分类号： G03F7/7085 , G03F7/70558 , G03F7/70625 , G03F7/70641 , H01L21/0275
摘要： In the semiconductor integrated circuit device lithography process it is becoming more and more essential to control both exposure dose and focus value independently with a high accuracy. Using a wafer treated precedingly, a section profile of a photoresist is acquired by the technique of scatterometry, then both exposure dose and focus value are estimated independently with a high accuracy on the basis of the section profile thus acquired and using a conjectural expression obtained by the technique of multivariate analysis, and a focus setting in the exposure of a succeedingly treated wafer is corrected on the basis of the estimated exposure dose and focus value.
摘要翻译：在半导体集成电路器件光刻工艺中，以高精度独立地控制曝光剂量和聚焦值变得越来越重要。使用之前处理的晶片，通过散射技术获得光致抗蚀剂的截面轮廓，然后基于所获得的截面轮廓，以高精度独立地估计曝光剂量和聚焦值，并使用由基于估计的曝光剂量和聚焦值来校正多变量分析技术和接下来处理的晶片的曝光中的焦点设置。

3. 发明授权

US06617080B1 Photomask, semiconductor device, and method for exposing through photomask 失效
标题翻译：光掩模，半导体器件和通过光掩模曝光的方法
公开(公告)号：US06617080B1
公开(公告)日：2003-09-09
申请号：US09563953
申请日：2000-05-02
申请人： Toshihide Kawachi , Takuya Matsushita , Shigenori Yamashita , Yuki Miyamoto , Atsushi Ueno , Shinroku Maejima
发明人： Toshihide Kawachi , Takuya Matsushita , Shigenori Yamashita , Yuki Miyamoto , Atsushi Ueno , Shinroku Maejima
IPC分类号： G03F900
CPC分类号： G03F7/70633
摘要： The present invention provides a photomask, a semiconductor device, and a method for exposing through the photomask. The photomask comprises a photomask substrate, and an on-mask circuit area including an on-mask circuit pattern and an on-mask test mark area including an on-mask test pattern, both formed on the surface of the substrate, wherein the photomask substrate further includes an on-mask photolithography screening mark area including an on-mask comparison pattern and an on-mask screening pattern, the on-mask comparison pattern has substantially the same configuration as at least a part of the on-mask circuit pattern, and the on-mask screening pattern has substantially the same configuration as at least a part of the on-mask test pattern. The present invention allows it to measure the actual displacement generated from an overlaying (i.e. alignment) process for the purpose of eliminating of an the overlay displacement which can take place in a photolithography process.
摘要翻译：本发明提供了一种光掩模，半导体器件和用于曝光光掩模的方法。光掩模包括光掩模基板和包括掩模电路图案的掩模电路区域和包括掩模测试图案的掩模测试标记区域，二者都形成在基板的表面上，其中光掩模基板进一步包括包括掩膜比较图案和掩模屏蔽图案的掩模光刻掩模标记区域，掩模比较图案具有与至少一部分屏蔽电路图案基本相同的配置，以及掩模掩模图案具有与掩模测试图案的至少一部分基本相同的构造。本发明允许它测量从重叠（即对准）过程产生的实际位移，以消除可能在光刻工艺中发生的覆盖位移。

4. 发明授权

US5868560A Reticle, pattern transferred thereby, and correction method 失效
标题翻译：掩模版，由此转移的图案，以及校正方法
公开(公告)号：US5868560A
公开(公告)日：1999-02-09
申请号：US940946
申请日：1997-09-30
申请人： Naohisa Tamada , Toshihide Kawachi , Yuki Miyamoto
发明人： Naohisa Tamada , Toshihide Kawachi , Yuki Miyamoto
IPC分类号： G03F1/42 , G03F7/20 , G03F9/00 , H01L21/027
CPC分类号： G03F7/70591 , G03F7/70633
摘要： A reticle that allows deviation in rotation and magnification of an exposure region detected just using a wafer subjected to exposure and development without having to provide an underlying pattern, a pattern transferred using such a reticle, and a correction method are achieved. A first measurement pattern is provided on a dicing line pattern of the X axis direction. Also, a second measurement pattern is formed on a line of extension of the first measurement pattern in the Y axis direction. Similarly, a third measurement pattern is formed on the dicing line pattern in the Y axis direction. A fourth measurement pattern is provided corresponding to the third measurement pattern.
摘要翻译：实现了掩模版，其允许仅使用经受曝光和显影的晶片检测到的曝光区域的旋转偏移和放大率，而不必提供下面的图案，使用这种掩模版转印的图案和校正方法。在X轴方向的切割线图案上设置第一测量图案。此外，在Y轴方向上的第一测量图案的延伸线上形成第二测量图案。类似地，在切割线图案上沿Y轴方向形成第三测量图案。对应于第三测量图案提供第四测量图案。

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