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1. 发明申请

US20130001792A1 SEMICONDUCTOR DEVICE 有权
标题翻译：半导体器件
公开(公告)号：US20130001792A1
公开(公告)日：2013-01-03
申请号：US13531567
申请日：2012-06-24
申请人： Tomoaki UNO , Yoshitaka Onaya , Hirokazu Kato , Ryotaro Kudo , Koji Saikusa , Katsuhiko Funatsu
发明人： Tomoaki UNO , Yoshitaka Onaya , Hirokazu Kato , Ryotaro Kudo , Koji Saikusa , Katsuhiko Funatsu
IPC分类号： H01L23/48
CPC分类号： H01L23/49575 , H01L23/3107 , H01L23/4824 , H01L23/49524 , H01L23/49562 , H01L24/37 , H01L24/40 , H01L24/73 , H01L2224/05554 , H01L2224/32245 , H01L2224/37011 , H01L2224/371 , H01L2224/37124 , H01L2224/37147 , H01L2224/37599 , H01L2224/40095 , H01L2224/40245 , H01L2224/48091 , H01L2224/48137 , H01L2224/48247 , H01L2224/73221 , H01L2224/73265 , H01L2224/83801 , H01L2224/8385 , H01L2224/84801 , H01L2224/8485 , H01L2924/1306 , H01L2924/13091 , H01L2924/181 , H01L2924/30107 , H01L2924/351 , H02M3/1588 , H02M2001/0009 , Y02B70/1466 , H01L2924/00012 , H01L2924/00 , H01L2924/00014
摘要： A power MOSFET for switching and a sense MOSFET having an area smaller than that of the power MOSFET and configured to detect an electric current flowing through the power MOSFET are formed within one semiconductor chip CPH and the semiconductor chip CPH is mounted over a chip mounting part via an electrically conductive joining material and sealed with a resin. In a main surface of the semiconductor chip CPH, a sense MOSFET region in which the sense MOSFET is formed is located more internally than a source pad PDHS4 of the sense MOSFET region RG2. Furthermore, in the main surface of the semiconductor chip, the sense MOSFET region RG2 is surrounded by a region in which the power MOSFET is formed.
摘要翻译：用于开关的功率MOSFET和具有小于功率MOSFET的面积并且被配置为检测流过功率MOSFET的电流的感测MOSFET形成在一个半导体芯片CPH内，并且半导体芯片CPH安装在芯片安装部分通过导电接合材料并用树脂密封。在半导体芯片CPH的主表面中，形成感测MOSFET的感测MOSFET区域位于读出MOSFET区域RG2的源极焊盘PDHS4的内部。此外，在半导体芯片的主表面中，感测MOSFET区域RG2由形成功率MOSFET的区域包围。

2. 发明授权

US08633550B2 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US08633550B2
公开(公告)日：2014-01-21
申请号：US13531567
申请日：2012-06-24
申请人： Tomoaki Uno , Yoshitaka Onaya , Hirokazu Kato , Ryotaro Kudo , Koji Saikusa , Katsuhiko Funatsu
发明人： Tomoaki Uno , Yoshitaka Onaya , Hirokazu Kato , Ryotaro Kudo , Koji Saikusa , Katsuhiko Funatsu
IPC分类号： H01L27/088
CPC分类号： H01L23/49575 , H01L23/3107 , H01L23/4824 , H01L23/49524 , H01L23/49562 , H01L24/37 , H01L24/40 , H01L24/73 , H01L2224/05554 , H01L2224/32245 , H01L2224/37011 , H01L2224/371 , H01L2224/37124 , H01L2224/37147 , H01L2224/37599 , H01L2224/40095 , H01L2224/40245 , H01L2224/48091 , H01L2224/48137 , H01L2224/48247 , H01L2224/73221 , H01L2224/73265 , H01L2224/83801 , H01L2224/8385 , H01L2224/84801 , H01L2224/8485 , H01L2924/1306 , H01L2924/13091 , H01L2924/181 , H01L2924/30107 , H01L2924/351 , H02M3/1588 , H02M2001/0009 , Y02B70/1466 , H01L2924/00012 , H01L2924/00 , H01L2924/00014
摘要： To improve reliability of a semiconductor deviceA power MOSFET for switching and a sense MOSFET having an area smaller than that of the power MOSFET and configured to detect an electric current flowing through the power MOSFET are formed within one semiconductor chip CPH and the semiconductor chip CPH is mounted over a chip mounting part via an electrically conductive joining material and sealed with a resin. In a main surface of the semiconductor chip CPH, a sense MOSFET region in which the sense MOSFET is formed is located more internally than a source pad PDHS4 of the sense MOSFET region RG2. Furthermore, in the main surface of the semiconductor chip, the sense MOSFET region RG2 is surrounded by a region in which the power MOSFET is formed.
摘要翻译：提高半导体器件的可靠性在一个半导体芯片CPH和半导体芯片CPH内形成用于开关的功率MOSFET和具有小于功率MOSFET的功率MOSFET并且被配置为检测流过功率MOSFET的电流的感测MOSFET 通过导电接合材料安装在芯片安装部分上并用树脂密封。在半导体芯片CPH的主表面中，形成感测MOSFET的感测MOSFET区域位于读出MOSFET区域RG2的源极焊盘PDHS4的内部。此外，在半导体芯片的主表面中，感测MOSFET区域RG2由形成功率MOSFET的区域包围。

3. 发明授权

US09418986B2 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US09418986B2
公开(公告)日：2016-08-16
申请号：US13589160
申请日：2012-08-19
申请人： Tomoaki Uno , Yoshitaka Onaya , Hirokazu Kato , Ryotaro Kudo , Koji Saikusa
发明人： Tomoaki Uno , Yoshitaka Onaya , Hirokazu Kato , Ryotaro Kudo , Koji Saikusa
IPC分类号： H01L27/088 , H01L23/495 , H01L25/16 , H02M1/32 , H02M3/156 , H01L21/8234 , H01L23/00 , H01L25/07 , H02M1/00
CPC分类号： H01L27/088 , H01L21/823487 , H01L23/49524 , H01L23/49562 , H01L23/49575 , H01L24/37 , H01L24/40 , H01L24/73 , H01L25/074 , H01L25/16 , H01L2224/05554 , H01L2224/0603 , H01L2224/32245 , H01L2224/37011 , H01L2224/371 , H01L2224/37124 , H01L2224/37147 , H01L2224/3754 , H01L2224/40095 , H01L2224/40245 , H01L2224/48091 , H01L2224/48137 , H01L2224/48247 , H01L2224/73221 , H01L2224/73265 , H01L2224/8385 , H01L2224/84801 , H01L2224/8485 , H01L2924/13091 , H01L2924/181 , H01L2924/30107 , H02M1/32 , H02M3/156 , H02M2001/0009 , H01L2924/00012 , H01L2924/00 , H01L2924/00014
摘要： A semiconductor device is improved in reliability. A power MOSFET for switching, and a sense MOSFET for sensing a current flowing in the power MOSFET, which is smaller in area than the power MOSFET, are formed in one semiconductor chip. The semiconductor chip is mounted over a chip mounting portion, and sealed in a resin. To first and second source pads for outputting the current flowing in the power MOSFET, a metal plate is bonded. A third source pad for sensing the source voltage of the power MOSFET is at a position not overlapping the metal plate. A coupled portion between a source wire forming the third pad and another source wire forming the first and second pads is at a position overlapping the metal plate.
摘要翻译：提高了半导体器件的可靠性。在一个半导体芯片中形成用于切换的功率MOSFET和用于感测功率MOSFET中流过的电流的感测MOSFET，该功率MOSFET的面积小于功率MOSFET。半导体芯片安装在芯片安装部分上，并密封在树脂中。对于用于输出在功率MOSFET中流动的电流的第一和第二源极焊盘，金属板被接合。用于感测功率MOSFET的源极电压的第三源极焊盘位于与金属板不重叠的位置。形成第三焊盘的源极线和形成第一和第二焊盘的另一源极之间的耦合部分处于与金属板重叠的位置。

4. 发明授权

US09000497B2 Trench MOSFET having an independent coupled element in a trench 有权
标题翻译：沟槽MOSFET在沟槽中具有独立的耦合元件
公开(公告)号：US09000497B2
公开(公告)日：2015-04-07
申请号：US13617744
申请日：2012-09-14
申请人： Tetsuo Sato , Tomoaki Uno , Hirokazu Kato , Nobuyoshi Matsuura
发明人： Tetsuo Sato , Tomoaki Uno , Hirokazu Kato , Nobuyoshi Matsuura
IPC分类号： H01L29/76 , H01L23/58 , H01L21/70 , H01L23/34 , H03K17/16 , H01L29/40 , H01L29/78 , H01L29/417 , H02M1/44 , H03K17/687
CPC分类号： H02M3/158 , H01L27/0629 , H01L28/10 , H01L29/407 , H01L29/41766 , H01L29/42336 , H01L29/4916 , H01L29/7803 , H01L29/7813 , H02M1/08 , H02M1/44 , H03K7/08 , H03K17/162 , H03K17/165 , H03K2017/6878 , H03K2217/0036
摘要： A trench MOSFET is disclosed that includes a semiconductor substrate having a vertically oriented trench containing a gate. The trench MOSFET further includes a source, a drain, and a conductive element. The conductive element, like the gate is contained in the trench, and extends between the gate and a bottom of the trench. The conductive element is electrically isolated from the source, the gate, and the drain. When employed in a device such as a DC-DC converter, the trench MOSFET may reduce power losses and electrical and electromagnetic noise.
摘要翻译：公开了一种沟槽MOSFET，其包括具有包含栅极的垂直取向沟槽的半导体衬底。沟槽MOSFET还包括源极，漏极和导电元件。导电元件像栅极一样被包含在沟槽中，并且在栅极和沟槽的底部之间延伸。导电元件与源极，栅极和漏极电隔离。当用于诸如DC-DC转换器的器件中时，沟槽MOSFET可以减少功率损耗和电和电磁噪声。

5. 发明申请

US20160351702A1 SEMICONDUCTOR DEVICE 有权
标题翻译：半导体器件
公开(公告)号：US20160351702A1
公开(公告)日：2016-12-01
申请号：US14406991
申请日：2014-01-31
申请人： Hideo Numabe , Nobuyuki Shirai , Hirokazu Kato , Tomoaki Uno , Kazuyuki Umezu
发明人： Hideo Numabe , Nobuyuki Shirai , Hirokazu Kato , Tomoaki Uno , Kazuyuki Umezu
IPC分类号： H01L29/78 , H01L29/40 , H01L29/06 , H01L29/10 , H01L23/535 , H01L29/417 , H01L29/423 , H01L29/08
CPC分类号： H01L29/7813 , H01L23/535 , H01L29/0696 , H01L29/0865 , H01L29/0882 , H01L29/1033 , H01L29/407 , H01L29/41741 , H01L29/4236 , H01L2224/05554 , H01L2224/0603 , H01L2224/371 , H01L2224/37124 , H01L2224/37147 , H01L2224/40245 , H01L2224/45144 , H01L2224/48137 , H01L2224/48247 , H01L2224/49171 , H01L2924/181 , H01L2924/00012 , H01L2924/00
摘要： A control electrode GE1 is formed in a lower portion of a trench TR1 formed in a semiconductor substrate SUB, and a gate electrode GE2 is formed in an upper portion inside the trench TR1. An insulating film G1 is formed between the control electrode GE1 and a side wall and a bottom surface of the trench TR1, an insulating film G2 is formed between the side wall of the trench TR1 and the gate electrode GE2, and an insulating film G3 is formed between the control electrode GE1 and the gate electrode GE2. A region adjacent to the trench TR1 includes an n+-type semiconductor region NR for a source, a p-type semiconductor region PR for a channel formation, and a semiconductor region for a drain. A wiring connected to the control electrode GE1 is not connected to a wiring connected to the gate electrode GE2, and is not connected to a wiring connected to the n+-type semiconductor region NR for a source.
摘要翻译：控制电极GE1形成在形成在半导体衬底SUB中的沟槽TR1的下部，栅电极GE2形成在沟槽TR1内部的上部。在控制电极GE1与沟槽TR1的侧壁和底面之间形成绝缘膜G1，在沟槽TR1的侧壁与栅电极GE2之间形成绝缘膜G2，绝缘膜G3为形成在控制电极GE1和栅电极GE2之间。与沟槽TR1相邻的区域包括用于源极的n +型半导体区域NR，用于沟道形成的p型半导体区域PR和用于漏极的半导体区域。连接到控制电极GE1的布线不连接到与栅电极GE2连接的布线，并且不连接到与源的n +型半导体区域NR连接的布线。

6. 发明申请

US20140077778A1 TRENCH MOSFET HAVING AN INDEPENDENT COUPLED ELEMENT IN A TRENCH 有权
标题翻译：在TRENCH中具有独立耦合元件的TRENCH MOSFET
公开(公告)号：US20140077778A1
公开(公告)日：2014-03-20
申请号：US13617744
申请日：2012-09-14
申请人： Tetsuo Sato , Tomoaki Uno , Hirokazu Kato , Nobuyoshi Matsuura
发明人： Tetsuo Sato , Tomoaki Uno , Hirokazu Kato , Nobuyoshi Matsuura
IPC分类号： H01L29/78 , G05F1/00
CPC分类号： H02M3/158 , H01L27/0629 , H01L28/10 , H01L29/407 , H01L29/41766 , H01L29/42336 , H01L29/4916 , H01L29/7803 , H01L29/7813 , H02M1/08 , H02M1/44 , H03K7/08 , H03K17/162 , H03K17/165 , H03K2017/6878 , H03K2217/0036
摘要： A trench MOSFET is disclosed that includes a semiconductor substrate having a vertically oriented trench containing a gate. The trench MOSFET further includes a source, a drain, and a conductive element. The conductive element, like the gate is contained in the trench, and extends between the gate and a bottom of the trench. The conductive element is electrically isolated from the source, the gate, and the drain. When employed in a device such as a DC-DC converter, the trench MOSFET may reduce power losses and electrical and electromagnetic noise.
摘要翻译：公开了一种沟槽MOSFET，其包括具有包含栅极的垂直取向沟槽的半导体衬底。沟槽MOSFET还包括源极，漏极和导电元件。导电元件像栅极一样被包含在沟槽中，并且在栅极和沟槽的底部之间延伸。导电元件与源极，栅极和漏极电隔离。当用于诸如DC-DC转换器的器件中时，沟槽MOSFET可以减少功率损耗和电和电磁噪声。

7. 发明授权

US09789875B2 Brake/drive force controlling apparatus for vehicle 有权
公开(公告)号：US09789875B2
公开(公告)日：2017-10-17
申请号：US12676235
申请日：2008-09-03
申请人： Yoji Mizoguchi , Koji Taguchi , Hirokazu Kato
发明人： Yoji Mizoguchi , Koji Taguchi , Hirokazu Kato
IPC分类号： B60W30/18 , B60W10/184 , B60W10/06 , B60W10/16 , B60K23/04 , B60T8/1755
CPC分类号： B60W30/18109 , B60K23/04 , B60T8/1755 , B60T2201/14 , B60T2260/08 , B60W10/06 , B60W10/16 , B60W10/184 , B60W2520/14 , B60W2540/12
摘要： A brake/drive force controlling apparatus for a vehicle includes an engine for applying drive forces to driving wheels of the vehicles, a control diff for distributing the drive forces to the left and right driving wheels independently, and an electronic control system brake device for applying brake forces to the left and right driving wheels independently. An ECU is configured so as to be able to control the engine, the control diff, and the electronic control system brake device according to an operating state of the vehicle. When the electronic control system brake device is operated, this ECU stops the operation of the control diff, thereby avoiding a sudden input of load on the drive force distribution mechanism, regardless of the running state of the vehicle. This makes the apparatus simpler and more lightweight.

8. 发明授权

US08614144B2 Method for fabrication of interconnect structure with improved alignment for semiconductor devices 失效
标题翻译：用于制造具有改进的半导体器件对准的互连结构的方法
公开(公告)号：US08614144B2
公开(公告)日：2013-12-24
申请号：US13157744
申请日：2011-06-10
申请人： Hirokazu Kato
发明人： Hirokazu Kato
IPC分类号： H01L21/31 , H01L21/469
CPC分类号： H01L21/76811 , H01L21/31144 , H01L21/76813 , H01L21/76816
摘要： Methods and structure are provided for creating and utilizing hard masks to facilitate creation of a grating effect to control an anisotropic etching process for the creation of an opening, and subsequent formation of a interconnect structure (e.g., a via) in a multilayered semiconductor device. A first hard mask can be patterned to control etching in a first dimension, and a second hard mask can be patterned to control etching in a second dimension, wherein the second hard mask is patterned orthogonally opposed to the first hard mask. A resist can be patterned by inverting the pattern of a metal line patterning. Interconnects can be formed with critical dimension(s) and also self-aligned.
摘要翻译：提供了用于创建和利用硬掩模的方法和结构，以便于创建光栅效应以控制用于产生开口的各向异性蚀刻工艺，以及随后在多层半导体器件中形成互连结构（例如通孔）。可以对第一硬掩模进行图案化以控制第一维度的蚀刻，并且可以对第二硬掩模进行图案化以控制第二维度中的蚀刻，其中第二硬掩模被图案与第一硬掩模垂直相对。通过反转金属线图案的图案可以对抗蚀剂进行图案化。互连可以形成临界尺寸，也可以自对准。

9. 发明授权

US08391589B2 Information processing apparatus and method for calculating the position and orientation of an image sensing device 有权
标题翻译：用于计算图像感测装置的位置和取向的信息处理装置和方法
公开(公告)号：US08391589B2
公开(公告)日：2013-03-05
申请号：US12013123
申请日：2008-01-11
申请人： Daisuke Kotake , Shinji Uchiyama , Hirokazu Kato
发明人： Daisuke Kotake , Shinji Uchiyama , Hirokazu Kato
IPC分类号： G06K9/00
CPC分类号： G01C11/00 , G01S5/16 , G06T7/20 , G06T7/73
摘要： Three pieces of candidate position information are calculated based on a plurality of pieces of sensing position information, and three pieces of candidate orientation information are calculated based on a plurality of pieces of sensing orientation information. Sets each of which combines one candidate position information and one candidate orientation information are prepared for all combinations. For each set, the candidate position information and candidate orientation information which configure that set are corrected. An evaluation value is calculated for each corrected set, and one of the sets is selected based on the calculated evaluation values. The candidate position information and candidate orientation information which configure the selected set are respectively recorded in a memory as sensing position information and sensing orientation information.
摘要翻译：基于多条感测位置信息计算三条候选位置信息，并且基于多条感测取向信息来计算三条候选方向信息。对于所有组合，为每个组合一个候选位置信息和一个候选方向信息。对于每个集合，配置该组的候选位置信息和候选方向信息被校正。针对每个校正组计算评估值，并且基于所计算的评估值来选择一组。配置所选择的集合的候选位置信息和候选方向信息分别作为感测位置信息和感测取向信息记录在存储器中。

10. 发明申请

US20110274767A1 PRODUCTION METHOD OF TITANIUM OXIDE SOL 有权
标题翻译：氧化钛溶胶的生产方法
公开(公告)号：US20110274767A1
公开(公告)日：2011-11-10
申请号：US13128496
申请日：2009-10-27
申请人： Hirokazu Kato , Natsumi Tsuihiji
发明人： Hirokazu Kato , Natsumi Tsuihiji
IPC分类号： A01N59/16 , B01J21/06 , H01B1/02 , A01P1/00
CPC分类号： B01J13/0047 , C01G23/053 , C01P2002/70 , C09C1/3669
摘要： There is provided a method for efficiently producing an anatase-type titanium oxide sol in an extremely advantageous dispersion state. The method comprises mixing a titanium alkoxide, an organic acid, and a quaternary ammonium hydroxide with water in a molar ratio of the organic acid of 0.4 to 4.0 relative to 1 mol of a titanium atom of the titanium alkoxide and in a molar ratio of the quaternary ammonium hydroxide of 0.8 to 1.9 relative to 1 mol of the organic acid to prepare an aqueous mixed solution having a concentration in terms of TiO2 of 0.5 to 10% by mass; heating the aqueous mixed solution to 50 to 100° C. to remove an alcohol; and subjecting the resulting titanium-containing aqueous solution to a hydrothermal treatment at 110 to 170° C.
摘要翻译：提供了一种在非常有利的分散状态下有效地生产锐钛矿型氧化钛溶胶的方法。该方法包括使钛醇盐，有机酸和季铵氢氧化物与水相比，相对于1摩尔钛醇钛的钛原子，有机酸的摩尔比为0.4-4.0摩尔比，相对于1摩尔有机酸为0.8〜1.9的季铵氢氧化物，以制备TiO 2浓度为0.5〜10质量％的水性混合溶液; 将含水混合溶液加热至50至100℃以除去醇; 并将所得含钛水溶液在110〜170℃进行水热处理。

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