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1. 发明申请

US20090063888A1 METHOD AND APPARATUS FOR CLOCK CYCLE STEALING 有权
标题翻译：用于时钟循环的方法和装置
公开(公告)号：US20090063888A1
公开(公告)日：2009-03-05
申请号：US11841179
申请日：2007-08-31
申请人： Spencer M. Gold , Bill K.C. Kwan , Craig D. Eaton
发明人： Spencer M. Gold , Bill K.C. Kwan , Craig D. Eaton
IPC分类号： G06F1/06
CPC分类号： G06F1/06 , G06F1/08
摘要： A method for producing a plurality of clock signals. The method includes generating a reference clock signal using a phase locked loop (PLL). The reference clock signal is then provided to each of a plurality of clock divider units which each divide the received reference clock signal to produce a corresponding divided clock signal. The method then removes one or more clock cycles (per a given number of cycles) in order to produce a plurality of domain clock signals each having an effective frequency based on a frequency and a number of cycles removed from the correspondingly received divided clock signal.
摘要翻译：一种用于产生多个时钟信号的方法。该方法包括使用锁相环（PLL）产生参考时钟信号。然后将参考时钟信号提供给多个时钟分频器单元中的每一个，每个时钟分频器单元分别接收到的参考时钟信号以产生相应的分频时钟信号。该方法然后去除一个或多个时钟周期（每给定数量的周期），以便产生多个域时钟信号，每个域时钟信号基于从对应接收到的分频时钟信号中去除的频率和数目的周期而具有有效频率。

2. 发明授权

US07913103B2 Method and apparatus for clock cycle stealing 有权
标题翻译：时钟周期窃取的方法和装置
公开(公告)号：US07913103B2
公开(公告)日：2011-03-22
申请号：US11841179
申请日：2007-08-31
申请人： Spencer M. Gold , Bill K. C. Kwan , Craig D. Eaton
发明人： Spencer M. Gold , Bill K. C. Kwan , Craig D. Eaton
IPC分类号： G06K1/00 , H03K3/017
CPC分类号： G06F1/06 , G06F1/08
摘要： A method for producing a plurality of clock signals. The method includes generating a reference clock signal using a phase locked loop (PLL). The reference clock signal is then provided to each of a plurality of clock divider units which each divide the received reference clock signal to produce a corresponding divided clock signal. The method then removes one or more clock cycles (per a given number of cycles) in order to produce a plurality of domain clock signals each having an effective frequency based on a frequency and a number of cycles removed from the correspondingly received divided clock signal.
摘要翻译：一种用于产生多个时钟信号的方法。该方法包括使用锁相环（PLL）产生参考时钟信号。然后将参考时钟信号提供给多个时钟分频器单元中的每一个，每个时钟分频器单元分别接收到的参考时钟信号以产生相应的分频时钟信号。该方法然后去除一个或多个时钟周期（每给定数量的周期），以便产生多个域时钟信号，每个域时钟信号基于从对应接收到的分频时钟信号中去除的频率和数目的周期而具有有效频率。

3. 发明授权

US08914687B2 Providing test coverage of integrated ECC logic en embedded memory 有权
标题翻译：提供嵌入式内存的集成ECC逻辑的测试覆盖
公开(公告)号：US08914687B2
公开(公告)日：2014-12-16
申请号：US13087808
申请日：2011-04-15
申请人： Spencer M. Gold , Arun B. Hegde
发明人： Spencer M. Gold , Arun B. Hegde
IPC分类号： G11C29/00 , G06F11/10 , G11C29/02 , G06F11/22 , G11C29/04
CPC分类号： G06F11/2215 , G06F11/1052 , G06F2217/70 , G11C29/02 , G11C2029/0411
摘要： A method is provided in which a first error test may be performed on a memory that includes an integrated error correcting code (ECC) portion. The functionality of the ECC portion may be bypassed in the first error test. A second error test may be performed on the memory, where the second error test includes testing the functionality of the ECC portion. Also provided is an apparatus including a memory device and an error correcting code (ECC) circuit. The apparatus also includes a first switching device adapted to select a first input signal or a second input signal and a second switching device adapted to select one of a signal from the memory device or a signal from a portion of the ECC circuit. Also provided are computer readable storage devices encoded with data for adapting a manufacturing facility to create the apparatus and for adapting a processor to perform the method above.
摘要翻译：提供了一种方法，其中可以对包括集成纠错码（ECC）部分的存储器执行第一错误测试。在第一个错误测试中可以绕过ECC部分的功能。可以对存储器执行第二错误测试，其中第二错误测试包括测试ECC部分的功能。还提供了一种包括存储器件和纠错码（ECC）电路的装置。该装置还包括适于选择第一输入信号或第二输入信号的第一开关装置和适于从存储装置选择信号之一或来自ECC电路的一部分的信号的第二开关装置。还提供了用数据编码的计算机可读存储设备，用于使制造设施适配以创建设备并使调适处理器执行上述方法。

4. 发明申请

US20090235108A1 AUTOMATIC PROCESSOR OVERCLOCKING 审中-公开
标题翻译：自动处理器过载
公开(公告)号：US20090235108A1
公开(公告)日：2009-09-17
申请号：US12045916
申请日：2008-03-11
申请人： Spencer M. Gold , Alex Branover , Hanwoo Cho , Sebastien Nussbaum
发明人： Spencer M. Gold , Alex Branover , Hanwoo Cho , Sebastien Nussbaum
IPC分类号： G06F1/00
CPC分类号： G06F1/206 , G06F1/3203 , G06F1/324 , Y02D10/126
摘要： Processor overclocking techniques are disclosed. Upon automatically determining that overclocking entry criteria are satisfied, one or more cores are clocked above their standard operation frequencies. The cores may be overclocked until one or more exit criteria are satisfied. At that point, an exit procedure is performed, with the one or more overclocked cores return to their normal operating frequency.
摘要翻译：处理器超频技术被公开。当自动确定超频进入条件得到满足时，一个或多个核心的时钟频率超过其标准工作频率。核心可以超频，直到满足一个或多个退出标准。此时，执行一个退出程序，一个或多个超频核心恢复到正常工作频率。

5. 发明授权

US09047981B2 Bit-flipping in memories 有权
标题翻译：记忆中的位翻转
公开(公告)号：US09047981B2
公开(公告)日：2015-06-02
申请号：US13724924
申请日：2012-12-21
申请人： Arun B. Hegde , Spencer M. Gold , Thomas E. Ryan
发明人： Arun B. Hegde , Spencer M. Gold , Thomas E. Ryan
IPC分类号： G11C7/04 , G11C11/419
CPC分类号： G11C11/419 , G11C7/04 , G11C11/417
摘要： Data stored in SRAM cells are periodically flipped e.g., before long idle periods. Operating the memories in both a ‘flipped’ mode and a ‘non-flipped’ mode helps cause the Bias Temperature Instability (BTI) degradation to be symmetric, thereby not degrading the Static Noise Margin (SNM) degradation of the cells. The data stored in memory locations is flipped by reading out the data, inverting the read out data, and writing the inverted read out data into the memory locations until the memory locations of the SRAM have been read out and written. When the memory operates in flipped mode, data read from and written into the memory is inverted to maintain transparency to the memory user. After operating the data in flipped mode for a period of time, the flipped data stored in the memory is reflipped to operate in the non-flipped mode.
摘要翻译：存储在SRAM单元中的数据例如在长时间的空闲周期之前被周期性翻转。以“翻转”模式和“非翻转”模式操作存储器有助于使偏置温度不稳定（BTI）劣化成对称，从而不会降低单元的静态噪声余量（SNM）降级。存储在存储单元中的数据通过读出数据，反转读出数据以及将反相读出数据写入到存储器位置来翻转，直到SRAM的存储器位置被读出和写入。当存储器以翻转模式操作时，从存储器读取和写入存储器的数据被反转以保持对存储器用户的透明度。在经过一段时间的翻转模式下操作数据之后，将存储在存储器中的翻转数据重新提供以非翻转模式操作。

6. 发明授权

US07191315B2 Method and system for tracking and recycling physical register assignment 有权
标题翻译：跟踪和回收物理寄存器分配的方法和系统
公开(公告)号：US07191315B2
公开(公告)日：2007-03-13
申请号：US09874173
申请日：2001-06-04
申请人： Spencer M. Gold , Julie M. Staraitis , Masooma Bhiawala
发明人： Spencer M. Gold , Julie M. Staraitis , Masooma Bhiawala
IPC分类号： G06F9/00
CPC分类号： G06F9/30098
摘要： The present invention provides methods and memory structures for efficient tracking and recycling of physical register assignments. The disclosed methods and memory structures each provide an approach to reduce the size of the memory structures needed to track the usage of the physical registers and the recycling of these registers.
摘要翻译：本发明提供用于有效跟踪和回收物理寄存器分配的方法和存储器结构。所公开的方法和存储结构各自提供了减少跟踪物理寄存器的使用所需的存储器结构的大小以及这些寄存器的再循环的方法。

7. 发明授权

US06959377B2 Method and system for managing registers 有权
标题翻译：管理寄存器的方法和系统
公开(公告)号：US06959377B2
公开(公告)日：2005-10-25
申请号：US10103181
申请日：2002-03-20
申请人： Spencer M. Gold , Masooma Bhiawala
发明人： Spencer M. Gold , Masooma Bhiawala
IPC分类号： G06F9/30 , G06F9/38 , G06F9/40
CPC分类号： G06F9/384 , G06F9/3836 , G06F9/3855 , G06F9/3857
摘要： A system and method for memory structures for efficient tracking and recycling of physical register assignments are disclosed. The method and system provide the necessary functionality to allow the number of physical registers assigned to incoming instructions to equal the number of physical registers that are returned to the list of free registers each cycle, thereby maintaining a substantially constant number of physical register pointers in the list of free registers. The system and method reduce the size of the memory structures utilized to track the usage of physical registers and the recycling of these registers.
摘要翻译：公开了一种用于有效跟踪和回收物理寄存器分配的存储器结构的系统和方法。该方法和系统提供了必要的功能，以允许分配给输入指令的物理寄存器的数量等于每个周期返回到空闲寄存器列表的物理寄存器的数量，从而保持在免费寄存器列表。该系统和方法减小了用于跟踪物理寄存器的使用和这些寄存器的回收的存储器结构的大小。

8. 发明授权

US06560140B2 Single ended two-stage memory cell 有权
公开(公告)号：US06560140B2
公开(公告)日：2003-05-06
申请号：US09852427
申请日：2001-05-09
申请人： Spencer M. Gold , Julie Staraitis
发明人： Spencer M. Gold , Julie Staraitis
IPC分类号： G11C700
CPC分类号： G11C15/00 , G11C11/005 , G11C11/41
摘要： The present invention provides a memory array having an array structure that has at least one memory cell, including a word write bit line and a single transfer line. The memory array is also provided with a two-stage memory cell having a speculative storage node, a non-speculative storage node, and a circuit. The two-stage memory cell is electrically coupled to the array structure. Activation of the circuit causes a speculative data value stored in the speculative storage node to be written to the non-speculative storage node.

9. 发明申请

US20120266033A1 PROVIDING TEST COVERAGE OF INTEGRATED ECC LOGIC EN EMBEDDED MEMORY 有权
标题翻译：提供集成ECC逻辑嵌入式存储器的测试覆盖
公开(公告)号：US20120266033A1
公开(公告)日：2012-10-18
申请号：US13087808
申请日：2011-04-15
申请人： Spencer M. Gold , Arun B. Hegde
发明人： Spencer M. Gold , Arun B. Hegde
IPC分类号： G06F11/00 , G06F17/50
CPC分类号： G06F11/2215 , G06F11/1052 , G06F2217/70 , G11C29/02 , G11C2029/0411
摘要： A method is provided in which a first error test may be performed on a memory that includes an integrated error correcting code (ECC) portion. The functionality of the ECC portion may be bypassed in the first error test. A second error test may be performed on the memory, where the second error test includes testing the functionality of the ECC portion. Also provided is an apparatus including a memory device and an error correcting code (ECC) circuit. The apparatus also includes a first switching device adapted to select a first input signal or a second input signal and a second switching device adapted to select one of a signal from the memory device or a signal from a portion of the ECC circuit. Also provided are computer readable storage devices encoded with data for adapting a manufacturing facility to create the apparatus and for adapting a processor to perform the method above.
摘要翻译：提供了一种方法，其中可以对包括集成纠错码（ECC）部分的存储器执行第一错误测试。在第一个错误测试中可以绕过ECC部分的功能。可以对存储器执行第二错误测试，其中第二错误测试包括测试ECC部分的功能。还提供了一种包括存储器件和纠错码（ECC）电路的装置。该装置还包括适于选择第一输入信号或第二输入信号的第一开关装置和适于从存储装置选择信号之一或来自ECC电路的一部分的信号的第二开关装置。还提供了用数据编码的计算机可读存储设备，用于使制造设施适配以创建设备并使调适处理器执行上述方法。

10. 发明申请

US20100237924A1 DIGITAL FREQUENCY SYNTHESIZER DEVICE AND METHOD THEREOF 有权
标题翻译：数字频率合成器件及其方法
公开(公告)号：US20100237924A1
公开(公告)日：2010-09-23
申请号：US12409228
申请日：2009-03-23
申请人： Richard W. Reeves , Spencer M. Gold , Steven J. Kommrusch , Anwar P. Kashem
发明人： Richard W. Reeves , Spencer M. Gold , Steven J. Kommrusch , Anwar P. Kashem
IPC分类号： G06F1/04
CPC分类号： G06F1/3203 , G06F1/08 , G06F1/324 , Y02D10/126
摘要： A first plurality of clock signals including a first clock signal and a second clock signal is received, the first and second clock signal out of phase with each other. A second plurality of clock signals comprising a third clock signal and a fourth clock signal is received, the third and fourth clock signals out of phase with each other. A plurality of enable signals are received. A fifth clock signal is determined based on the first plurality of clock signals and the plurality of enable signals. A sixth clock signal is determined based on the second plurality of clock signals and the plurality of enable signals. A seventh clock signal is determined based on the fifth clock signal and the sixth clock signal.
摘要翻译：接收包括第一时钟信号和第二时钟信号的第一多个时钟信号，第一和第二时钟信号彼此异相。接收包括第三时钟信号和第四时钟信号的第二多个时钟信号，第三和第四时钟信号彼此不同相。接收多个使能信号。基于第一多个时钟信号和多个使能信号来确定第五时钟信号。基于第二多个时钟信号和多个使能信号来确定第六时钟信号。基于第五时钟信号和第六时钟信号确定第七时钟信号。

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