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1. 发明授权

US06265298B1 Method for forming inter-metal dielectrics 失效
标题翻译：形成金属间电介质的方法
公开(公告)号：US06265298B1
公开(公告)日：2001-07-24
申请号：US09249882
申请日：1999-02-16
申请人： Shuenn-Jeng Chen , Ching-Hsing Hsieh , Chih-Ching Hsu
发明人： Shuenn-Jeng Chen , Ching-Hsing Hsieh , Chih-Ching Hsu
IPC分类号： H01L2144
CPC分类号： H01L21/76829 , H01L21/76819 , H01L21/76826
摘要： An improved method for forming inter-metal dielectrics (IMD) over a semiconductor substrate is provided, wherein a conductive line is formed thereon. A first dielectric layer is formed over the conductive line. A second dielectric layer is formed on the first dielectric layer by a spin-on glass method. A curing treatment with an electron beam having a low energy and a high dosage is performed to cure an upper portion of the second dielectric layer so that a cured third dielectric layer is formed on the second dielectric layer. A fourth dielectric layer is formed on the cured third dielectric layer. A chemical-mechanical polishing process is performed using the cured dielectric layer as a stop layer. A cap layer is formed on the fourth dielectric layer.
摘要翻译：提供了一种用于在半导体衬底上形成金属间电介质（IMD）的改进方法，其中在其上形成导电线。在导电线上形成第一介电层。通过旋涂玻璃法在第一介电层上形成第二介电层。执行具有低能量和高剂量的电子束的固化处理以固化第二介电层的上部，使得固化的第三介电层形成在第二介电层上。在固化的第三电介质层上形成第四电介质层。使用固化的电介质层作为停止层进行化学机械抛光工艺。在第四电介质层上形成覆盖层。

2. 发明授权

US06277755B1 Method for fabricating an interconnect 失效
标题翻译：制造互连的方法
公开(公告)号：US06277755B1
公开(公告)日：2001-08-21
申请号：US09466686
申请日：1999-12-20
申请人： Shuenn-Jeng Chen , Chih-Ching Hsu
发明人： Shuenn-Jeng Chen , Chih-Ching Hsu
IPC分类号： H01L21303
CPC分类号： H01L21/76829 , H01L21/76807 , H01L21/76822
摘要： A method for fabricating an interconnect structure by a dual damascene process is described, in which a first low dielectric constant material is formed on a substrate, followed by forming a gradient silicon oxy-nitride layer on the first low dielectric constant. A second low dielectric constant layer is further formed on the gradient silicon oxy-nitride layer. A trench line is then formed in the second low dielectric constant material using the gradient silicon oxy-nitride layer as an etch-stop, followed by forming a via under the trench line.
摘要翻译：描述了通过双镶嵌工艺制造互连结构的方法，其中在衬底上形成第一低介电常数材料，随后在第一低介电常数上形成梯度硅氮化物层。在梯度硅氮化物层上进一步形成第二低介电常数层。然后在第二低介电常数材料中使用梯度硅氧氮化物层作为蚀刻停止层形成沟槽线，随后在沟槽线下形成通孔。

3. 发明授权

US6074941A Method of forming a via with plasma treatment of SOG 失效
标题翻译：通过等离子体处理SOG形成通孔的方法
公开(公告)号：US6074941A
公开(公告)日：2000-06-13
申请号：US113471
申请日：1998-07-10
申请人： Ching-Hsing Hsieh , William Lu , Chih-Ching Hsu , Yung-Chieh Kuo
发明人： Ching-Hsing Hsieh , William Lu , Chih-Ching Hsu , Yung-Chieh Kuo
IPC分类号： H01L21/3105 , H01L21/316 , H01L21/768 , H01L21/4763
CPC分类号： H01L21/316 , H01L21/3105 , H01L21/76814
摘要： A method of forming a via is provided comprising a plasma treatment at the spin-on-glass layer after forming the unlanding via. The plasma comprises hydrogen and a second gas. The mist containing in the spin-on-glass layer is damaged and removed away.
摘要翻译：提供了一种形成通孔的方法，其包括在形成无引导孔之后在旋涂玻璃层处进行等离子体处理。等离子体包括氢气和第二气体。包含在旋涂玻璃层中的雾被损坏并被去除。

4. 发明授权

US06277754B1 Method of planarizing dielectric layer 失效
标题翻译：平面化电介质层的方法
公开(公告)号：US06277754B1
公开(公告)日：2001-08-21
申请号：US09067548
申请日：1998-04-27
申请人： Brian Wang , Chih-Ching Hsu
发明人： Brian Wang , Chih-Ching Hsu
IPC分类号： H01L21311
CPC分类号： H01L21/02362 , H01L21/02129 , H01L21/02271 , H01L21/02274 , H01L21/31051 , H01L21/31055 , H01L21/31612 , H01L21/31625 , Y10S438/958
摘要： A method of planarizing a dielectric layer comprising the steps of providing a substrate having structures already formed thereon, and then forming a borophosphosilicate glass layer over the substrate. Next, a rapid thermal process is applied heating the borophosphosilicate layer to cause a thermal flow, and then the borophosphosilicate layer is etched back so that a planar surface is obtained. Finally, a passivation layer is formed over the borophosphosilicate glass layer to prevent the formation of pits in subsequent pre-metal wet etching operations.
摘要翻译：一种平面化电介质层的方法，包括以下步骤：提供其上已经形成结构的衬底，然后在衬底上形成硼磷硅玻璃层。接下来，施加快速热处理，加热硼磷硅酸盐层引起热流，然后将硼磷硅酸盐层回蚀，从而获得平坦的表面。最后，在硼磷硅酸盐玻璃层之上形成钝化层，以防止在后续的金属前湿法蚀刻操作中形成凹坑。

5. 发明授权

US07837511B2 Electrical connector having improved connecting module 有权
标题翻译：电连接器具有改进的连接模块
公开(公告)号：US07837511B2
公开(公告)日：2010-11-23
申请号：US12321710
申请日：2009-01-22
申请人： Chih-Ching Hsu
发明人： Chih-Ching Hsu
IPC分类号： H01R24/04
CPC分类号： H01R13/6658 , H01R13/7175 , H01R24/64
摘要： An electrical connector (100) includes an insulative element (1) and an electrical unit (2) mounted to the insluative element. The electrical unit includes a housing (21), a terminal module (23) assembled to the housing, at least a daughter board (25) mounted to a side portion of the housing, and a connecting module (27). The connecting module has a base (271), a number of first pins (273) assembled to the base and extending through the daughter board, and at least a contacting subassembly (272) mounted to the base and having a number of second pins (277) connected to the daughter board.
摘要翻译：电连接器（100）包括绝缘元件（1）和安装在所述绝缘元件上的电单元（2）。电气单元包括壳体（21），组装到壳体的端子模块（23），安装到壳体的侧部的至少一个子板（25）和连接模块（27）。连接模块具有底座（271），多个第一销（273）组装到底座并延伸通过子板，以及至少一个安装到基座上的接触子组件（272），并具有多个第二销（ 277）连接到子板。

6. 发明授权

US06184115B2 Method of fabricating self-aligned silicide 失效
标题翻译：制造自对准硅化物的方法
公开(公告)号：US06184115B2
公开(公告)日：2001-02-06
申请号：US09250618
申请日：1999-02-16
申请人： Hung-Yu Kou , Chih-Ching Hsu
发明人： Hung-Yu Kou , Chih-Ching Hsu
IPC分类号： H01L213205
CPC分类号： H01L29/66507 , H01L21/28518
摘要： The present invention is directed towards a method of fabricating a self-aligned silicide on gate electrode and source/drain region of a semiconductor device. A semiconductor substrate having gate oxide layer and polysilicon layer is provided. Next, a first silicide layer is formed on polysilicon layer. The substrate is patterned and then, etched to form a gate structure. A spacer is formed on the sidewall of the gate structure and source/drain region is formed adjacent thereto. A metal layer is covered on the surface of the substrate. The substrate is performed a thermal process to convert the portion of the metal layer on gate structure and source/drain region into self-aligned silicide.
摘要翻译：本发明涉及在半导体器件的栅电极和源/漏区上制造自对准硅化物的方法。提供具有栅氧化层和多晶硅层的半导体衬底。接下来，在多晶硅层上形成第一硅化物层。将衬底图案化，然后蚀刻以形成栅极结构。在栅极结构的侧壁上形成间隔物，并且与其相邻地形成源极/漏极区。金属层被覆盖在基板的表面上。进行基板的热处理以将栅极结构和源极/漏极区域上的金属层的部分转换成自对准硅化物。

7. 发明授权

US5998286A Method to grow self-aligned silicon on a poly-gate, source and drain region 失效
标题翻译：在多晶硅，源极和漏极区域生长自对准硅的方法
公开(公告)号：US5998286A
公开(公告)日：1999-12-07
申请号：US48924
申请日：1998-03-26
申请人： Shu-Jen Chen , Jacky Kuo , Jiunn-Hsien Lin , Chih-Ching Hsu
发明人： Shu-Jen Chen , Jacky Kuo , Jiunn-Hsien Lin , Chih-Ching Hsu
IPC分类号： H01L21/28 , H01L21/285 , H01L21/336 , H01L29/417 , H01L21/283
CPC分类号： H01L29/665 , H01L21/28052 , H01L21/28518 , H01L21/28525 , H01L29/41775 , H01L29/41783
摘要： The method of the present invention includes forming a MOS on a semiconductor substrate. Subsequently, a silicon-rich metal silicide layer is deposited on the MOS and substrate by using chemical vapor deposition to act as a silicon material source. Then, a thermal process is carried out to separate a portion of the silicon out of the metal silicide layer, thereby forming a silicon layer on top of the gate of the MOS, source/drain. The nest step is to remove the metal suicide layer. A self-aligned metal silicide layer is formed on the silicon layer.
摘要翻译：本发明的方法包括在半导体衬底上形成MOS。随后，通过使用化学气相沉积作为硅材料源，在MOS和衬底上沉积富硅金属硅化物层。然后，进行热处理以将硅的一部分从金属硅化物层分离出来，从而在MOS源极/漏极的栅极顶部形成硅层。嵌套步骤是去除金属硅化物层。在硅层上形成自对准的金属硅化物层。

8. 发明授权

US5924010A Method for simultaneously fabricating salicide and self-aligned barrier 失效
标题翻译：同时制造自对准和自对准屏障的方法
公开(公告)号：US5924010A
公开(公告)日：1999-07-13
申请号：US740512
申请日：1996-10-30
申请人： Shu-Jen Chen , Jiunn-Hsien Lin , Chih-Ching Hsu
发明人： Shu-Jen Chen , Jiunn-Hsien Lin , Chih-Ching Hsu
IPC分类号： H01L21/28 , H01L21/336
CPC分类号： H01L29/665 , H01L21/28052
摘要： A method of fabricating salicide and self-aligned barrier simultaneously is disclosed. The initial steps include sputtering a metal stack (Ti--TiN--Ti) and forming a salicide layer by thermally reacting the metal stack and the wafer followed by a chemical etching which removes the unreacted portions of the metal stack. The portions of the metal stack on Si can react with Si to form a TiSi.sub.2 layer, thus forming TiSi.sub.2 --TiN--TiSi.sub.2. The TiSi.sub.2 layer over the TiN layer acts as a mask in the chemical etching and protects the TiN layer from been etched. The diffusion barrier layer is thus formed simultaneously within the fabricating of salicide.
摘要翻译：公开了一种同时制造自对准屏障的方法。初始步骤包括溅射金属叠层（Ti-TiN-Ti）并通过使金属叠层和晶片热反应，然后通过化学蚀刻形成硅化物层，从而除去金属堆叠体的未反应部分。 Si上的金属堆叠部分可与Si反应形成TiSi2层，从而形成TiSi2-TiN-TiSi2。 TiN层上的TiSi2层用作化学蚀刻中的掩模，并保护TiN层免受蚀刻。因此，在制造硅化物的同时形成扩散阻挡层。

9. 发明申请

US20130076575A1 PORTABLE ELECTRONIC APPARATUS WITH ANTENNA STRUCTURE 审中-公开
标题翻译：具有天线结构的便携式电子设备
公开(公告)号：US20130076575A1
公开(公告)日：2013-03-28
申请号：US13334067
申请日：2011-12-22
申请人： Ching-Chia Mai , Chih-Ching Hsu , Cheng-Han Lee , Yuan-Chin Hsu
发明人： Ching-Chia Mai , Chih-Ching Hsu , Cheng-Han Lee , Yuan-Chin Hsu
IPC分类号： H01Q1/24
CPC分类号： H01Q1/52 , H01Q1/243
摘要： A portable electronic apparatus with antenna structure is disclosed. The portable electronic apparatus includes an apparatus casing, an antenna structure, and an electronic component. The apparatus casing has an accommodating space and an appearance casing. The antenna structure is disposed adjacent to the appearance casing. The electronic component is disposed in the accommodating space and leaks electromagnetic wave during operation. Thereby, even though the electronic component leaks electromagnetic wave toward the antenna structure, the invention can reduce the influence on the antenna structure by the leaked electromagnetic wave by disposing the antenna structure as away from the electronic component as possible. Therefore, the antenna structure still can work normally during the operation of the electronic component, which solves the problem that an antenna structure of a conventional portable electronic apparatus is easily interrupted in the range of the leaked electromagnetic wave in the prior art.
摘要翻译：公开了一种具有天线结构的便携式电子设备。便携式电子设备包括装置壳体，天线结构和电子部件。设备壳体具有容纳空间和外观壳体。天线结构设置在外观外壳附近。电子部件设置在容纳空间中，在运转时泄漏电磁波。因此，即使电子部件向天线结构泄漏电磁波，本发明也可以通过将天线结构尽可能远离电子部件来减少由泄露的电磁波对天线结构的影响。因此，在电子部件的动作中，天线结构仍然可以正常工作，这解决了现有技术中传统的便携式电子设备的天线结构在泄漏电磁波的范围内容易中断的问题。

10. 发明申请

US20090186531A1 Electrical connector having improved connecting module 有权
标题翻译：电连接器具有改进的连接模块
公开(公告)号：US20090186531A1
公开(公告)日：2009-07-23
申请号：US12321710
申请日：2009-01-22
申请人： Chih-Ching Hsu
发明人： Chih-Ching Hsu
IPC分类号： H01R24/04 , H01R3/00
CPC分类号： H01R13/6658 , H01R13/7175 , H01R24/64
摘要： An electrical connector (100) includes an insulative element (1) and an electrical unit (2) mounted to the insluative element. The electrical unit includes a housing (21), a terminal module (23) assembled to the housing, at least a daughter board (25) mounted to a side portion of the housing, and a connecting module (27). The connecting module has a base (271), a number of first pins (273) assembled to the base and extending through the daughter board, and at least a contacting subassembly (272) mounted to the base and having a number of second pins (277) connected to the daughter board.
摘要翻译：电连接器（100）包括绝缘元件（1）和安装在所述绝缘元件上的电单元（2）。电气单元包括壳体（21），组装到壳体的端子模块（23），安装到壳体的侧部的至少一个子板（25）和连接模块（27）。连接模块具有底座（271），多个第一销（273）组装到底座并延伸通过子板，以及至少一个安装到基座上的接触子组件（272），并具有多个第二销（ 277）连接到子板。

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