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1. 发明授权

US5998286A Method to grow self-aligned silicon on a poly-gate, source and drain region 失效
标题翻译：在多晶硅，源极和漏极区域生长自对准硅的方法
公开(公告)号：US5998286A
公开(公告)日：1999-12-07
申请号：US48924
申请日：1998-03-26
申请人： Shu-Jen Chen , Jacky Kuo , Jiunn-Hsien Lin , Chih-Ching Hsu
发明人： Shu-Jen Chen , Jacky Kuo , Jiunn-Hsien Lin , Chih-Ching Hsu
IPC分类号： H01L21/28 , H01L21/285 , H01L21/336 , H01L29/417 , H01L21/283
CPC分类号： H01L29/665 , H01L21/28052 , H01L21/28518 , H01L21/28525 , H01L29/41775 , H01L29/41783
摘要： The method of the present invention includes forming a MOS on a semiconductor substrate. Subsequently, a silicon-rich metal silicide layer is deposited on the MOS and substrate by using chemical vapor deposition to act as a silicon material source. Then, a thermal process is carried out to separate a portion of the silicon out of the metal silicide layer, thereby forming a silicon layer on top of the gate of the MOS, source/drain. The nest step is to remove the metal suicide layer. A self-aligned metal silicide layer is formed on the silicon layer.
摘要翻译：本发明的方法包括在半导体衬底上形成MOS。随后，通过使用化学气相沉积作为硅材料源，在MOS和衬底上沉积富硅金属硅化物层。然后，进行热处理以将硅的一部分从金属硅化物层分离出来，从而在MOS源极/漏极的栅极顶部形成硅层。嵌套步骤是去除金属硅化物层。在硅层上形成自对准的金属硅化物层。

2. 发明授权

US5924010A Method for simultaneously fabricating salicide and self-aligned barrier 失效
标题翻译：同时制造自对准和自对准屏障的方法
公开(公告)号：US5924010A
公开(公告)日：1999-07-13
申请号：US740512
申请日：1996-10-30
申请人： Shu-Jen Chen , Jiunn-Hsien Lin , Chih-Ching Hsu
发明人： Shu-Jen Chen , Jiunn-Hsien Lin , Chih-Ching Hsu
IPC分类号： H01L21/28 , H01L21/336
CPC分类号： H01L29/665 , H01L21/28052
摘要： A method of fabricating salicide and self-aligned barrier simultaneously is disclosed. The initial steps include sputtering a metal stack (Ti--TiN--Ti) and forming a salicide layer by thermally reacting the metal stack and the wafer followed by a chemical etching which removes the unreacted portions of the metal stack. The portions of the metal stack on Si can react with Si to form a TiSi.sub.2 layer, thus forming TiSi.sub.2 --TiN--TiSi.sub.2. The TiSi.sub.2 layer over the TiN layer acts as a mask in the chemical etching and protects the TiN layer from been etched. The diffusion barrier layer is thus formed simultaneously within the fabricating of salicide.
摘要翻译：公开了一种同时制造自对准屏障的方法。初始步骤包括溅射金属叠层（Ti-TiN-Ti）并通过使金属叠层和晶片热反应，然后通过化学蚀刻形成硅化物层，从而除去金属堆叠体的未反应部分。 Si上的金属堆叠部分可与Si反应形成TiSi2层，从而形成TiSi2-TiN-TiSi2。 TiN层上的TiSi2层用作化学蚀刻中的掩模，并保护TiN层免受蚀刻。因此，在制造硅化物的同时形成扩散阻挡层。

3. 发明授权

US06197680B1 Method for forming conductive line 有权
标题翻译：形成导线的方法
公开(公告)号：US06197680B1
公开(公告)日：2001-03-06
申请号：US09313510
申请日：1999-05-17
申请人： Jiunn-Hsien Lin , Wen-Pin Kuo
发明人： Jiunn-Hsien Lin , Wen-Pin Kuo
IPC分类号： H01L214763
CPC分类号： H01L21/02071 , H01L21/32136 , H01L21/7682 , H01L21/76838 , H01L23/5222 , H01L23/5283 , H01L2924/0002 , H01L2924/00
摘要： An improved method of forming a conductive line on a semiconductor substrate is described. A conductive layer is formed on the substrate. A patterned photoresist layer is formed on the conductive layer. A first etching step is performed on the conductive layer to define the conductive layer and to form a conductive line. A second etching step is performed on the conductive line to undercut the conductive line so as to make the conductive line have smaller bottom and to increase a distance between neighboring conductive lines. A third etching step is performed to remove residue generated on the substrate during the first and the second etching steps. A dielectric layer is formed to cover the conductive line. A planarization process is performed.
摘要翻译：描述了在半导体衬底上形成导线的改进方法。在基板上形成导电层。在导电层上形成图案化的光致抗蚀剂层。在导电层上执行第一蚀刻步骤以限定导电层并形成导电线。在导电线上执行第二蚀刻步骤以切割导电线，以使导线具有较小的底部并增加相邻导电线之间的距离。执行第三蚀刻步骤以在第一和第二蚀刻步骤期间去除在基板上产生的残留物。形成介电层以覆盖导线。进行平面化处理。

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