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1. 发明授权

US06340632B1 Method of manufacturing a semiconductor device 有权
标题翻译：制造半导体器件的方法
公开(公告)号：US06340632B1
公开(公告)日：2002-01-22
申请号：US09585629
申请日：2000-06-02
申请人： Shinichi Fukada , Kazuo Nojiri , Takashi Yunogami , Shoji Hotta , Hideo Aoki , Takayuki Oshima , Nobuyoshi Kobayashi
发明人： Shinichi Fukada , Kazuo Nojiri , Takashi Yunogami , Shoji Hotta , Hideo Aoki , Takayuki Oshima , Nobuyoshi Kobayashi
IPC分类号： H01L214763
CPC分类号： H01L21/76874 , H01L21/76804 , H01L21/76811 , H01L21/76813 , H01L21/76829 , H01L21/76843 , H01L21/76873 , H01L23/53238 , H01L2221/1036 , H01L2924/0002 , H01L2924/00
摘要： Insulating films 34 through 38 (of which insulating films 34, 36, 38 are silicon nitride films and insulating films 35, 38 are silicon oxide films) are sequentially formed on the wires 33 of the fourth wiring layer and groove pattern 40 is transferred into the insulating film 38 by means of photolithography. An anti-reflection film 41 is formed to fill the grooves 40 of the insulating film 38 and then a resist film 42 carrying a hole pattern 43 is formed. The films are subjected to an etching operation in the presence of the resist film 42 to transfer the hole pattern into the insulating films 38, 37, 36 and part of the insulating film 35. Subsequently, the resist film 42 and the anti-reflection film 41 are removed and the groove pattern 40 and the hole pattern 43 are transferred respectively into the insulating film 37 and the insulating film 35 by using the insulating film 38 as mask.
摘要翻译：绝缘膜34至38（其绝缘膜34,36,38是氮化硅膜和绝缘膜35,38是氧化硅膜）依次形成在第四布线层的布线33上，并将凹槽图案40转移到绝缘膜38。形成防反射膜41以填充绝缘膜38的槽40，然后形成承载孔图案43的抗蚀剂膜42。在存在抗蚀剂膜42的情况下对膜进行蚀刻操作，以将孔图案转印到绝缘膜38,37,36和绝缘膜35的一部分中。随后，将抗蚀剂膜42和抗反射膜 41，并且通过使用绝缘膜38作为掩模将槽图案40和孔图案43分别转印到绝缘膜37和绝缘膜35中。

2. 发明授权

US06555464B2 Semiconductor device and method of manufacturing the same 有权
公开(公告)号：US06555464B2
公开(公告)日：2003-04-29
申请号：US10046814
申请日：2002-01-17
申请人： Shinichi Fukada , Kazuo Nojiri , Takashi Yunogami , Shoji Hotta , Hideo Aoki , Takayuki Oshima , Nobuyoshi Kobayashi
发明人： Shinichi Fukada , Kazuo Nojiri , Takashi Yunogami , Shoji Hotta , Hideo Aoki , Takayuki Oshima , Nobuyoshi Kobayashi
IPC分类号： H01L214763
CPC分类号： H01L21/76874 , H01L21/76804 , H01L21/76811 , H01L21/76813 , H01L21/76829 , H01L21/76843 , H01L21/76873 , H01L23/53238 , H01L2221/1036 , H01L2924/0002 , H01L2924/00
摘要： Insulating films 34 through 38 (of which insulating films 34, 36, 38 are silicon nitride films and insulating films 35, 38 are silicon oxide films) are sequentially formed on the wires 33 of the fourth wiring layer and groove pattern 40 is transferred into the insulating film 38 by means of photolithography. An anti-reflection film 41 is formed to fill the grooves 40 of the insulating film 38 and then a resist film 42 carrying a hole pattern 43 is formed. The films are subjected to an etching operation in the presence of the resist film 42 to transfer the hole pattern into the insulating films 38, 37, 36 and part of the insulating film 35. Subsequently, the resist film 42 and the anti-reflection film 41 are removed and the groove pattern 40 and the hole pattern 43 are transferred respectively into the insulating film 37 and the insulating film 35 by using the insulating film 38 as mask.

3. 发明授权

US06774020B2 Semiconductor device and method of manufacturing the same 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US06774020B2
公开(公告)日：2004-08-10
申请号：US10355116
申请日：2003-01-31
申请人： Shinichi Fukada , Kazuo Nojiri , Takashi Yunogami , Shoji Hotta , Hideo Aoki , Takayuki Oshima , Nobuyoshi Kobayashi
发明人： Shinichi Fukada , Kazuo Nojiri , Takashi Yunogami , Shoji Hotta , Hideo Aoki , Takayuki Oshima , Nobuyoshi Kobayashi
IPC分类号： H01L2120
CPC分类号： H01L21/76874 , H01L21/76804 , H01L21/76811 , H01L21/76813 , H01L21/76829 , H01L21/76843 , H01L21/76873 , H01L23/53238 , H01L2221/1036 , H01L2924/0002 , H01L2924/00
摘要： Insulating films 34 through 38 (of which insulating films 34, 36, 38 are silicon nitride films and insulating films 35, 38 are silicon oxide films) are sequentially formed on the wires 33 of the fourth wiring layer and groove pattern 40 is transferred into the insulating film 38 by means of photolithography. An anti-reflection film 41 is formed to fill the grooves 40 of the insulating film 38 and then a resist film 42 carrying a hole pattern 43 is formed. The films are subjected to an etching operation in the presence of the resist film 42 to transfer the hole pattern into the insulating films 38, 37, 36 and part of the insulating film 35. Subsequently, the resist film 42 and the anti-reflection film 41 are removed and the groove pattern 40 and the hole pattern 43 are transferred respectively into the insulating film 37 and the insulating film 35 by using the insulating film 38 as mask.
摘要翻译：绝缘膜34至38（其绝缘膜34,36,38是氮化硅膜和绝缘膜35,38是氧化硅膜）依次形成在第四布线层的布线33上，并将凹槽图案40转移到绝缘膜38。形成防反射膜41以填充绝缘膜38的槽40，然后形成承载孔图案43的抗蚀剂膜42。在存在抗蚀剂膜42的情况下对膜进行蚀刻操作，以将孔图案转印到绝缘膜38,37,36和绝缘膜35的一部分中。随后，将抗蚀剂膜42和抗反射膜 41，并且通过使用绝缘膜38作为掩模将槽图案40和孔图案43分别转印到绝缘膜37和绝缘膜35中。

4. 发明授权

US06528400B2 Method of manufacturing a semiconductor device 有权
公开(公告)号：US06528400B2
公开(公告)日：2003-03-04
申请号：US09998649
申请日：2001-12-03
申请人： Shinichi Fukada , Kazuo Nojiri , Takashi Yunogami , Shoji Hotta , Hideo Aoki , Takayuki Oshima , Nobuyoshi Kobayashi
发明人： Shinichi Fukada , Kazuo Nojiri , Takashi Yunogami , Shoji Hotta , Hideo Aoki , Takayuki Oshima , Nobuyoshi Kobayashi
IPC分类号： H01L2120
CPC分类号： H01L21/76874 , H01L21/76804 , H01L21/76811 , H01L21/76813 , H01L21/76829 , H01L21/76843 , H01L21/76873 , H01L23/53238 , H01L2221/1036 , H01L2924/0002 , H01L2924/00
摘要： Insulating films 34 through 38 (of which insulating films 34, 36, 38 are silicon nitride films and insulating films 35, 38 are silicon oxide films) are sequentially formed on the wires 33 of the fourth wiring layer and groove pattern 40 is transferred into the insulating film 38 by means of photolithography. An anti-reflection film 41 is formed to fill the grooves 40 of the insulating film 38 and then a resist film 42 carrying a hole pattern 43 is formed. The films are subjected to an etching operation in the presence of the resist film 42 to transfer the hole pattern into the insulating films 38, 37, 36 and part of the insulating film 35. Subsequently, the resist film 42 and the anti-reflection film 41 are removed and the groove pattern 40 and the hole pattern 43 are transferred respectively into the insulating film 37 and the insulating film 35 by using the insulating film 38 as mask.

5. 发明申请

US20070004189A1 Manufacturing method of semiconductor device 失效
标题翻译：半导体器件的制造方法
公开(公告)号：US20070004189A1
公开(公告)日：2007-01-04
申请号：US11516762
申请日：2006-09-07
申请人： Junji Noguchi , Hideo Aoki , Shoji Hotta , Takayuki Oshima
发明人： Junji Noguchi , Hideo Aoki , Shoji Hotta , Takayuki Oshima
IPC分类号： H01L21/44
CPC分类号： H01L21/76811 , H01L21/02052 , H01L21/02063 , H01L21/31116 , H01L21/31144 , H01L21/76802 , H01L21/76813
摘要： The present invention provides a method for preventing the defect the in shape of via holes cased when an alumina mask is used for the dry etching of an interlayer insulator composed of an SiOC film in the dual damascene process in which via holes are formed prior to forming wiring trenches. That is, after forming an alumina mask on an interlayer insulator composed of a low-k SiOC film via a cap insulator, the cap insulator and the interlayer insulator are dry-etched with using a photoresist film as a mask to form via holes. Next, after removing the photoresist film, the inside of the via holes are cleaned by using dilute hydrofluoric acid solution to remove alumina residue. Thereafter, the cap insulator and the interlayer insulator are dry-etched with using the alumina mask as a mask to form wiring trenches.
摘要翻译：本发明提供了一种在双镶嵌工艺中使用氧化铝掩模用于干法蚀刻由SiOC膜构成的层间绝缘膜时形成通孔的缺陷的方法，其中在形成过孔之前形成通孔接线沟。也就是说，在通过盖绝缘体由低k SiOC膜构成的层间绝缘体上形成氧化铝掩模之后，使用光致抗蚀剂膜作为掩模对盖绝缘体和层间绝缘体进行干蚀刻以形成通孔。接下来，在除去光致抗蚀剂膜之后，通过使用稀氢氟酸溶液来清洁通孔的内部以除去氧化铝残留物。此后，使用氧化铝掩模作为掩模来干蚀刻帽绝缘体和层间绝缘体以形成布线沟槽。

6. 发明申请

US20050118809A1 Manufacturing method of semiconductor device 失效
标题翻译：半导体器件的制造方法
公开(公告)号：US20050118809A1
公开(公告)日：2005-06-02
申请号：US10981662
申请日：2004-11-05
申请人： Junji Noguchi , Hideo Aoki , Shoji Hotta , Takayuki Oshima
发明人： Junji Noguchi , Hideo Aoki , Shoji Hotta , Takayuki Oshima
IPC分类号： H01L21/3065 , H01L21/28 , H01L21/304 , H01L21/306 , H01L21/311 , H01L21/3213 , H01L21/44 , H01L21/768 , H01L23/522
CPC分类号： H01L21/76811 , H01L21/02052 , H01L21/02063 , H01L21/31116 , H01L21/31144 , H01L21/76802 , H01L21/76813
摘要： The present invention provides a method for preventing the defect the in shape of via holes cased when an alumina mask is used for the dry etching of an interlayer insulator composed of an SiOC film in the dual damascene process in which via holes are formed prior to forming wiring trenches. That is, after forming an alumina mask on an interlayer insulator composed of a low-k SiOC film via a cap insulator, the cap insulator and the interlayer insulator are dry-etched with using a photoresist film as a mask to form via holes. Next, after removing the photoresist film, the inside of the via holes are cleaned by using dilute hydrofluoric acid solution to remove alumina residue. Thereafter, the cap insulator and the interlayer insulator are dry-etched with using the alumina mask as a mask to form wiring trenches.
摘要翻译：本发明提供了一种在双镶嵌工艺中使用氧化铝掩模用于干法蚀刻由SiOC膜构成的层间绝缘膜时形成通孔的缺陷的方法，其中在形成过孔之前形成通孔接线沟。也就是说，在通过盖绝缘体由低k SiOC膜构成的层间绝缘体上形成氧化铝掩模之后，使用光致抗蚀剂膜作为掩模对盖绝缘体和层间绝缘体进行干蚀刻以形成通孔。接下来，在除去光致抗蚀剂膜之后，通过使用稀氢氟酸溶液来清洁通孔的内部以除去氧化铝残留物。此后，使用氧化铝掩模作为掩模来干蚀刻帽绝缘体和层间绝缘体以形成布线沟槽。

7. 发明授权

US07419916B2 Manufacturing method of semiconductor device 失效
标题翻译：半导体器件的制造方法
公开(公告)号：US07419916B2
公开(公告)日：2008-09-02
申请号：US11516762
申请日：2006-09-07
申请人： Junji Noguchi , Hideo Aoki , Shoji Hotta , Takayuki Oshima
发明人： Junji Noguchi , Hideo Aoki , Shoji Hotta , Takayuki Oshima
IPC分类号： H01L21/302 , H01L21/461 , H01L21/44
CPC分类号： H01L21/76811 , H01L21/02052 , H01L21/02063 , H01L21/31116 , H01L21/31144 , H01L21/76802 , H01L21/76813
摘要： The present invention provides a method for preventing the defect the in shape of via holes cased when an alumina mask is used for the dry etching of an interlayer insulator composed of an SiOC film in the dual damascene process in which via holes are formed prior to forming wiring trenches. That is, after forming an alumina mask on an interlayer insulator composed of a low-k SiOC film via a cap insulator, the cap insulator and the interlayer insulator are dry-etched with using a photoresist film as a mask to form via holes. Next, after removing the photoresist film, the inside of the via holes are cleaned by using dilute hydrofluoric acid solution to remove alumina residue. Thereafter, the cap insulator and the interlayer insulator are dry-etched with using the alumina mask as a mask to form wiring trenches.
摘要翻译：本发明提供了一种在双镶嵌工艺中使用氧化铝掩模用于干法蚀刻由SiOC膜构成的层间绝缘膜时形成通孔的缺陷的方法，其中在形成过孔之前形成通孔接线沟。也就是说，在通过盖绝缘体由低k SiOC膜构成的层间绝缘体上形成氧化铝掩模之后，使用光致抗蚀剂膜作为掩模对盖绝缘体和层间绝缘体进行干蚀刻以形成通孔。接下来，在除去光致抗蚀剂膜之后，通过使用稀氢氟酸溶液来清洁通孔的内部以除去氧化铝残留物。此后，使用氧化铝掩模作为掩模来干蚀刻帽绝缘体和层间绝缘体以形成布线沟槽。

8. 发明授权

US07109127B2 Manufacturing method of semiconductor device 失效
标题翻译：半导体器件的制造方法
公开(公告)号：US07109127B2
公开(公告)日：2006-09-19
申请号：US10981662
申请日：2004-11-05
申请人： Junji Noguchi , Hideo Aoki , Shoji Hotta , Takayuki Oshima
发明人： Junji Noguchi , Hideo Aoki , Shoji Hotta , Takayuki Oshima
IPC分类号： H01L21/302 , H01L21/461 , H01L21/44
CPC分类号： H01L21/76811 , H01L21/02052 , H01L21/02063 , H01L21/31116 , H01L21/31144 , H01L21/76802 , H01L21/76813
摘要： The present invention provides a method for preventing the defect the in shape of via holes cased when an alumina mask is used for the dry etching of an interlayer insulator composed of an SiOC film in the dual damascene process in which via holes are formed prior to forming wiring trenches. That is, after forming an alumina mask on an interlayer insulator composed of a low-k SiOC film via a cap insulator, the cap insulator and the interlayer insulator are dry-etched with using a photoresist film as a mask to form via holes. Next, after removing the photoresist film, the inside of the via holes are cleaned by using dilute hydrofluoric acid solution to remove alumina residue. Thereafter, the cap insulator and the interlayer insulator are dry-etched with using the alumina mask as a mask to form wiring trenches.
摘要翻译：本发明提供了一种在双镶嵌工艺中使用氧化铝掩模用于干法蚀刻由SiOC膜构成的层间绝缘膜时形成通孔的缺陷的方法，其中在形成过孔之前形成通孔接线沟。也就是说，在通过盖绝缘体由低k SiOC膜构成的层间绝缘体上形成氧化铝掩模之后，使用光致抗蚀剂膜作为掩模对盖绝缘体和层间绝缘体进行干蚀刻以形成通孔。接下来，在除去光致抗蚀剂膜之后，通过使用稀氢氟酸溶液来清洁通孔的内部以除去氧化铝残留物。此后，使用氧化铝掩模作为掩模来干蚀刻帽绝缘体和层间绝缘体以形成布线沟槽。

9. 发明授权

US07943903B2 Defect inspection method and its system 有权
标题翻译：缺陷检查方法及其系统
公开(公告)号：US07943903B2
公开(公告)日：2011-05-17
申请号：US12320574
申请日：2009-01-29
申请人： Shinji Okazaki , Shoji Hotta , Yasunari Sohda , Yoshinori Nakayama
发明人： Shinji Okazaki , Shoji Hotta , Yasunari Sohda , Yoshinori Nakayama
IPC分类号： H01J37/153 , G01N23/00
CPC分类号： H01L22/12 , G06T7/0006 , G06T7/001 , G06T2207/10056 , G06T2207/30148 , H01L2924/0002 , H01L2924/00
摘要： A method for enabling management of fatal defects of semiconductor integrated patterns easily, the method enables storing of design data of each pattern designed by a semiconductor integrated circuit designer, as well as storing of design intent data having pattern importance levels ranked according to their design intents respectively. The method also enables anticipating of defects to be generated systematically due to the characteristics of the subject exposure system, etc. while each designed circuit pattern is exposed and delineated onto a wafer in a simulation carried out beforehand and storing those defects as hot spot information. Furthermore, the method also enables combining of the design intent data with hot spot information to limit inspection spots that might include systematic defects at high possibility with respect to the characteristics of the object semiconductor integrated circuit and shorten the defect inspection time significantly.
摘要翻译：一种能够容易地管理半导体集成图案的致命缺陷的方法，该方法能够存储由半导体集成电路设计者设计的每个图案的设计数据，以及存储具有根据其设计意图排列的图案重要性级别的设计意图数据分别。该方法还可以预测由于目标曝光系统等的特性而系统地产生的缺陷，同时在预先进行的模拟中将每个设计的电路图案暴露并描绘到晶片上，并将这些缺陷存储为热点信息。此外，该方法还能够将设计意图数据与热点信息组合，以限制可能包括关于对象半导体集成电路的特性的高可能性的系统缺陷的检查点，并显着缩短缺陷检查时间。

10. 发明申请

US20080006149A1 Compressor 审中-公开
标题翻译：压缩机
公开(公告)号：US20080006149A1
公开(公告)日：2008-01-10
申请号：US11824858
申请日：2007-07-03
申请人： Takayuki Kato , Fuminobu Enokijima , Masaki Inoue , Hajime Ikuno , Akira Yamada , Hiroshi Hohjo , Hiroshi Kawahara , Shoji Hotta , Isamu Ueda
发明人： Takayuki Kato , Fuminobu Enokijima , Masaki Inoue , Hajime Ikuno , Akira Yamada , Hiroshi Hohjo , Hiroshi Kawahara , Shoji Hotta , Isamu Ueda
IPC分类号： F02F7/00
CPC分类号： F04B39/12 , C22C21/02 , C22F1/043 , F04B27/1081 , F05C2201/021 , F05C2201/903
摘要： A compressor having a housing formed by a plurality of housing members that are connected together is disclosed. The compressor is configured in such a manner that refrigerant is compressed in the housing and discharged to the exterior. Each of the housing members contains 9 to 17 percent by mass of Si, 3.5 to 6 percent by mass of Cu, 0.2 to 1.2 percent by mass of Mg, 0.2 to 1.5 percent by mass of Fe, 0 to 1 percent by mass of Mn, 0.5 percent by mass or less of Ni, and a remaining portion containing Al and unavoidable impurities. It is preferred that the average hardness of each housing member is adjusted to HV130 to HV170 through solution heating in which the housing member is maintained at the treatment temperature of 450° C. to 510° C. for 0.5 hours or longer, followed by water quenching, and then by aging treatment in which the housing member is maintained at the treatment temperature of 170° C. to 230° C. for one to twenty-four hours after the c housing member is cast.
摘要翻译：公开了一种压缩机，其具有由连接在一起的多个壳体构件形成的壳体。压缩机构造成使得制冷剂在壳体中被压缩并排放到外部。每个壳体中含有9〜17质量％的Si，3.5〜6质量％的Cu，0.2〜1.2质量％的Mg，0.2〜1.5质量％的Fe，0〜1质量％的Mn ，0.5质量％以下的Ni，剩余部分含有Al和不可避免的杂质。优选地，通过溶液加热将每个壳体构件的平均硬度调节至HV130至HV170，其中壳体构件在450℃至510℃的处理温度下保持0.5小时或更长时间，然后是水淬火，然后通过老化处理，其中壳体构件被保持在处理温度为170℃至230℃，在c壳体构件被铸造之后一到二十四小时。

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