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1. 发明授权

US08001328B2 Method and process for expediting the return of line exclusivity to a given processor through enhanced inter-node communications 有权
标题翻译：通过增强的节点间通信来加速线路排他性返回到给定处理器的方法和过程
公开(公告)号：US08001328B2
公开(公告)日：2011-08-16
申请号：US12021378
申请日：2008-01-29
申请人： Sebastian C. Burckhardt , Arthur J. O'Neill , Vesselina K. Papazova , Craig R. Walters
发明人： Sebastian C. Burckhardt , Arthur J. O'Neill , Vesselina K. Papazova , Craig R. Walters
IPC分类号： G06F12/00
CPC分类号： G06F12/0831 , G06F12/0813 , G06F2212/1016
摘要： A method and apparatus in which the observability of cross-invalidates requests within remote nodes is controlled at the time of a partial response generation, when a remote request initially checks/snoops the directory state of the remote node, but before such the time that the cross-invalidate request is actually sent to the processors on a given node. If all of the remote nodes in the system indicate that the cross-invalidates could be sent during an initial directory snoop, the requesting node is able to return full exclusivity to a given cache line to a requesting processor at the time when it receives all of the partial responses, instead of having to wait for the final responses from each of the remote nodes within the system.
摘要翻译：当远程请求最初检查/窥探远程节点的目录状态时，而在远程节点的时间之前，在部分响应生成时控制远程节点内的交叉无效请求的可观察性的方法和装置，交叉无效请求实际上发送给给定节点上的处理器。如果系统中的所有远程节点指示可以在初始目录窥探期间发送交叉无效信息，则请求节点能够在给定的缓存行接收到所有请求的处理器时向所请求的处理器返回完整的排他性部分响应，而不必等待系统内每个远程节点的最终响应。

2. 发明授权

US08131937B2 Apparatus and method for improved data persistence within a multi-node system 有权
标题翻译：用于改善多节点系统内的数据持久性的装置和方法
公开(公告)号：US08131937B2
公开(公告)日：2012-03-06
申请号：US11766977
申请日：2007-06-22
申请人： Michael A. Blake , Harmony L. Helterhoff , Arthur J. O'Neill , Vesselina K. Papazova , Craig R. Walters
发明人： Michael A. Blake , Harmony L. Helterhoff , Arthur J. O'Neill , Vesselina K. Papazova , Craig R. Walters
IPC分类号： G06F13/00
CPC分类号： G06F12/084 , G06F12/0897 , G06F12/126
摘要： Improved access to retained data useful to a system is accomplished by managing data flow through cache associated with the processor(s) of a multi-node system. A data management facility operable with the processors and memory array directs the flow of data from the processors to the memory array by determining the path along which data evicted from a level of cache close to one of the processors is to return to a main memory and directing evicted data to be stored, if possible, in a horizontally associated cache.
摘要翻译：改进对对系统有用的保留数据的访问通过管理与多节点系统的处理器相关联的高速缓存的数据流来实现。可与处理器和存储器阵列一起操作的数据管理设备通过确定沿着哪个数据从处理器中的一个接收到的高速缓存驱逐出的数据返回到主存储器，从而将来自处理器的数据流引导到存储器阵列，如果可能的话，将被驱逐的数据存储在水平相关的缓存中。

3. 发明申请

US20090193192A1 Method and Process for Expediting the Return of Line Exclusivity to a Given Processor Through Enhanced Inter-node Communications 有权
标题翻译：通过增强的节点间通信加速给定处理器的线路独占性返回的方法和过程
公开(公告)号：US20090193192A1
公开(公告)日：2009-07-30
申请号：US12021378
申请日：2008-01-29
申请人： Sebastian Burckhardt , Arthur J. O'Neill , Vesselina K. Papazova , Craig R. Walters
发明人： Sebastian Burckhardt , Arthur J. O'Neill , Vesselina K. Papazova , Craig R. Walters
IPC分类号： G06F12/08
CPC分类号： G06F12/0831 , G06F12/0813 , G06F2212/1016
摘要： Cache coherency latency is reduced through a method and apparatus that expedites the return of line exclusivity to a given processor in a multi-node data handling system through enhanced inter-node communications.
摘要翻译：通过一种通过增强的节点间通信在多节点数据处理系统中加速线路排他性返回到给定处理器的方法和装置来减少高速缓存一致等待时间。

4. 发明申请

US20090006693A1 Apparatus and Method for Fairness Arbitration for a Shared Pipeline in a Large SMP Computer System 有权
标题翻译：大型SMP计算机系统共享管道公平仲裁的装置与方法
公开(公告)号：US20090006693A1
公开(公告)日：2009-01-01
申请号：US11768934
申请日：2007-06-27
申请人： Deanna P. Dunn , Christine C. Jones , Arthur J. O'Neill , Vesselina K. Papazova , Robert J. Sonnelitter, III , Craig R. Walters
发明人： Deanna P. Dunn , Christine C. Jones , Arthur J. O'Neill , Vesselina K. Papazova , Robert J. Sonnelitter, III , Craig R. Walters
IPC分类号： G06F13/14
CPC分类号： G06F13/14 , G06F9/50 , G06F2209/5021 , Y02D10/14 , Y02D10/22
摘要： A modification of rank priority arbitration for access to computer system resources through a shared pipeline that provides more equitable arbitration by allowing a higher ranked request access to the shared resource ahead of a lower ranked requester only one time. If multiple requests are active at the same time, the rank priority will first select the highest priority active request and grant it access to the resource. It will also set a ‘blocking latch’ to prevent that higher priority request from re-gaining access to the resource until the rest of the outstanding lower priority active requesters have had a chance to access the resource.
摘要翻译：通过共享流水线访问计算机系统资源的等级优先仲裁的修改，通过允许较高排名的请求仅在较低等级的请求者之前访问共享资源，提供更公平的仲裁。如果多个请求同时处于活动状态，则排名优先级将首先选择最高优先级的活动请求并授予对资源的访问权限。它还将设置一个“阻塞锁定”，以防止更高优先级的请求重新获得对资源的访问，直到其余的优先级较低的主动请求者有机会访问该资源。

5. 发明申请

US20080320226A1 Apparatus and Method for Improved Data Persistence within a Multi-node System 有权
标题翻译：在多节点系统内改善数据持久性的装置和方法
公开(公告)号：US20080320226A1
公开(公告)日：2008-12-25
申请号：US11766977
申请日：2007-06-22
申请人： Michael A. Blake , Harmony L. Helterhoff , Arthur J. O'Neill , Vesselina K. Papazova , Craig R. Walters
发明人： Michael A. Blake , Harmony L. Helterhoff , Arthur J. O'Neill , Vesselina K. Papazova , Craig R. Walters
IPC分类号： G06F13/00
CPC分类号： G06F12/084 , G06F12/0897 , G06F12/126
摘要： Improved access to retained data useful to a system is accomplished by managing data flow through cache associated with the processor(s) of a multi-node system. A data management facility operable with the processors and memory array directs the flow of data from the processors to the memory array by determining the path along which data evicted from a level of cache close to one of the processors is to return to a main memory and directing evicted data to be stored, if possible, in a horizontally associated cache.
摘要翻译：改进对对系统有用的保留数据的访问通过管理与多节点系统的处理器相关联的缓存的数据流来实现。可与处理器和存储器阵列一起操作的数据管理设备通过确定沿着哪个数据从处理器中的一个接收到的高速缓存驱逐出的数据返回到主存储器，从而将来自处理器的数据流引导到存储器阵列，如果可能的话，将被驱逐的数据存储在水平相关的缓存中。

6. 发明申请

US20130339808A1 BITLINE DELETION 失效
公开(公告)号：US20130339808A1
公开(公告)日：2013-12-19
申请号：US13523633
申请日：2012-06-14
申请人： Ekaterina M. Ambroladze , Michael A. Blake , Michael Fee , Hieu T. Huynh , Patrick J. Meaney , Arthur J. O'Neill
发明人： Ekaterina M. Ambroladze , Michael A. Blake , Michael Fee , Hieu T. Huynh , Patrick J. Meaney , Arthur J. O'Neill
IPC分类号： G06F11/20
CPC分类号： G06F11/1064 , G06F11/073 , G06F11/076 , G06F11/08 , G11C2029/1204
摘要： Embodiments relate to a method including detecting a first error when reading a first cache line, recording a first address of the first error, detecting a second error when reading a second cache line and recording a second address of the second error. Embodiments also include comparing the first and second bitline address, comparing the first and second wordline address, activating a bitline delete mode based on matching first and second bitline addresses and not matching the first and second wordline addresses, detecting a third error when reading a third cache line, recording a third bitline address of the third error, comparing the second bitline address to a third bitline address and deleting a location corresponding to the third cache line from available cache locations based on the activated bitline delete mode and the third bitline address matching the second bitline address.
摘要翻译：实施例涉及一种方法，包括当读取第一高速缓存行时检测第一错误，记录第一错误的第一地址，在读取第二高速缓存行时检测第二错误并记录第二错误的第二地址。实施例还包括比较第一和第二位线地址，比较第一和第二字线地址，基于匹配的第一和第二位线地址激活位线删除模式，并且不匹配第一和第二字线地址，在读取第三位线时检测第三错误记录第三错误的第三位线地址，将第二位线地址与第三位线地址进行比较，并且基于激活的位线删除模式和第三位线地址匹配从可用高速缓存位置删除与第三高速缓存行相对应的位置第二个位线地址。

7. 发明申请

US20130339822A1 BAD WORDLINE/ARRAY DETECTION IN MEMORY 有权
公开(公告)号：US20130339822A1
公开(公告)日：2013-12-19
申请号：US13523971
申请日：2012-06-15
申请人： Patrick J. Meaney , Arthur J. O'Neill , Gary E. Strait
发明人： Patrick J. Meaney , Arthur J. O'Neill , Gary E. Strait
IPC分类号： H03M13/05 , G06F11/10
CPC分类号： H03M13/05 , G06F11/073 , G06F11/1008 , G06F11/1064 , G06F11/1666 , G06F11/20
摘要： A technique for error detection is provided. A controller is configured to detect errors by using error correcting code (ECC), and a cache includes independent ECC words for storing data. The controller detects the errors in the ECC words for a wordline that is read. The controller detects a first error in a first ECC word on the wordline and a second error in a second ECC word on the wordline. The controller determines that the wordline is a failing wordline based on detecting the first error in the first ECC word and the second error in the second ECC word.

8. 发明申请

US20130339606A1 REDUCING STORE OPERATION BUSY TIMES 有权
标题翻译：减少存储操作繁忙时间
公开(公告)号：US20130339606A1
公开(公告)日：2013-12-19
申请号：US13523567
申请日：2012-06-14
申请人： Deanna Postles Dunn Berger , Michael F. Fee , Christine C. Jones , Arthur J. O'Neill , Diane L. Orf
发明人： Deanna Postles Dunn Berger , Michael F. Fee , Christine C. Jones , Arthur J. O'Neill , Diane L. Orf
IPC分类号： G06F12/08
CPC分类号： G06F12/0806 , G06F9/38 , G06F9/3855 , G06F12/0855 , G11C7/22 , G11C2207/229 , Y02D10/13
摘要： A computer product for reducing store operation busy times is provided and relates to associating first and second platform registers with a cache array, determining that first and second store operations target a same wordline of the cache array, loading control information and data of the store operations into the platform registers and delaying a commit of the first store operation until the loading of the second platform register is complete. The method further includes committing the data from the platform registers using the control information from the platform registers to the wordline of the cache array at a same time to thereby reduce a busy time of the wordline of the cache array.
摘要翻译：提供了用于减少存储操作繁忙时间的计算机产品，并且涉及将第一和第二平台寄存器与高速缓存阵列相关联，确定第一和第二存储操作针对高速缓存阵列的相同字线，加载控制信息和存储操作的数据进入平台寄存器并延迟第一个存储操作的提交，直到第二个平台寄存器的加载完成。该方法还包括使用来自平台寄存器的控制信息将来自平台寄存器的数据同时提交到高速缓存阵列的字线，从而减少高速缓存阵列的字线的繁忙时间。

9. 发明申请

US20110320697A1 DYNAMICALLY SUPPORTING VARIABLE CACHE ARRAY BUSY AND ACCESS TIMES 失效
标题翻译：动态地支持可变缓存队列和访问时间
公开(公告)号：US20110320697A1
公开(公告)日：2011-12-29
申请号：US12822341
申请日：2010-06-24
申请人： Deanna P. Berger , Michael F. Fee , Arthur J. O'Neill
发明人： Deanna P. Berger , Michael F. Fee , Arthur J. O'Neill
IPC分类号： G06F12/08 , G06F12/02
CPC分类号： G06F12/0851
摘要： Various embodiments of the present invention manage access to a cache memory. In or more embodiments a request for a targeted interleave within a cache memory is received. The request is associated with an operation of a given type. The target is determined to be available. The request is granted in response to the determining that the target is available. A first interleave availability table associated with a first busy time associated with the cache memory is updated based on the operation associated with the request in response to granting the request. A second interleave availability table associated with a second busy time associated with the cache memory is updated based on the operation associated with the request in response to granting the request.
摘要翻译：本发明的各种实施例管理对高速缓冲存储器的访问。在一个或多个实施例中，接收对高速缓冲存储器内的目标交错的请求。该请求与给定类型的操作相关联。目标被确定为可用。响应于确定目标可用的请求被授予。基于与请求相关联的操作来响应于授予请求来更新与与高速缓冲存储器相关联的第一繁忙时间相关联的第一交错可用性表。基于与请求相关联的响应于响应于授予请求而更新与与高速缓冲存储器相关联的第二繁忙时间相关联的第二交织可用性表。

10. 发明授权

US09075727B2 Reducing penalties for cache accessing operations 有权
公开(公告)号：US09075727B2
公开(公告)日：2015-07-07
申请号：US13523523
申请日：2012-06-14
申请人： Michael F. Fee , Christine C. Jones , Arthur J. O'Neill , Diane L. Orf
发明人： Michael F. Fee , Christine C. Jones , Arthur J. O'Neill , Diane L. Orf
IPC分类号： G06F12/08 , G06F9/38
CPC分类号： G06F12/0864 , G06F9/3824 , G06F12/0846 , G06F12/0855 , Y02D10/13
摘要： A computer program product for reducing penalties for cache accessing operations is provided. The computer program product includes a tangible storage medium readable by a processing circuit and storing instructions for execution by the processing circuit for performing a method. The method includes respectively associating platform registers with cache arrays, loading control information and data of a store operation to be executed with respect to one or more of the cache arrays into the one or more of the platform registers respectively associated with the one or more of the cache arrays, and, based on the one or more of the cache arrays becoming available, committing the data from the one or more of the platform registers using the control information from the same platform registers to the one or more of the cache arrays.

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