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1. 发明授权

US07305596B2 Nonvolatile memory and nonvolatile memory apparatus 有权
标题翻译：非易失性存储器和非易失性存储器件
公开(公告)号：US07305596B2
公开(公告)日：2007-12-04
申请号：US11182781
申请日：2005-07-18
申请人： Satoshi Noda , Kenji Kozakai , Toru Matsushita , Yusuke Jono
发明人： Satoshi Noda , Kenji Kozakai , Toru Matsushita , Yusuke Jono
IPC分类号： G11C29/00
CPC分类号： G06F11/1068 , G11C11/5621 , G11C16/3454
摘要： To provide a technique which enables a load on a controller to be reduced by rapidly detecting n-bit errors during writing/erasing on a chip in ECC in a nonvolatile memory. A flash memory of the present invention, which is a nonvolatile memory that includes plural electrically erasable and writable nonvolatile memory cells and performs write-and-verify processing in a write operation on the nonvolatile memory cells, includes an ECC determination circuit that counts the number of bits of write error detected in the write-and-verify processing, and outputs the information, and a status register for holding pass/fail information of the write operation and the information about the number of bits of write error outputted from the ECC determination circuit.
摘要翻译：提供一种能够通过在非易失性存储器中的ECC中的芯片上的写入/擦除期间快速检测n位错误来降低控制器上的负载的技术。作为非易失性存储器的本发明的闪速存储器，其是包括多个电可擦写可写非易失性存储单元的非易失性存储器，并且在对非易失性存储单元的写入操作中进行写入验证处理包括：ECC确定电路，在写入和验证处理中检测到的写入错误的位，并且输出该信息，以及用于保持写入操作的通过/失败信息的状态寄存器以及关于从ECC确定输出的写入错误的位数的信息电路。

2. 发明申请

US20060026489A1 Nonvolatile memory and nonvolatile memory apparatus 有权
标题翻译：非易失性存储器和非易失性存储器件
公开(公告)号：US20060026489A1
公开(公告)日：2006-02-02
申请号：US11182781
申请日：2005-07-18
申请人： Satoshi Noda , Kenji Kozakai , Toru Matsushita , Yusuke Jono
发明人： Satoshi Noda , Kenji Kozakai , Toru Matsushita , Yusuke Jono
IPC分类号： G11C29/00
CPC分类号： G06F11/1068 , G11C11/5621 , G11C16/3454
摘要： To provide a technique which enables a load on a controller to be reduced by rapidly detecting n-bit errors during writing/erasing on a chip in ECC in a nonvolatile memory. A flash memory of the present invention, which is a nonvolatile memory that includes plural electrically erasable and writable nonvolatile memory cells and performs write-and-verify processing in a write operation on the nonvolatile memory cells, includes an ECC determination circuit that counts the number of bits of write error detected in the write-and-verify processing, and outputs the information, and a status register for holding pass/fail information of the write operation and the information about the number of bits of write error outputted from the ECC determination circuit.
摘要翻译：提供一种能够通过在非易失性存储器中的ECC中的芯片上的写入/擦除期间快速检测n位错误来降低控制器上的负载的技术。作为非易失性存储器的本发明的闪速存储器，其是包括多个电可擦写可写非易失性存储单元的非易失性存储器，并且在对非易失性存储单元的写入操作中进行写入验证处理包括：ECC确定电路，在写入和验证处理中检测到的写入错误的位，并且输出该信息，以及用于保持写入操作的通过/失败信息的状态寄存器和关于从ECC确定输出的写入错误的位数的信息电路。

3. 发明授权

US07301815B2 Semiconductor memory device comprising controllable threshould voltage dummy memory cells 有权
标题翻译：半导体存储器件包括可控制的电压虚拟存储器单元
公开(公告)号：US07301815B2
公开(公告)日：2007-11-27
申请号：US11180659
申请日：2005-07-14
申请人： Hideaki Kurata , Yoshihiro Ikeda , Masahiro Shimizu , Kenji Kozakai , Satoshi Noda
发明人： Hideaki Kurata , Yoshihiro Ikeda , Masahiro Shimizu , Kenji Kozakai , Satoshi Noda
IPC分类号： G11C11/34
CPC分类号： G11C8/14
摘要： The present invention provides a semiconductor memory device capable of preventing a defect caused by falling of a word line and deterioration in patterning precision due to disturbance of the pitch of word lines at an end of a memory block. Plural dummy word lines are disposed at an end of a memory block and a word driver is mounted for the dummy word line to control the threshold voltage of a dummy memory cell formed below the dummy word line. Also at the time of operating a memory area for storing data from the outside, a bias is applied to the dummy word line. The invention can prevent a defect caused by falling of a word line and deterioration in patterning precision due to disturbance of the pitches of word lines at an end of a memory block, and realize high yield and reliable operation.
摘要翻译：本发明提供了一种半导体存储器件，其能够防止由于字线下降引起的缺陷以及由于在存储器块的末端处的字线的间距的干扰而引起的图案精度的劣化。多个虚拟字线设置在存储器块的一端，并且为虚拟字线安装字驱动器以控制形成在虚拟字线下方的虚拟存储器单元的阈值电压。此外，在操作用于存储来自外部的数据的存储区域时，偏置被施加到虚拟字线。本发明可以防止由于字线下降引起的缺陷和由于记忆块末端的字线的间距的干扰导致的图案精度的劣化，并且实现了高产率和可靠的操作。

4. 发明授权

US07283408B2 Nonvolatile memory apparatus enabling data to be replaced prior to supplying read data and prior to supplying write data 有权
标题翻译：在提供读取数据之前和在提供写入数据之前使数据能被替换的非易失性存储装置
公开(公告)号：US07283408B2
公开(公告)日：2007-10-16
申请号：US11159303
申请日：2005-06-23
申请人： Tsutomu Nakajima , Satoshi Noda , Kenji Kozakai , Atsushi Tokairin
发明人： Tsutomu Nakajima , Satoshi Noda , Kenji Kozakai , Atsushi Tokairin
IPC分类号： G11C11/34
CPC分类号： G11C29/84 , G11C29/82
摘要： A nonvolatile memory apparatus which need not compare an access address with a faulty address every time for rescuing from any fault is to be provided. The apparatus has memory arrays, data registers for inputting and outputting data to and from the memory arrays, and control circuits. The control circuits, after transferring a plurality of sets of data from the memory arrays to the data registers in response to an instruction to read data, take out rescuing data out of the plurality of sets of data transferred to the data registers, and perform processing to replace with the taken-out rescuing data corresponding faulty addresses on the data register to enable the data on the data register to be supplied to the outside. When any faulty data in the read data are to be replaced with rescuing data on any data register to which data have been transferred from any memory array, read access addresses need not be checked whether or not they are faulty every time an access address is supplied from outside.
摘要翻译：提供不需要每次对任何故障进行抢救的访问地址与故障地址进行比较的非易失性存储装置。该装置具有存储器阵列，用于向存储器阵列输入数据和从存储器阵列输出数据的数据寄存器以及控制电路。控制电路在响应于读取数据的指令将多组数据从存储器阵列传送到数据寄存器之后，从传送到数据寄存器的多组数据中取出拯救数据，并执行处理取代数据寄存器上相应的故障地址的取出救援数据，使数据寄存器上的数据能够提供给外部。当数据从任何存储器阵列传送到任何数据寄存器上时，读取数据中的任何有故障的数据将被替换为数据寄存器中的数据，每次提供访问地址时，不需要检查读取访问地址是否有故障从外面。

5. 发明申请

US20060023554A1 Nonvolatile memory apparatus 审中-公开
标题翻译：非易失存储器
公开(公告)号：US20060023554A1
公开(公告)日：2006-02-02
申请号：US11167588
申请日：2005-06-28
申请人： Toru Matsushita , Kenji Kozakai , Hajime Tanabe , Takashi Horii
发明人： Toru Matsushita , Kenji Kozakai , Hajime Tanabe , Takashi Horii
IPC分类号： G11C8/00
CPC分类号： G11C16/32 , G11C2216/22
摘要： A read command having designated a bank, can be inputted from outside. A read command having designated a bank can be inputted from outside while an operation for reading from a memory array to a data buffer is being performed at the bank. Further, a read command having designated a bank is inputted from outside, and a buffer read command having designated a bank is inputted from outside while an operation for reading from a memory array to a data buffer is being performed at the bank, whereby reading from the data buffer of the bank to the outside is enabled.
摘要翻译：可以从外部输入具有指定银行的读取命令。从存储器阵列向数据缓冲器读取的操作正在银行执行时，可以从外部输入指定存储体的读取命令。此外，从外部输入指定了存储体的读取命令，并且从外部输入具有指定存储区的缓冲器读取命令，同时在存储体中执行从存储器阵列读取到数据缓冲器的操作，从而从银行到外部的数据缓冲区被启用。

6. 发明申请

US20060039230A1 Semiconductor memory device 有权
标题翻译：半导体存储器件
公开(公告)号：US20060039230A1
公开(公告)日：2006-02-23
申请号：US11180659
申请日：2005-07-14
申请人： Hideaki Kurata , Yoshihiro Ikeda , Masahiro Shimizu , Kenji Kozakai , Satoshi Noda
发明人： Hideaki Kurata , Yoshihiro Ikeda , Masahiro Shimizu , Kenji Kozakai , Satoshi Noda
IPC分类号： G11C8/02
CPC分类号： G11C8/14
摘要： An object of the present invention is to provide a semiconductor memory device capable of preventing a defect caused by falling of a word line and deterioration in patterning precision due to disturbance of the pitch of word lines at an end of a memory block. Plural dummy word lines are disposed at an end of a memory block, a word driver is mounted for the dummy word line to control the threshold voltage of a dummy memory cell formed below the dummy word line. Also at the time of operating a memory area for storing data from the outside, a bias is applied to the dummy word line. The invention can prevent a defect caused by falling of a word line and deterioration in patterning precision due to disturbance of the pitches of word lines at an end of a memory block, and realize high yield and reliably operation.
摘要翻译：本发明的目的是提供一种半导体存储器件，其能够防止由于字线的下降引起的缺陷以及由于在存储器块的端部处的字线的间距的干扰而导致的图案精度的劣化。多个虚拟字线设置在存储器块的末端，为虚拟字线安装字驱动器以控制形成在虚拟字线下面的虚拟存储器单元的阈值电压。此外，在操作用于存储来自外部的数据的存储区域时，偏置被施加到虚拟字线。本发明可以防止由于字线下降引起的缺陷和由于记忆块末端的字线的间距的干扰导致的图案精度的劣化，并且实现高产率和可靠的操作。

7. 发明申请

US20060002199A1 Nonvolatile memory apparatus 有权
标题翻译：非易失存储器
公开(公告)号：US20060002199A1
公开(公告)日：2006-01-05
申请号：US11159303
申请日：2005-06-23
申请人： Tsutomu Nakajima , Satoshi Noda , Kenji Kozakai , Atsushi Tokairin
发明人： Tsutomu Nakajima , Satoshi Noda , Kenji Kozakai , Atsushi Tokairin
IPC分类号： G11C7/00
CPC分类号： G11C29/84 , G11C29/82
摘要： A nonvolatile memory apparatus which need not compare an access address with a faulty address every time for rescuing from any fault is to be provided. The apparatus has memory arrays, data registers for inputting and outputting data to and from the memory arrays, and control circuits. The control circuits, after transferring a plurality of sets of data from the memory arrays to the data registers in response to an instruction to read data, take out rescuing data out of the plurality of sets of data transferred to the data registers, and perform processing to replace with the taken-out rescuing data corresponding faulty addresses on the data register to enable the data on the data register to be supplied to the outside. When any faulty data in the read data are to be replaced with rescuing data on any data register to which data have been transferred from any memory array, read access addresses need not be checked whether or not they are faulty every time an access address is supplied from outside.
摘要翻译：提供不需要每次对任何故障进行抢救的访问地址与故障地址进行比较的非易失性存储装置。该装置具有存储器阵列，用于向存储器阵列输入数据和从存储器阵列输出数据的数据寄存器以及控制电路。控制电路在响应于读取数据的指令将多组数据从存储器阵列传送到数据寄存器之后，从传送到数据寄存器的多组数据中取出拯救数据，并执行处理取代数据寄存器上相应的故障地址的取出救援数据，使数据寄存器上的数据能够提供给外部。当数据从任何存储器阵列传送到任何数据寄存器上时，读取数据中的任何有故障的数据将被替换为劫持数据时，每次提供访问地址时，都不需要检查读取访问地址是否有故障从外面。

8. 发明申请

US20080002480A1 Nonvolatile memory apparatus 审中-公开
标题翻译：非易失存储器
公开(公告)号：US20080002480A1
公开(公告)日：2008-01-03
申请号：US11896912
申请日：2007-09-06
申请人： Tsutomu Nakajima , Satoshi Noda , Kenji Kozakai , Atsushi Tokairin
发明人： Tsutomu Nakajima , Satoshi Noda , Kenji Kozakai , Atsushi Tokairin
IPC分类号： G11C7/10
CPC分类号： G11C29/84 , G11C29/82
摘要： A nonvolatile memory apparatus which need not compare an access address with a faulty address every time for rescuing from any fault is to be provided. The apparatus has memory arrays, data registers for inputting and outputting data to and from the memory arrays, and control circuits. The control circuits, after transferring a plurality of sets of data from the memory arrays to the data registers in response to an instruction to read data, take out rescuing data out of the plurality of sets of data transferred to the data registers, and perform processing to replace with the taken-out rescuing data corresponding faulty addresses on the data register to enable the data on the data register to be supplied to the outside. When any faulty data in the read data are to be replaced with rescuing data on any data register to which data have been transferred from any memory array, read access addresses need not be checked whether or not they are faulty every time an access address is supplied from outside.
摘要翻译：提供不需要每次对任何故障进行抢救的访问地址与故障地址进行比较的非易失性存储装置。该装置具有存储器阵列，用于向存储器阵列输入数据和从存储器阵列输出数据的数据寄存器以及控制电路。控制电路在响应于读取数据的指令将多组数据从存储器阵列传送到数据寄存器之后，从传送到数据寄存器的多组数据中取出拯救数据，并执行处理取代数据寄存器上相应的故障地址的取出救援数据，使数据寄存器上的数据能够提供给外部。当数据从任何存储器阵列传送到任何数据寄存器上时，读取数据中的任何有故障的数据将被替换为数据寄存器中的数据，每次提供访问地址时，不需要检查读取访问地址是否有故障从外面。

9. 发明申请

US20080055983A1 Semiconductor memory device comprising controllable threshold voltage dummy memory cells 审中-公开
标题翻译：半导体存储器件包括可控阈值电压虚拟存储器单元
公开(公告)号：US20080055983A1
公开(公告)日：2008-03-06
申请号：US11976299
申请日：2007-10-23
申请人： Hideaki Kurata , Yoshihiro Ikeda , Masahiro Shimizu , Kenji Kozakai , Satoshi Noda
发明人： Hideaki Kurata , Yoshihiro Ikeda , Masahiro Shimizu , Kenji Kozakai , Satoshi Noda
IPC分类号： G11C16/28
CPC分类号： G11C8/14
摘要： An object of the present invention is to provide a semiconductor memory device capable of preventing a defect caused by falling of a word line and deterioration in patterning precision due to disturbance of the pitch of word lines at an end of a memory block. Plural dummy word lines are disposed at an end of a memory block, a word driver is mounted for the dummy word line to control the threshold voltage of a dummy memory cell formed below the dummy word line. Also at the time of operating a memory area for storing data from the outside, a bias is applied to the dummy word line. The invention can prevent a defect caused by falling of a word line and deterioration in patterning precision due to disturbance of the pitches of word lines at an end of a memory block, and realize high yield and reliably operation.
摘要翻译：本发明的目的是提供一种半导体存储器件，其能够防止由于字线的下降引起的缺陷以及由于在存储器块的端部处的字线的间距的干扰而导致的图案精度的劣化。多个虚拟字线设置在存储器块的末端，为虚拟字线安装字驱动器以控制形成在虚拟字线下面的虚拟存储器单元的阈值电压。此外，在操作用于存储来自外部的数据的存储区域时，偏置被施加到虚拟字线。本发明可以防止由于字线下降引起的缺陷和由于记忆块末端的字线的间距的干扰导致的图案精度的劣化，并且实现高产率和可靠的操作。

10. 发明授权

US07933158B2 Nonvolatile memory 有权
标题翻译：非易失性存储器
公开(公告)号：US07933158B2
公开(公告)日：2011-04-26
申请号：US12896016
申请日：2010-10-01
申请人： Kenji Kozakai , Takeshi Nakamura , Tatsuya Ishii , Motoyasu Tsunoda , Shinya Iguchi , Junichi Maruyama
发明人： Kenji Kozakai , Takeshi Nakamura , Tatsuya Ishii , Motoyasu Tsunoda , Shinya Iguchi , Junichi Maruyama
IPC分类号： G11C5/14
CPC分类号： G06F12/0246 , G06F11/1068 , G06F12/06 , G06F2212/1036 , G11C16/04 , G11C16/10 , G11C16/349 , G11C29/44 , G11C29/76 , G11C2029/0409
摘要： For a nonvolatile memory permitting electrical writing and erasing of information to be stored, such as a flash memory, the load on the system developer is to be reduced, and it is to be made possible to avoid, even if such important data for the system as management and address translation information are damaged, an abnormal state in which the system becomes unable to operate. The nonvolatile memory is provided with a replacing function to replace a group of memory cells including defective memory cells which are incapable of normal writing or erasion with a group of memory cells including no defective memory cell, a numbers of rewrites averaging function to grasp the number of data rewrites in each group of memory cells and to so perform replacement of memory cell groups that there may arise no substantial difference in the number of rewrites among a plurality of memory cell groups, and an error correcting function to detect and correct any error in data stored in the memory array, wherein first address translation information deriving from the replacing function and second address translation information deriving from the numbers of rewrites averaging function are stored in respectively prescribed areas in the memory array, and the first address translation information and second address translation information concerning the same memory cell group are stored in a plurality of sets in a time series.
摘要翻译：对于允许电子写入和擦除要存储的信息（例如闪存）的非易失性存储器，系统开发者的负载将被减少，并且即使这样的系统的重要数据也可以避免由于管理和地址转换信息被破坏，系统无法运行的异常状态。非易失性存储器设置有替换功能，以替换包括不能正常写入或擦除的缺陷存储器单元的存储器单元组，所述存储器单元不包括不存在缺陷存储器单元的存储单元组，重写次数用于掌握数量的每个存储器单元组中的数据重写，并且因此执行存储单元组的替换，使得多个存储单元组之间的重写次数可能没有显着差异，以及用于检测和校正任何错误的错误校正功能存储在存储器阵列中的数据，其中从替换功能导出的第一地址转换信息和从重写平均函数导出的第二地址转换信息被存储在存储器阵列中的分别规定的区域中，并且第一地址转换信息和第二地址关于相同存储单元组的翻译信息是sto 以时间序列的多个集合中的红色。

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