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1. 发明授权

US5452260A Semiconductor memory circuit 失效
标题翻译：半导体存储电路
公开(公告)号：US5452260A
公开(公告)日：1995-09-19
申请号：US215487
申请日：1994-03-21
申请人： Katsuaki Matsui , Sampei Miyamoto , Tamihiro Ishimura
发明人： Katsuaki Matsui , Sampei Miyamoto , Tamihiro Ishimura
IPC分类号： G11C11/413 , G11C8/10 , G11C8/12 , G11C11/401 , G11C11/407 , G11C11/408 , G11C8/00
CPC分类号： G11C8/12 , G11C8/10
摘要： A semiconductor memory circuit selects one memory cell group in response to an address signal having block selection information, first and second significant bit information. First, to third memory cell blocks respectively have memory cell groups each including memory cells. First, to third decoder groups respectively have first decoders each coupled to one memory cell group in the first memory cell block, second decoders each coupled to one memory cell group in the second memory cell block, and third decoders each coupled to one memory cell group in the third memory cell block. First and second logic circuits respectively output a first common block selection signal with respect to the first and second memory cell blocks in response to the block selection information of the address signal, and a second common block selection signal with respect to the second and third memory cell blocks in response to the block selection information of the address signal. Third and fourth logic circuits respectively, in response to the second and first significant information, apply first common decode signals to the first and second decoder groups upon the first common block selection signal being outputted, and a plurality of second common decode signals to the second and third decoder groups upon the second common block selection signal being outputted. In response to the first and second common decode signals, a second decoder in the second decoder group is activated to select one memory cell group in the second memory cell block.
摘要翻译：半导体存储器电路响应具有块选择信息的地址信号，第一和第二有效位信息来选择一个存储单元组。首先，对第三存储单元块分别具有各自包含存储单元的存储单元组。首先，第三解码器组分别具有耦合到第一存储器单元块中的一个存储单元组的第一解码器，每个耦合到第二存储单元块中的一个存储单元组的第二解码器，以及每个耦合到一个存储单元组的第三解码器在第三个存储单元块中。第一和第二逻辑电路响应于地址信号的块选择信息分别输出关于第一和第二存储单元块的第一公共块选择信号，以及相对于第二和第三存储器的第二公共块选择信号响应于地址信号的块选择信息的单元块。第三和第四逻辑电路分别响应于第二和第一有效信息，在第一公共块选择信号被输出时，将第一公共解码信号应用于第一和第二解码器组，并将多个第二公共解码信号施加到第二公共解码信号第三解码器组输出第二公共块选择信号。响应于第一和第二公共解码信号，第二解码器组中的第二解码器被激活以选择第二存储器单元块中的一个存储器单元组。

2. 发明授权

US5818787A Semiconductor memory device 失效
公开(公告)号：US5818787A
公开(公告)日：1998-10-06
申请号：US833046
申请日：1997-04-03
申请人： Sampei Miyamoto , Tamihiro Ishimura
发明人： Sampei Miyamoto , Tamihiro Ishimura
IPC分类号： G11C11/41 , G11C7/10 , G11C11/401 , G11C11/409 , G11C11/4096 , G11C11/419 , G11C7/00
CPC分类号： G11C11/419 , G11C11/4096 , G11C7/1048
摘要： A semiconductor memory device according to the present invention comprise a plurality of arrays each supplied with a common column address signal. In an selected array, the potential of a data line is set to a potential corresponding to a potential supplied to a corresponding bit line in response to the potential of the bit line, the potential of the corresponding column address signal and the potential of a terminal. In non-selected array other than the selected array at this time, since the potential of a terminal in the non-selected array is set to a potential different from that of the terminal in the selected array, the potential of the data line remains unchanged irrespective of the column address signal.

3. 发明授权

US5394374A Semiconductor memory with improved transfer gate drivers 失效
标题翻译：具有改进的传输栅极驱动器的半导体存储器
公开(公告)号：US5394374A
公开(公告)日：1995-02-28
申请号：US25677
申请日：1993-03-03
申请人： Tamihiro Ishimura , Sampei Miyamoto
发明人： Tamihiro Ishimura , Sampei Miyamoto
IPC分类号： G11C11/409 , G11C7/06 , G11C11/401 , G11C11/407 , H03K3/356 , H03K17/10 , H03K19/017 , H03K17/06
CPC分类号： G11C7/06 , H03K17/102 , H03K3/356017 , H03K3/356113
摘要： A semiconductor memory has a sense amplifier array shared by first and second memory cell arrays, which are selected by first and second selection signals. Interconnections between the sense amplifier array and the first memory cell array are controlled by a first transfer gate signal. When the first selection signal is inactive, the second selection signal is coupled through a first transfer gate driver to become the first transfer gate signal. When the first selection signal is active, the first transfer gate signal is decoupled from the second selection signal and driven to an elevated level.
摘要翻译：半导体存储器具有通过第一和第二选择信号选择的第一和第二存储单元阵列共享的读出放大器阵列。读出放大器阵列和第一存储单元阵列之间的互连由第一传输门信号控制。当第一选择信号无效时，第二选择信号通过第一传输门驱动器耦合成为第一传输门信号。当第一选择信号有效时，第一传输门信号与第二选择信号解耦并被驱动到升高的电平。

4. 发明授权

US5521869A Semiconductor memory with improved transfer gate drivers 失效
公开(公告)号：US5521869A
公开(公告)日：1996-05-28
申请号：US351117
申请日：1994-11-30
申请人： Tamihiro Ishimura , Sampei Miyamoto
发明人： Tamihiro Ishimura , Sampei Miyamoto
IPC分类号： G11C11/409 , G11C7/06 , G11C11/401 , G11C11/407 , H03K3/356 , H03K17/10 , H03K19/017 , H03K17/06
CPC分类号： G11C7/06 , H03K17/102 , H03K3/356017 , H03K3/356113
摘要： A semiconductor memory has a sense amplifier array shared by first and second memory cell arrays, which are selected by first and second selection signals. Interconnections between the sense amplifier array and the first memory cell array are controlled by a first transfer gate signal. When the first selection signal is inactive, the second selection signal is coupled through a first transfer gate driver to become the first transfer gate signal. When the first selection signal is active, the first transfer gate signal is decoupled from the second selection signal and driven to an elevated level.

5. 发明授权

US4843258A Drive circuit with a ring oscillator for a semiconductor device 失效
标题翻译：具有用于半导体器件的环形振荡器的驱动电路
公开(公告)号：US4843258A
公开(公告)日：1989-06-27
申请号：US226087
申请日：1988-07-29
申请人： Masahumi Miyawaki , Sampei Miyamoto , Tamihiro Ishimura
发明人： Masahumi Miyawaki , Sampei Miyamoto , Tamihiro Ishimura
IPC分类号： G05F3/24 , G11C11/407 , G11C11/413 , H02M3/07 , H03K3/03 , H03K3/354
CPC分类号： G05F3/24 , H03K3/0315 , H03K3/354
摘要： A drive circuit for driving a semiconductor device includes a reference voltage level generator for outputting a reference voltage level which is associated with an input voltage level from an external power source. Supplied with the reference level, a ring oscillator oscillates a frequency signal having a predetermined frequency. A drive voltage level generator responds to the reference level and the frequency signal for producing a drive voltage level which is constantly substantially equal to the reference level in synchronism with the frequency signal. The drive voltage level generator feeds power from the external power source to the semiconductor device at the drive level, thereby driving the semiconductor load circuit.
摘要翻译：用于驱动半导体器件的驱动电路包括用于输出与来自外部电源的输入电压电平相关联的参考电压电平的参考电压电平发生器。提供参考电平，环形振荡器振荡具有预定频率的频率信号。驱动电压电平发生器响应参考电平和频率信号，以产生与频率信号同步地恒定地基本上等于参考电平的驱动电压电平。驱动电压电平发生器将来自外部电源的功率从驱动电平提供给半导体器件，由此驱动半导体负载电路。

6. 发明授权

US5699316A Semiconductor memory device 失效
标题翻译：半导体存储器件
公开(公告)号：US5699316A
公开(公告)日：1997-12-16
申请号：US542221
申请日：1995-10-12
申请人： Katsuaki Matsui , Tamihiro Ishimura , Sampei Miyamoto
发明人： Katsuaki Matsui , Tamihiro Ishimura , Sampei Miyamoto
IPC分类号： G11C11/41 , G11C7/10 , G11C11/401 , G11C11/409 , G11C11/4096 , G11C11/419 , G11C11/34 , H01L27/10
CPC分类号： G11C11/419 , G11C11/4096 , G11C7/1048
摘要： A semiconductor memory device according to the present invention comprise a plurality of arrays each supplied with a common column address signal. In an selected array, the potential of a data line is set to a potential corresponding to a potential supplied to a corresponding bit line in response to the potential of the bit line, the potential of the corresponding column address signal and the potential of a terminal. In non-selected array other than the selected array at this time, since the potential of a terminal in the non-selected array is set to a potential different from that of the terminal in the selected array, the potential of the data line remains unchanged irrespective of the column address signal.
摘要翻译：根据本发明的半导体存储器件包括多个阵列，每个阵列都具有公共列地址信号。在所选择的阵列中，响应于位线的电位，相应的列地址信号的电位和端子的电位，将数据线的电位设置为对应于提供给相应位线的电位的电位。在这个时候，除了所选择的阵列以外的非选择的阵列中，由于未选择的阵列中的终端的电位被设置为与所选择的阵列中的终端的电位不同的电位，所以数据线的电位保持不变不管列地址信号如何。

7. 发明授权

US5686752A Semiconductor device having a CMOS element as a buffer 失效
标题翻译：具有CMOS元件作为缓冲器的半导体器件
公开(公告)号：US5686752A
公开(公告)日：1997-11-11
申请号：US576614
申请日：1995-12-21
申请人： Tamihiro Ishimura , Sampei Miyamoto
发明人： Tamihiro Ishimura , Sampei Miyamoto
IPC分类号： G11C11/413 , G11C11/408 , G11C11/409 , H01L21/822 , H01L27/04 , H01L27/08 , H01L27/092 , H03K17/08 , H03K17/687 , H03K19/003 , H03K19/0175 , H03K19/0948 , H01L29/76 , H01L29/94
CPC分类号： H03K19/00315 , H01L27/0921
摘要： A PMOS 21 and an NMOS 22, which are connected in series between a power supply potential Vcc and a ground potential Vss, perform ON and Off operation in accordance with data signals G1 and G2 from an output buffer control circuit 40, and generate an output signal. A Vpp generating circuit 50 generates a potential Vpp higher than the power supply potential Vcc and a back gate bias of the PMOS 21 is set at the potential Vpp. Even if a latch-up trigger current due to a surge voltage is produced, the back gate bias of the PMOS 21 is set at Vpp and therefore a potential difference caused in an N type well resistor becomes small and a base potential of a parasitic bipolar transistor disposed between the N type well 2 and a substrate 1 becomes approximate to the potential Vpp. Accordingly, the current which flows into the substrate 1 is suppressed and a latch-up tolerance is improved.
摘要翻译：串联连接在电源电位Vcc和接地电位Vss之间的PMOS21和NMOS22根据来自输出缓冲器控制电路40的数据信号G1和G2进行ON和OFF操作，并产生输出信号。 Vpp发生电路50产生高于电源电位Vcc的电位Vpp，并且将PMOS21的背栅极偏置设置为电位Vpp。即使产生由于浪涌电压引起的闭锁触发电流，PMOS21的背栅极偏置被设定为Vpp，因此在N型阱电阻中引起的电位差变小，并且寄生双极性的基极电位配置在N型阱2和基板1之间的晶体管接近电位Vpp。因此，流入基板1的电流被抑制，并且提高了闩锁公差。

8. 发明授权

US5297105A Semiconductor memory circuit 失效
标题翻译：半导体存储电路
公开(公告)号：US5297105A
公开(公告)日：1994-03-22
申请号：US30708
申请日：1993-03-12
申请人： Katsuaki Matsui , Sampei Miyamoto , Tamihiro Ishimura
发明人： Katsuaki Matsui , Sampei Miyamoto , Tamihiro Ishimura
IPC分类号： G11C11/413 , G11C8/10 , G11C8/12 , G11C11/401 , G11C11/407 , G11C11/408 , G11C8/00
CPC分类号： G11C8/12 , G11C8/10
摘要： A semiconductor memory circuit selects one memory cell group in response to an address signal having block selection information, first and second significant bit information. First to third memory cell blocks respectively have memory cell groups each including memory cells. First to third decoder groups respectively have first decoders each coupled to one memory cell group in the first memory cell block, second decoders each coupled to one memory cell group in the second memory cell block, and third decoders each coupled to one memory cell group in the third memory cell block. First and second logic circuits respectively output a first common block selection signal with respect to the first and second memory cell blocks in response to the block selection information of the address signal, and a second common block selection signal with respect to the second and third memory cell blocks in response to the block selection information of the address signal. Third and fourth logic circuits respectively, in response to the second and the first information, apply first common decode signals to the first and second decoder groups upon the first common block selection signal being outputted, and a plurality of second common decode signals to the second and third decoder groups upon the second common block selection signal being outputted. In response to the first and second common decode signals, a second decoder in the second decoder group is activated so as to select one memory cell group in the second memory cell block.
摘要翻译：半导体存储器电路响应具有块选择信息的地址信号，第一和第二有效位信息来选择一个存储单元组。第一至第三存储单元块分别具有各自包括存储单元的存储单元组。第一到第三解码器组分别具有耦合到第一存储器单元块中的一个存储器单元组的第一解码器，每个耦合到第二存储器单元块中的一个存储器单元组的第二解码器和每个耦合到一个存储单元组的第三解码器第三个存储单元块。第一和第二逻辑电路响应于地址信号的块选择信息分别输出关于第一和第二存储单元块的第一公共块选择信号，以及相对于第二和第三存储器的第二公共块选择信号响应于地址信号的块选择信息的单元块。第三和第四逻辑电路分别响应于第二和第一信息，在输出第一公共块选择信号时将第一公共解码信号施加到第一和第二解码器组，并将多个第二公共解码信号施加到第二公共解码信号第三解码器组输出第二公共块选择信号。响应于第一和第二公共解码信号，第二解码器组中的第二解码器被激活，以便选择第二存储器单元块中的一个存储器单元组。

9. 发明授权

US5280453A Semiconductor memory device with noise reduction system 失效
标题翻译：具有降噪系统的半导体存储器件
公开(公告)号：US5280453A
公开(公告)日：1994-01-18
申请号：US705341
申请日：1991-05-24
申请人： Masahumi Miyawaki , Tamihiro Ishimura
发明人： Masahumi Miyawaki , Tamihiro Ishimura
IPC分类号： G11C11/4091 , G11C7/02
CPC分类号： G11C11/4091
摘要： An integrated circuit semiconductor memory device includes a memory array having memory cells. A sensing circuit is coupled to the memory cells through one of first and second bit lines. A first conductive line is for applying a first voltage potential to the sensing circuit, and a second conductive line is for applying a second voltage potential to the sensing circuit. A first field effect transistor is provided having first, second electrodes connected to the first conductive line, and a gate electrode connected to the second conductive line. The sensing circuit has a second field effect transistor and a third field effect transistor of an opposite channel type to the second field effect transistor. The first, second and gate electrodes of the first field effect transistor are formed substantially simultaneously with the first, second and gate electrodes of one of the second and third field effect transistors during manufacture of the integrated circuit semiconductor memory device. Also, the first conductive line is formed substantially simultaneously with the second conductive line during manufacture of the integrated circuit semiconductor memory device.
摘要翻译：集成电路半导体存储器件包括具有存储单元的存储器阵列。感测电路通过第一和第二位线之一耦合到存储器单元。第一导线用于向感测电路施加第一电压电位，第二导线用于向感测电路施加第二电压电位。提供第一场效应晶体管，其具有连接到第一导线的第一，第二电极和连接到第二导线的栅电极。感测电路具有与第二场效应晶体管相反通道类型的第二场效应晶体管和第三场效应晶体管。在集成电路半导体存储器件的制造期间，第一场效应晶体管的第一，第二和第二栅极电极基本上与第二和第三场效应晶体管之一的第一，第二和第二栅极电极形成同时。此外，在集成电路半导体存储器件的制造期间，第一导线基本上与第二导线形成同时形成。

10. 发明授权

US5091886A Dual current data bus clamp circuit of semiconductor memory device 失效
标题翻译：半导体存储器件的双电流数据总线钳位电路
公开(公告)号：US5091886A
公开(公告)日：1992-02-25
申请号：US706206
申请日：1991-05-28
申请人： Masahumi Miyawaki , Tamihiro Ishimura , Yoshio Ohtsuki
发明人： Masahumi Miyawaki , Tamihiro Ishimura , Yoshio Ohtsuki
IPC分类号： G11C11/409 , G11C7/10
CPC分类号： G11C7/1048
摘要： A data bus clamping circuit for use in a semiconductor memory device includes a memory cell array for storing data, a row address decoder for decoding row address signals taken in by a row address strobe signal to select memory cells in a row direction of the memory cell array, a column address decoder for decoding column address signals based on a column address decoder enabling signal to select memory cells in a column direction of the memory cell array, complementary data buses for transmitting data read out from the memory cell array, a data bus pull-up circuit for pulling up the complementary data buses, and a differential amplification type of readout circuit for amplifying on a differential basis data on the complementary data buses to output readout data. The data bus clamping circuit includes a first discharge circuit for discharging electric charge on the complementary data buses during an active period of the row address strobe signal, and a second discharge circuit for discharging electric charge on the complementary data buses with a discharge ability larger than the first discharge circuit, during a period of time from the time the active period of the row address strobe signal starts until the column address decoder enabling signal becomes active.

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