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1. 发明授权

US08351287B1 Bitline floating circuit for memory power reduction 有权
标题翻译：位线浮动电路用于存储器功率降低
公开(公告)号：US08351287B1
公开(公告)日：2013-01-08
申请号：US12976412
申请日：2010-12-22
申请人： Rohith Sood , Fabiano Fontana , Zheng Chen
发明人： Rohith Sood , Fabiano Fontana , Zheng Chen
IPC分类号： G11C7/00
CPC分类号： G11C11/419 , G11C7/12 , G11C11/412 , H03K19/0008 , H03K19/0016
摘要： Techniques are provided which may be used to reduce power consumed by memory circuits. In one example, a memory circuit includes a static random access memory (SRAM) cell. A pair of bitlines are connected to the SRAM cell. A precharge circuit is connected to the bitlines. The precharge circuit is adapted to precharge the bitlines immediately prior to read and write operations performed on the SRAM cell and float relative to the bitlines at other times.
摘要翻译：提供了可用于减少存储器电路消耗的功率的技术。在一个示例中，存储器电路包括静态随机存取存储器（SRAM）单元。一对位线连接到SRAM单元。预充电电路连接到位线。预充电电路适用于在对SRAM单元进行读和写操作之前立即对位线进行预充电，而在其它时间相对于位线浮动。

2. 发明授权

US08553463B1 Voltage discharge circuit having divided discharge current 有权
标题翻译：放电电路具有分压放电电流
公开(公告)号：US08553463B1
公开(公告)日：2013-10-08
申请号：US13052142
申请日：2011-03-21
申请人： Robert Gary Pollachek , Loren Mclaury , Fabiano Fontana
发明人： Robert Gary Pollachek , Loren Mclaury , Fabiano Fontana
IPC分类号： G11C16/06
CPC分类号： G11C16/06 , G11C16/16
摘要： In one embodiment, a voltage discharge (VD) system has a slow VD subsystem that provides two concurrent discharge current paths to at least begin to discharge both positive and negative voltages: a first path from the positive-voltage node to ground and a second path from the positive-voltage node to the negative-voltage node. In addition to this relatively slow VD subsystem, the VD system can also have a conventional fast VD subsystem that is turned on after the slow VD subsystem has reduced the positive and negative voltages to some degree (e.g., half of each charge removed). Such a VD system can eliminate dangerous overshoot conditions, even when control-signal skew is present.
摘要翻译：在一个实施例中，电压放电（VD）系统具有缓慢的VD子系统，其提供两个并发的放电电流路径，以至少开始放电正电压和负电压：从正电压节点到地的第一路径和第二路径从正电压节点到负电压节点。除了这种相对较慢的VD子系统之外，VD系统还可以具有传统的快速VD子系统，其在慢VD子系统在一定程度上减小正电压和负电压（例如，每个电荷被移除的一半）之后被接通。即使存在控制信号偏移，这种VD系统也可以消除危险的过冲条件。

3. 再颁专利

USRE40311E1 Zero-power programmable memory cell 有权
标题翻译：零功率可编程存储单元
公开(公告)号：USRE40311E1
公开(公告)日：2008-05-13
申请号：US11206282
申请日：2005-08-17
申请人： Sunil D. Mehta , Fabiano Fontana
发明人： Sunil D. Mehta , Fabiano Fontana
IPC分类号： G11C16/04
CPC分类号： G11C16/045 , G11C16/0441
摘要： A zero-power electrically erasable and programmable memory cell is implemented in CMOS (complementary metal oxide semiconductor) technology. A P-channel sense transistor has a source coupled to a first voltage generator, and an N-channel sense transistor has a source coupled to a second voltage generator. The drains of the P-channel and N-channel sense transistors are coupled together to form an output of the memory cell, and the gates of the P-channel and N-channel sense transistor are coupled together to form a floating gate of the memory cell. In an example embodiment of the present invention, each of the first and second voltage generators are variable voltage generators that apply a positive voltage at the respective source of each of the P-channel and N-channel sense transistors during the erase operation and/or that apply a ground or negative voltage at the respective source of each of the P-channel and N-channel sense transistors during the program operation. In another embodiment of the present invention, a magnitude of the respective threshold voltage of each of the P-channel and N-channel sense transistors is higher than a magnitude of a threshold voltage of standard process P-channel and N-channel transistors. With such a higher threshold voltage, the P-channel and N-channel sense transistors do not erroneously turn on to dissipate power during the read operation, to ensure that the memory cell is a zero-power memory cell.
摘要翻译：在CMOS（互补金属氧化物半导体）技术中实现零功率电可擦除和可编程存储器单元。 P沟道感测晶体管具有耦合到第一电压发生器的源极，并且N沟道感测晶体管具有耦合到第二电压发生器的源极。 P沟道和N沟道感测晶体管的漏极耦合在一起以形成存储单元的输出，并且P沟道和N沟道读出晶体管的栅极耦合在一起以形成存储器的浮置栅极细胞。在本发明的示例性实施例中，第一和第二电压发生器中的每一个是在擦除操作期间在每个P沟道和N沟道读出晶体管的各个源处施加正电压的可变电压发生器和/或其在编程操作期间在每个P沟道和N沟道感测晶体管的相应源处施加接地或负电压。在本发明的另一个实施例中，每个P沟道和N沟道检测晶体管的相应阈值电压的大小都高于标准工艺P沟道和N沟道晶体管的阈值电压的幅度。利用这种较高的阈值电压，P信道和N沟道检测晶体管在读取操作期间不会错误地导通以耗散功率，以确保存储器单元是零功率存储单元。

4. 发明申请

US20070030736A1 Variable source resistor for flash memory 审中-公开
标题翻译：闪存可变源电阻
公开(公告)号：US20070030736A1
公开(公告)日：2007-02-08
申请号：US11196093
申请日：2005-08-03
申请人： Fabiano Fontana , Steven Fong
发明人： Fabiano Fontana , Steven Fong
IPC分类号： G11C16/04 , G11C11/34
CPC分类号： G11C16/24
摘要： In one embodiment of the invention, a flash memory is provided that includes: a plurality of flash memory cells sharing a common drain node and a common source node; and a current source that controls the current into the common source node.
摘要翻译：在本发明的一个实施例中，提供一种闪速存储器，其包括：多个共享共同漏极节点和公共源节点的闪存单元; 以及将电流控制到公共源节点的当前源。

5. 发明授权

US5982683A Enhanced method of testing semiconductor devices having nonvolatile elements 失效
标题翻译：具有非易失性元件的半导体器件测试的增强方法
公开(公告)号：US5982683A
公开(公告)日：1999-11-09
申请号：US046404
申请日：1998-03-23
申请人： James A. Watson , Fabiano Fontana , Jenny Chui , Steve Choi , Benjamin Lau
发明人： James A. Watson , Fabiano Fontana , Jenny Chui , Steve Choi , Benjamin Lau
IPC分类号： G11C29/10 , G11C7/00
CPC分类号： G11C29/10
摘要： An enhanced method of testing semiconductor devices having nonvolatile elements by determining regions of the semiconductor having differing orders of probability that a defect will occur. The enhanced method of testing includes testing of regions from the highest probability to the lowest probability of having a defect. Nonvolatile memory elements in the region being tested are placed in a high impedance state, bypass circuits in the region being tested are activated to bypass the nonvolatile memory elements that control the state of elements in the region being tested and test vectors are applied to the elements that are controlled by the bypassed nonvolatile memory elements. This procedure is repeated for the next untested region having the highest probability of having a defect until all regions have been tested.
摘要翻译：通过确定具有不同发生故障概率的半导体区域来测试具有非易失性元件的半导体器件的增强方法。增强的测试方法包括从最高概率到具有缺陷的最低概率的区域的测试。被测试区域中的非易失性存储元件被置于高阻抗状态，被测试区域中的旁路电路被激活以绕过控制待测区域中的元件状态的非易失性存储元件，测试矢量被应用于元件由旁路非易失性存储元件控制。对具有最大概率的缺陷的下一个未测试区域重复该过程，直到所有区域都已被测试为止。

6. 发明授权

US07724029B1 Power management for integrated circuits such as programmable logic devices 有权
标题翻译：集成电路的电源管理，如可编程逻辑器件
公开(公告)号：US07724029B1
公开(公告)日：2010-05-25
申请号：US12502141
申请日：2009-07-13
申请人： Satwant Singh , Fabiano Fontana , David Chang
发明人： Satwant Singh , Fabiano Fontana , David Chang
IPC分类号： H03K19/173
CPC分类号： H03K19/17744 , H03K19/17784
摘要： In one embodiment, an integrated circuit (IC) such as a programmable logic device includes a plurality of IC input terminals and an input buffer having a buffer input terminal and a buffer output terminal. A multiplexer is adapted to selectively couple an IC input terminal to the buffer input terminal or to couple the buffer output terminal to the buffer input terminal.
摘要翻译：在一个实施例中，诸如可编程逻辑器件的集成电路（IC）包括多个IC输入端子和具有缓冲器输入端子和缓冲器输出端子的输入缓冲器。复用器适于选择性地将IC输入端子耦合到缓冲器输入端子或将缓冲器输出端子耦合到缓冲器输入端子。

7. 发明申请

US20060145238A1 Diode structure for word-line protection in a memory circuit 审中-公开
标题翻译：存储器电路中字线保护的二极管结构
公开(公告)号：US20060145238A1
公开(公告)日：2006-07-06
申请号：US11029950
申请日：2005-01-05
申请人： Fabiano Fontana , Steven Fong , Sunil Mehta , Yongzhong Hu
发明人： Fabiano Fontana , Steven Fong , Sunil Mehta , Yongzhong Hu
IPC分类号： H01L29/788
CPC分类号： H01L27/115 , G11C16/04 , H01L27/0255
摘要： One embodiment of the invention is an integrated circuit having: (i) an array of flash transistors formed on a substrate and arranged in one or more rows, each flash transistor having a control gate, wherein, in each row, the control gates are connected to a word line; and (ii) for each word line, at least one diode structure formed on the substrate and having first and second diodes, each diode having a cathode and an anode, wherein the word line is connected to the cathode of the first diode and to the anode of the second diode.
摘要翻译：本发明的一个实施例是一种集成电路，其具有：（i）形成在衬底上并布置成一行或多行的闪存晶体管阵列，每个闪存晶体管具有控制栅极，其中在每行中连接控制栅极到字线和（ii）对于每个字线，形成在所述衬底上并具有第一和第二二极管的至少一个二极管结构，每个二极管具有阴极和阳极，其中所述字线连接到所述第一二极管的阴极和第二二极管的阳极。

8. 发明授权

US06838904B1 Enhanced CPLD macrocell module having selectable bypass of steering-based resource allocation 有权
标题翻译：增强的CPLD宏单元模块具有基于转向的资源分配的可选旁路
公开(公告)号：US06838904B1
公开(公告)日：2005-01-04
申请号：US10640828
申请日：2003-08-13
申请人： Om P. Agrawal , Fabiano Fontana , Gilles M. Bosco
发明人： Om P. Agrawal , Fabiano Fontana , Gilles M. Bosco
IPC分类号： H03K19/177
CPC分类号： H03K19/17748 , H03K19/17728 , H03K19/17736
摘要： Structures and techniques are provided for allowing one or more of the following actions to occur within a Complex Programmable Logic Device (CPLD): (1) Elective use of a fast, allocator-bypassing path (e.g., a fast 5-PT path) in combination with in-block simple or super-allocation; (2) Elective use of an OSM-bypassing path for signals that do not need pin-consistency; (3) Automatic re-routing of output enable signals that corresponding to output signals which are re-routed for pin-consistency purposes; (4) Global distribution of globally-usable output enable signals; (5) Elective use of two-stage steering to develop complex sum-of-clusters terms where fast path or simple allocation will not be sufficient; and (6) Use of unidirectional super-allocation with stage-2 wrap-around in designs having about 24 or less macrocell units per logic block. Techniques are provided for concentrating the development of complex function signals (e.g., ≦80PTs) within singular logic blocks so that the development of such complex function signals does not consume inter-block interconnect resources. One CPLD configuring method includes the machine-implemented steps of first identifying middle-complexity functions that are achievable by combined simple or super-allocation based development in one logic block and fast-path completion in the same or a second logic block; and configuring the CPLD to realize one or more of the functions identified in the first identification step by simple or super-allocation based development in one logic block and fast-path completion in the same or a second logic block.

9. 发明授权

US6133769A Phase locked loop with a lock detector 有权
标题翻译：带锁定检测器的锁相环
公开(公告)号：US6133769A
公开(公告)日：2000-10-17
申请号：US201081
申请日：1998-11-30
申请人： Fabiano Fontana , Mathew Anton Rybicki , Ammisetti V. Prasad
发明人： Fabiano Fontana , Mathew Anton Rybicki , Ammisetti V. Prasad
IPC分类号： H03L7/089 , H03L7/095 , H03L7/18 , H03L7/06
CPC分类号： H03L7/18 , H03L7/0891 , H03L7/095
摘要： A phase locked loop comprises a phase locking circuit (16) which includes a phase/frequency detector (18) capable of outputting up and down signals to a charge pump (22) through separate signal paths (24, 26) and a phase lock detector (34) coupled to receive the up and down signals. The phase lock detector (34) determines the difference between the up and down signals from the phase/frequency detector (18) and in response generates a phase lock indicator signal PLL.sub.-- OUT.
摘要翻译：锁相环包括相位锁定电路（16），该锁相电路包括能够通过分离的信号路径（24,26）向电荷泵（22）输出上下信号的相位/频率检测器（18）和相位锁定检测器（34），用于接收上下信号。相位锁定检测器（34）确定来自相位/频率检测器（18）的上升和下降信号之间的差异，并且响应产生锁相指示器信号PLL-OUT。

10. 发明授权

US5568066A Sense amplifier and or gate for a high density programmable logic device 失效
标题翻译：用于高密度可编程逻辑器件的感应放大器和/或门
公开(公告)号：US5568066A
公开(公告)日：1996-10-22
申请号：US341432
申请日：1994-11-17
申请人： Bradley A. Sharpe-Geisler , Fabiano Fontana
发明人： Bradley A. Sharpe-Geisler , Fabiano Fontana
IPC分类号： H03K19/0185 , H03K19/177 , H03K19/173
CPC分类号： H03K19/17708 , H03K19/018521
摘要： A high density programmable logic device (PLD) having sense amplifiers and OR gates configured to increase operation speed and reduce transistor count from previous circuits as well as to provide a selectable power down mode on a macrocell-by-macrocell basis. The sense amplifiers include a single cascode in the data path connecting a product term to the OR gates. The OR gates utilize a plurality of source follower transistors followed by pass gates to provide logic allocation enabling the sense amplifier outputs to be reduced from the 0.0 V-5.0 V CMOS rails to increase switching speed while reducing overall transistor count. Amplifying inverters normally provided in the sense amplifiers to provide the CMOS rail-to-rail switching and which would require complex feedback for providing power down on a macrocell-by-macrocell basis are moved forward into OR output circuits. Power down on a macrocell-by-macrocell basis is provided by selectively sizing the amplifying inverters in the OR output circuits.
摘要翻译：具有读出放大器和OR门的高密度可编程逻辑器件（PLD）被配置为增加操作速度并减少来自先前电路的晶体管数量，以及在逐个宏单元的基础上提供可选择的掉电模式。读出放大器包括将产品项连接到OR门的数据路径中的单个共源共栅。 OR门使用多个源极跟随器晶体管，随后是通过栅极，以提供逻辑分配，使得能够从0.0V-5.0V CMOS轨道减小读出放大器的输出，从而提高开关速度，同时降低总体晶体管数量。通常在读出放大器中提供的放大反相器，以提供CMOS轨到轨开关，并且这将需要复杂的反馈以便在宏单元逐宏基础上提供掉电向前进入OR输出电路。通过在OR输出电路中选择性地调整放大逆变器来提供基于宏小区的宏单元的功率下降。

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