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    • 1. 发明授权
    • Voltage discharge circuit having divided discharge current
    • 放电电路具有分压放电电流
    • US08553463B1
    • 2013-10-08
    • US13052142
    • 2011-03-21
    • Robert Gary PollachekLoren MclauryFabiano Fontana
    • Robert Gary PollachekLoren MclauryFabiano Fontana
    • G11C16/06
    • G11C16/06G11C16/16
    • In one embodiment, a voltage discharge (VD) system has a slow VD subsystem that provides two concurrent discharge current paths to at least begin to discharge both positive and negative voltages: a first path from the positive-voltage node to ground and a second path from the positive-voltage node to the negative-voltage node. In addition to this relatively slow VD subsystem, the VD system can also have a conventional fast VD subsystem that is turned on after the slow VD subsystem has reduced the positive and negative voltages to some degree (e.g., half of each charge removed). Such a VD system can eliminate dangerous overshoot conditions, even when control-signal skew is present.
    • 在一个实施例中,电压放电(VD)系统具有缓慢的VD子系统,其提供两个并发的放电电流路径,以至少开始放电正电压和负电压:从正电压节点到地的第一路径和第二路径 从正电压节点到负电压节点。 除了这种相对较慢的VD子系统之外,VD系统还可以具有传统的快速VD子系统,其在慢VD子系统在一定程度上减小正电压和负电压(例如,每个电荷被移除的一半)之后被接通。 即使存在控制信号偏移,这种VD系统也可以消除危险的过冲条件。
    • 2. 发明授权
    • Constant impedance, low noise CMOS buffer
    • 恒定阻抗,低噪声CMOS缓冲器
    • US6051995A
    • 2000-04-18
    • US151942
    • 1998-09-11
    • Robert Gary Pollachek
    • Robert Gary Pollachek
    • H03K19/0175H03K17/16H03K19/0185
    • H03K17/164
    • A low noise CMOS buffer has been provided which includes the advantages of having a stable load impedance and a linear-ramped current waveform at the output. The buffer adds waveform shaping transistors to delay the turn on of the driver circuits, and to shape the voltage and current waveforms of the drivers. These critically placed waveform shaping transistors accomplish the function of turning off the drivers in a manner to encourage an opposite polarity linear ramp current waveform at the buffer output. A method of using waveform shaping transistors to form a stable output impedance and a linear-ramped current waveform at the output of a buffer is also provided.
    • 已经提供了一种低噪声CMOS缓冲器,其包括在输出端具有稳定的负载阻抗和线性斜坡电流波形的优点。 缓冲器添加波形整形晶体管以延迟驱动器电路的导通,并且形成驱动器的电压和电流波形。 这些临界放置的波形整形晶体管以一种促进缓冲器输出端的相反极性线性斜坡电流波形的方式实现关断驱动器的功能。 还提供了一种在缓冲器的输出端使用波形整形晶体管以形成稳定的输出阻抗和线性斜坡电流波形的方法。
    • 3. 发明授权
    • Low-voltage current sense amplifier
    • 低压电流检测放大器
    • US08654600B1
    • 2014-02-18
    • US13037703
    • 2011-03-01
    • Robert Gary Pollachek
    • Robert Gary Pollachek
    • G11C7/02G11C7/00
    • G11C7/06G11C7/02G11C7/062G11C7/067G11C16/26G11C2207/063
    • In one embodiment, an integrated programmable device has a plurality of current sense amplifiers for reading data from non-volatile memory and a reference generator that provides common bias reference voltages to the sense amplifiers. The sense amplifiers can read data from the non-volatile memory at low power supply voltage levels (e.g., 750 mV) relative to the nominal supply level (e.g., 1.2V). Each sense amplifier has a trans-impedance amplifier that converts a memory bit-line current into a voltage level indicative of whether a selected memory cell is programmed or erased. The trans-impedance amplifier has a current mirror with a high-threshold regeneration device that lowers the sense amplifier's range of operating voltages. Each sense amplifier also has a level-shifted inverter that further lowers the sense amplifier's operating voltage range. The reference generator generates a ground-referenced bias voltage that each sense amplifier or group of sense amplifiers converts into a local, supply-referenced bias voltage.
    • 在一个实施例中,集成可编程器件具有用于从非易失性存储器读取数据的多个电流检测放大器和向读出放大器提供公共偏置参考电压的参考发生器。 读出放大器可以以相对于额定电源电平(例如,1.2V)的低电源电压电平(例如,750mV))从非易失性存储器读取数据。 每个读出放大器具有跨阻抗放大器,其将存储器位线电流转换成指示所选存储单元是否被编程或擦除的电压电平。 跨阻放大器具有具有高阈值再生装置的电流镜,降低了读出放大器的工作电压范围。 每个读出放大器还具有电平移位的反相器,进一步降低读出放大器的工作电压范围。 参考发生器产生接地参考偏置电压,每个读出放大器或读出放大器组转换成本地的电源参考偏置电压。