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1. 发明申请

US20050188923A1 Substrate carrier for parallel wafer processing reactor 审中-公开
标题翻译：用于平行晶片处理反应器的基板载体
公开(公告)号：US20050188923A1
公开(公告)日：2005-09-01
申请号：US10966245
申请日：2004-10-15
申请人： Robert Cook , Ronald Stevens , Peter Schwartz , Cesar Tejamo , Vebjorn Nilsen , Gabriel Ormonde , Ajit Paranjpe , Somnath Nag , Michael Patten
发明人： Robert Cook , Ronald Stevens , Peter Schwartz , Cesar Tejamo , Vebjorn Nilsen , Gabriel Ormonde , Ajit Paranjpe , Somnath Nag , Michael Patten
IPC分类号： C23C16/24 , C23C16/34 , C23C16/44 , C23C16/455 , C23C16/458 , C23C16/46 , C23C16/48 , C23C16/509 , C23C16/54 , H01J37/32 , H01L21/00 , H01L21/205 , H01L21/318 , H01L21/673 , H01L21/677 , C23C16/00
CPC分类号： H01L21/67303 , C23C16/4584 , C23C16/54 , H01J37/32082 , H01J37/32733 , H01J2237/2001 , H01L21/02529 , H01L21/02532 , H01L21/0262 , H01L21/02658 , H01L21/3185 , H01L21/67017 , H01L21/67069 , H01L21/67115 , H01L21/67309 , H01L21/67346 , H01L21/67383
摘要： A substrate carrier for a parallel wafer processing reactor supports a plurality of substrates. The substrate carrier includes a plurality of susceptors, which may be thermal plates or annular rings that are arranged horizontally in a vertical stack. The substrates are mounted between pairs of susceptors on two or more supports provided around the outer periphery of the susceptors. The number of substrates mounted between each pair of susceptors may the same or different but is two or more between at least one pair of susceptors.
摘要翻译：用于平行晶片处理反应器的衬底载体支撑多个衬底。衬底载体包括多个基座，其可以是在垂直堆叠中水平布置的热板或环形环。衬底被安置在两个或更多个支撑体之间的基座对之间，所述支撑件设置在基座的外周周围。安装在每对感受体之间的衬底的数量可以相同或不同，但是在至少一对感受器之间是两个或更多个。

2. 发明申请

US20060084283A1 Low temperature sin deposition methods 审中-公开
标题翻译：低温沉积法
公开(公告)号：US20060084283A1
公开(公告)日：2006-04-20
申请号：US10970317
申请日：2004-10-20
申请人： Ajit Paranjpe , Kangzhan Zhang , Brendan McDougall , Wayne Vereb , Michael Patten , Alan Goldman , Somnath Nag
发明人： Ajit Paranjpe , Kangzhan Zhang , Brendan McDougall , Wayne Vereb , Michael Patten , Alan Goldman , Somnath Nag
IPC分类号： H01L21/31
CPC分类号： H01L21/0217 , C23C16/345 , C23C16/4412 , C23C16/45525 , H01L21/02211 , H01L21/0228 , H01L21/3185
摘要： A silicon nitride layer is deposited on a substrate within a processing region by introducing a silicon containing precursor into the processing region, exhausting gases in the processing region including the silicon containing precursor while uniformly, gradually reducing a pressure of the processing region, introducing a nitrogen containing precursor into the processing region, and exhausting gases in the processing region including the nitrogen containing precursor while uniformly, gradually reducing a pressure of the processing region. During the steps of exhausting, the slope of the pressure decrease with respect to time is substantially constant.
摘要翻译：通过将含硅前体引入加工区域，在均匀地引入包含含硅前体的处理区域中的气体中逐渐降低加工区域的压力，引入氮气，在处理区域内的基板上沉积氮化硅层并且在均匀地排出包含含氮前体的处理区域中的气体，逐渐降低加工区域的压力。在排气步骤中，压力相对于时间的斜率减小是基本恒定的。

3. 发明申请

US20080318441A1 PROCESS SEQUENCE FOR DOPED SILICON FILL OF DEEP TRENCHES 有权
标题翻译： DEEP TRENCHES DOPED SILICON FILL的工艺顺序
公开(公告)号：US20080318441A1
公开(公告)日：2008-12-25
申请号：US12199402
申请日：2008-08-27
申请人： Ajit Paranjpe , Somnath Nag
发明人： Ajit Paranjpe , Somnath Nag
IPC分类号： H01L21/762
CPC分类号： C23C16/045 , C23C16/24 , H01L21/76232 , H01L29/66181
摘要： A method for void free filling with in-situ doped amorphous silicon of a deep trench structure is provided in which a first fill is carried out in a way so that film deposition occurs from the bottom of the trench upwards, with step coverage well in excess of 100%. In a second fill step, deposition conditions are changed to reduce the impact of dopant on deposition rate, and deposition proceeds at a rate which exceeds the deposition rate of the first fill. In an application of this method to the formation of deep trench capacitor structures, the intermediate steps further including the capping of the void free filled trench with a thick layer of amorphous silicon, planarization of the wafer thereafter, followed by a thermal anneal to re-distribute the dopant within the filled trench. Thereafter, additional steps can be performed to complete the formation of the capacitor structure.
摘要翻译：提供了一种用于无缝填充深沟槽结构的原位掺杂非晶硅的方法，其中第一填充以使得膜沉积从沟槽底部向上发生的方式进行，其中步骤覆盖良好地超过 100％。在第二填充步骤中，改变沉积条件以减少掺杂剂对沉积速率的影响，并且沉积以超过第一填充的沉积速率的速率进行。在这种方法应用于深沟槽电容器结构的形成中，中间步骤进一步包括无孔填充沟槽的覆盖，其中厚层非晶硅，之后对晶片进行平面化，随后进行热退火，在填充的沟槽内分布掺杂剂。此后，可以执行附加步骤以完成电容器结构的形成。

4. 发明授权

US07446366B2 Process sequence for doped silicon fill of deep trenches 有权
标题翻译：深沟槽掺杂硅填充工艺顺序
公开(公告)号：US07446366B2
公开(公告)日：2008-11-04
申请号：US11420893
申请日：2006-05-30
申请人： Ajit Paranjpe , Somnath Nag
发明人： Ajit Paranjpe , Somnath Nag
IPC分类号： H01L27/108 , H01L29/76 , H01L29/94 , H01L31/119
CPC分类号： C23C16/045 , C23C16/24 , H01L21/76232 , H01L29/66181
摘要： A method for void free filling with in-situ doped amorphous silicon of a deep trench structure is provided in which a first fill is carried out in at a temperature, pressure and dopant to silane ratio such that film deposition occurs from the bottom of the trench upwards. By way of this first fill, step coverages well in excess 100% are achieved. In the second fill step, deposition is carried out under changed conditions so as to reduce the impact of dopant on deposition rate, whereby trench fill is completed at a deposition rate which exceeds the deposition rate of the first fill. In an application of this method to the formation of deep trench capacitor structures, the intermediate steps further including the capping of the void free filled trench with a thick layer of amorphous silicon, planarization of the wafer thereafter, followed by a thermal anneal to re-distribute the dopant within the filled trench. Thereafter, additional steps can be performed to complete the formation of the capacitor structure.
摘要翻译：提供了一种无空隙填充深沟槽结构的原位掺杂非晶硅的方法，其中在硅烷比例的温度，压力和掺杂剂下进行第一次填充，使得从沉积的底部发生膜沉积向上。通过这个第一次填充，达到100％以上的步骤覆盖率。在第二填充步骤中，在改变的条件下进行沉积，以减少掺杂剂对沉积速率的影响，由此以超过第一填充物的沉积速率的沉积速率完成沟槽填充。在这种方法应用于深沟槽电容器结构的形成中，中间步骤进一步包括无孔填充沟槽的覆盖，其中厚层非晶硅，之后对晶片进行平面化，随后进行热退火，在填充的沟槽内分布掺杂剂。此后，可以执行附加步骤以完成电容器结构的形成。

5. 发明申请

US20060128139A1 Process sequence for doped silicon fill of deep trenches 有权
公开(公告)号：US20060128139A1
公开(公告)日：2006-06-15
申请号：US11011550
申请日：2004-12-14
申请人： Ajit Paranjpe , Somnath Nag
发明人： Ajit Paranjpe , Somnath Nag
IPC分类号： H01L21/4763
CPC分类号： C23C16/045 , C23C16/24 , H01L21/76232 , H01L29/66181
摘要： A method for void free filling with in-situ doped amorphous silicon of a deep trench structure is provided in which a first fill is carried out in at a temperature, pressure and dopant to silane ratio such that film deposition occurs from the bottom of the trench upwards. By way of this first fill, step coverages well in excess 100% are achieved. In the second fill step, deposition is carried out under changed conditions so as to reduce the impact of dopant on deposition rate, whereby trench fill is completed at a deposition rate which exceeds the deposition rate of the first fill. In an application of this method to the formation of deep trench capacitor structures, the intermediate steps further including the capping of the void free filled trench with a thick layer of amorphous silicon, planarization of the wafer thereafter, followed by a thermal anneal to re-distribute the dopant within the filled trench. Thereafter, additional steps can be performed to complete the formation of the capacitor structure.

6. 发明授权

US07109097B2 Process sequence for doped silicon fill of deep trenches 有权
标题翻译：深沟槽掺杂硅填充工艺顺序
公开(公告)号：US07109097B2
公开(公告)日：2006-09-19
申请号：US11011550
申请日：2004-12-14
申请人： Ajit Paranjpe , Somnath Nag
发明人： Ajit Paranjpe , Somnath Nag
IPC分类号： H01L21/04
CPC分类号： C23C16/045 , C23C16/24 , H01L21/76232 , H01L29/66181
摘要： A method for void free filling with in-situ doped amorphous silicon of a deep trench structure is provided in which a first fill is carried out in at a temperature, pressure and dopant to silane ratio such that film deposition occurs from the bottom of the trench upwards. By way of this first fill, step coverages well in excess 100% are achieved. In the second fill step, deposition is carried out under changed conditions so as to reduce the impact of dopant on deposition rate, whereby trench fill is completed at a deposition rate which exceeds the deposition rate of the first fill. In an application of this method to the formation of deep trench capacitor structures, the intermediate steps further including the capping of the void free filled trench with a thick layer of amorphous silicon, planarization of the wafer thereafter, followed by a thermal anneal to re-distribute the dopant within the filled trench. Thereafter, additional steps can be performed to complete the formation of the capacitor structure.
摘要翻译：提供了一种无空隙填充深沟槽结构的原位掺杂非晶硅的方法，其中在硅烷比例的温度，压力和掺杂剂下进行第一次填充，使得从沉积的底部发生膜沉积向上。通过这个第一次填充，达到100％以上的步骤覆盖率。在第二填充步骤中，在改变的条件下进行沉积，以减少掺杂剂对沉积速率的影响，由此以超过第一填充物的沉积速率的沉积速率完成沟槽填充。在这种方法应用于深沟槽电容器结构的形成中，中间步骤进一步包括无孔填充沟槽的覆盖，其中厚层非晶硅，之后对晶片进行平面化，随后进行热退火，在填充的沟槽内分布掺杂剂。此后，可以执行附加步骤以完成电容器结构的形成。

7. 发明授权

US07713881B2 Process sequence for doped silicon fill of deep trenches 有权
标题翻译：深沟槽掺杂硅填充工艺顺序
公开(公告)号：US07713881B2
公开(公告)日：2010-05-11
申请号：US12199402
申请日：2008-08-27
申请人： Ajit Paranjpe , Somnath Nag
发明人： Ajit Paranjpe , Somnath Nag
IPC分类号： H01L21/311
CPC分类号： C23C16/045 , C23C16/24 , H01L21/76232 , H01L29/66181
摘要： A method for void free filling with in-situ doped amorphous silicon of a deep trench structure is provided in which a first fill is carried out in a way so that film deposition occurs from the bottom of the trench upwards, with step coverage well in excess of 100%. In a second fill step, deposition conditions are changed to reduce the impact of dopant on deposition rate, and deposition proceeds at a rate which exceeds the deposition rate of the first fill. In an application of this method to the formation of deep trench capacitor structures, the intermediate steps further including the capping of the void free filled trench with a thick layer of amorphous silicon, planarization of the wafer thereafter, followed by a thermal anneal to re-distribute the dopant within the filled trench. Thereafter, additional steps can be performed to complete the formation of the capacitor structure.
摘要翻译：提供了一种用于无缝填充深沟槽结构的原位掺杂非晶硅的方法，其中第一填充以使得膜沉积从沟槽底部向上发生的方式进行，其中步骤覆盖良好地超过 100％。在第二填充步骤中，改变沉积条件以减少掺杂剂对沉积速率的影响，并且沉积以超过第一填充的沉积速率的速率进行。在这种方法应用于深沟槽电容器结构的形成中，中间步骤进一步包括无孔填充沟槽的覆盖，其中厚层非晶硅，之后对晶片进行平面化，随后进行热退火，在填充的沟槽内分布掺杂剂。此后，可以执行附加步骤以完成电容器结构的形成。

8. 发明申请

US20060234470A1 PROCESS SEQUENCE FOR DOPED SILICON FILL OF DEEP TRENCHES 有权
标题翻译： DEEP TRENCHES DOPED SILICON FILL的工艺顺序
公开(公告)号：US20060234470A1
公开(公告)日：2006-10-19
申请号：US11420893
申请日：2006-05-30
申请人： Ajit Paranjpe , Somnath Nag
发明人： Ajit Paranjpe , Somnath Nag
IPC分类号： H01L21/76
CPC分类号： C23C16/045 , C23C16/24 , H01L21/76232 , H01L29/66181
摘要： A method for void free filling with in-situ doped amorphous silicon of a deep trench structure is provided in which a first fill is carried out in at a temperature, pressure and dopant to silane ratio such that film deposition occurs from the bottom of the trench upwards. By way of this first fill, step coverages well in excess 100% are achieved. In the second fill step, deposition is carried out under changed conditions so as to reduce the impact of dopant on deposition rate, whereby trench fill is completed at a deposition rate which exceeds the deposition rate of the first fill. In an application of this method to the formation of deep trench capacitor structures, the intermediate steps further including the capping of the void free filled trench with a thick layer of amorphous silicon, planarization of the wafer thereafter, followed by a thermal anneal to re-distribute the dopant within the filled trench. Thereafter, additional steps can be performed to complete the formation of the capacitor structure.
摘要翻译：提供了一种无空隙填充深沟槽结构的原位掺杂非晶硅的方法，其中在硅烷比例的温度，压力和掺杂剂下进行第一次填充，使得从沉积的底部发生膜沉积向上。通过这个第一次填充，达到100％以上的步骤覆盖率。在第二填充步骤中，在改变的条件下进行沉积，以减少掺杂剂对沉积速率的影响，由此以超过第一填充物的沉积速率的沉积速率完成沟槽填充。在这种方法应用于深沟槽电容器结构的形成中，中间步骤进一步包括无孔填充沟槽的覆盖，其中厚层非晶硅，之后对晶片进行平面化，随后进行热退火，在填充的沟槽内分布掺杂剂。此后，可以执行附加步骤以完成电容器结构的形成。

9. 发明授权

US06572744B1 Dual collimated deposition apparatus and method of use 失效
标题翻译：双准直沉积装置及其使用方法
公开(公告)号：US06572744B1
公开(公告)日：2003-06-03
申请号：US09767576
申请日：2001-01-22
申请人： Ajit Paranjpe , Peter Schwartz , Jacques Kools , Kang Song , Dorian Heimanson , Mehrdad Moslehi
发明人： Ajit Paranjpe , Peter Schwartz , Jacques Kools , Kang Song , Dorian Heimanson , Mehrdad Moslehi
IPC分类号： C23C1434
CPC分类号： H01J37/3447 , C23C14/046 , C23C14/221 , C23C14/34 , G11B5/3163 , H01J37/34
摘要： A dual collimation deposition apparatus and method are disclosed in which the dual collimation apparatus includes at least a long-throw collimator in combination with one or more physical collimators. A new physical collimator and shield design are also disclosed for improved process uniformity and increased equipment productivity.
摘要翻译：公开了一种双准直沉积装置和方法，其中双准直装置包括与一个或多个物理准直器组合的至少一个长投射准直仪。还公开了一种新的物理准直器和屏蔽设计，以改善工艺均匀性并提高设备生产率。

10. 发明授权

US06592728B1 Dual collimated deposition apparatus and method of use 失效
公开(公告)号：US06592728B1
公开(公告)日：2003-07-15
申请号：US09130527
申请日：1998-08-04
申请人： Ajit Paranjpe , Peter Schwartz , Jacques Kools , Kang Song , Dorian Heimanson , Mehrdad Moslehi
发明人： Ajit Paranjpe , Peter Schwartz , Jacques Kools , Kang Song , Dorian Heimanson , Mehrdad Moslehi
IPC分类号： C23C1434
CPC分类号： H01J37/3447 , C23C14/046 , C23C14/221 , C23C14/34 , G11B5/3163 , H01J37/34
摘要： A dual collimation deposition apparatus and method are disclosed in which the dual collimation apparatus includes at least a long-throw collimator in combination with one or more physical collimators. A new physical collimator and shield design are also disclosed for improved process uniformity and increased equipment productivity.

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