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    • 4. 发明授权
    • System and method for step coverage measurement
    • 步骤覆盖测量的系统和方法
    • US08486727B2
    • 2013-07-16
    • US12946846
    • 2010-11-15
    • Hanhong ChenEdward HaywoodPragati Kumar
    • Hanhong ChenEdward HaywoodPragati Kumar
    • G01R31/26H01L21/66
    • G01N23/223H01L22/12
    • Determining an unknown step coverage of a thin film deposited on a 3D wafer includes exposing a planar wafer comprising a first film deposited thereon to X-ray radiation to create first fluorescent radiation; detecting the first fluorescent radiation; measuring a number of XRF counts on the planar wafer; creating an XRF model of the planar wafer; providing a portion of the 3D wafer comprising troughs and a second film deposited thereon; determining a multiplier factor between the portion of the 3D wafer and the planar wafer; exposing the portion of the 3D wafer to X-ray radiation to create second fluorescent radiation; detecting the second fluorescent radiation; measuring a number of XRF counts on the portion of the 3D wafer; calculating a step coverage of the portion of the 3D wafer; and determining a uniformity of the 3D wafer based on the step coverage of the portion of the 3D wafer.
    • 确定沉积在3D晶片上的薄膜的未知步骤覆盖包括将包括沉积在其上的第一膜的平面晶片暴露于X射线辐射以产生第一荧光辐射; 检测第一荧光辐射; 测量平面晶片上的XRF数量; 创建平面晶片的XRF模型; 提供包括槽的3D晶片的一部分和沉积在其上的第二膜; 确定所述3D晶片的所述部分和所述平面晶片之间的乘数; 将3D晶片的部分暴露于X射线辐射以产生第二荧光辐射; 检测第二荧光辐射; 测量3D晶片部分上的XRF数量; 计算3D晶片的部分的台阶覆盖; 以及基于所述3D晶片的所述部分的台阶覆盖来确定所述3D晶片的均匀性。
    • 9. 发明申请
    • METHODS FOR FORMING HIGH-K CRYSTALLINE FILMS AND RELATED DEVICES
    • 用于形成高K晶体薄膜和相关器件的方法
    • US20120156889A1
    • 2012-06-21
    • US13334618
    • 2011-12-22
    • Hanhong ChenEdward HaywoodPragati KumarSandra MalhotraXiangxin Rui
    • Hanhong ChenEdward HaywoodPragati KumarSandra MalhotraXiangxin Rui
    • H01L21/316
    • H01L28/40H01L21/02186H01L21/02189H01L21/0228H01L28/56H01L28/60
    • This disclosure provides a method of fabricating a semiconductor stack and associated device, such as a capacitor or DRAM cell. In such a device, a high-K zirconia-based layer may be used as the primary dielectric together with a relatively inexpensive metal electrode based on titanium nitride. To prevent corruption of the electrode during device formation, a thin barrier layer can be used seal the electrode prior to the use of a high temperature process and a (high-concentration or dosage) ozone reagent (i.e., to create a high-K zirconia-based layer). In some embodiments, the barrier layer can also be zirconia-based, for example, a thin layer of doped or un-doped amorphous zirconia. Fabrication of a device in this manner facilitates formation of a device with dielectric constant of greater than 40 based on zirconia and titanium nitride, and generally helps produce less costly, increasingly dense DRAM cells and other semiconductor structures.
    • 本公开提供了制造半导体堆叠和相关联的器件(诸如电容器或DRAM单元)的方法。 在这种器件中,高K氧化锆基层可以与基于氮化钛的相对廉价的金属电极一起用作主要电介质。 为了防止在器件形成期间电极的损坏,可以使用薄的阻挡层,在使用高温工艺和(高浓度或剂量)的臭氧试剂之前密封电极(即,产生高K氧化锆 基层)。 在一些实施例中,阻挡层也可以是基于氧化锆的,例如掺杂或未掺杂的无定形氧化锆的薄层。 以这种方式制造器件有助于基于氧化锆和氮化钛形成具有大于40的介电常数的器件,并且通常有助于产生更便宜的,越来越致密的DRAM电池和其它半导体结构。