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1. 发明授权

US08595731B2 Low overhead dynamic thermal management in many-core cluster architecture 失效
标题翻译：多核心集群架构中的低开销动态热管理
公开(公告)号：US08595731B2
公开(公告)日：2013-11-26
申请号：US12698545
申请日：2010-02-02
申请人： Pradip Bose , Philip G. Emma , Eren Kursun , Jude A. Rivers
发明人： Pradip Bose , Philip G. Emma , Eren Kursun , Jude A. Rivers
IPC分类号： G06F9/46 , G06F9/44
CPC分类号： G06F9/46
摘要： A semiconductor chip includes a plurality of multi-core clusters each including a plurality of cores and a cluster controller unit. Each cluster controller unit is configured to control thread assignment within the multi-core cluster to which it belongs. The cluster controller unit monitors various parameters measured in the plurality of cores within the multi-core cluster to estimate the computational demand of each thread that runs in the cores. The cluster controller unit may reassign the threads within the multi-core cluster based on the estimated computational demand of the threads and transmit a signal to an upper-level software manager that controls the thread assignment across the semiconductor chip. When an acceptable solution to thread assignment cannot be achieved by shuffling of threads within the multi-core cluster, the cluster controller unit may also report inability to solve thread assignment to the upper-level software manager to request a system level solution.
摘要翻译：半导体芯片包括多个多芯簇，每个多核簇包括多个核和集群控制器单元。每个集群控制器单元被配置为控制它所属的多核集群内的线程分配。集群控制器单元监视在多核集群内的多个核心中测量的各种参数，以估计在核心中运行的每个线程的计算需求。集群控制器单元可以基于线程的估计的计算需求来重新分配多核集群内的线程，并将信号发送到控制半导体芯片上的线程分配的上级软件管理器。当通过在多核心集群内的线程进行混洗，无法实现线程分配的可接受解决方案时，集群控制器单元也可能会报告无法解决线程分配给上级软件管理器以请求系统级解决方案。

2. 发明申请

US20110191776A1 LOW OVERHEAD DYNAMIC THERMAL MANAGEMENT IN MANY-CORE CLUSTER ARCHITECTURE 失效
标题翻译：多个核心集群架构中的低层动态热管理
公开(公告)号：US20110191776A1
公开(公告)日：2011-08-04
申请号：US12698545
申请日：2010-02-02
申请人： Pradip Bose , Philip G. Emma , Eren Kursun , Jude A. Rivers
发明人： Pradip Bose , Philip G. Emma , Eren Kursun , Jude A. Rivers
IPC分类号： G06F9/46
CPC分类号： G06F9/46
摘要： A semiconductor chip includes a plurality of multi-core clusters each including a plurality of cores and a cluster controller unit. Each cluster controller unit is configured to control thread assignment within the multi-core cluster to which it belongs. The cluster controller unit monitors various parameters measured in the plurality of cores within the multi-core cluster to estimate the computational demand of each thread that runs in the cores. The cluster controller unit may reassign the threads within the multi-core cluster based on the estimated computational demand of the threads and transmit a signal to an upper-level software manager that controls the thread assignment across the semiconductor chip. When an acceptable solution to thread assignment cannot be achieved by shuffling of threads within the multi-core cluster, the cluster controller unit may also report inability to solve thread assignment to the upper-level software manager to request a system level solution.
摘要翻译：半导体芯片包括多个多芯簇，每个多核簇包括多个核和集群控制器单元。每个集群控制器单元被配置为控制它所属的多核集群内的线程分配。集群控制器单元监视在多核集群内的多个核心中测量的各种参数，以估计在核心中运行的每个线程的计算需求。集群控制器单元可以基于线程的估计的计算需求来重新分配多核集群内的线程，并将信号发送到控制半导体芯片上的线程分配的上级软件管理器。当通过在多核心集群内的线程进行混洗，无法实现线程分配的可接受解决方案时，集群控制器单元也可能会报告无法解决线程分配给上级软件管理器以请求系统级解决方案。

3. 发明授权

US08141020B2 Temperature-controlled 3-dimensional bus placement 有权
标题翻译：温控三维总线布置
公开(公告)号：US08141020B2
公开(公告)日：2012-03-20
申请号：US12493599
申请日：2009-06-29
申请人： Philip G. Emma , Eren Kursun , Jude A. Rivers
发明人： Philip G. Emma , Eren Kursun , Jude A. Rivers
IPC分类号： G06F17/50
CPC分类号： G06F17/5072
摘要： Block placement within each device-containing layer is optimized under the constraint of a simultaneous optimization of interlayer connectivity between the device-containing layer and immediately adjacent device-containing layers. For each functional block within the device-containing layer, lateral heat flow is calculated to laterally adjacent functional blocks. If the lateral heat flow is less than a threshold value for a pair of adjacent functional blocks, placement of the functional blocks and/or interlayer interconnect structure array therebetween or modification of the interlayer interconnect structure array is performed. This routine is repeated for all adjacent pairs of functional blocks in each of the device-containing layers. Subsequently, block placement within each device-containing layer may be optimized under the constraint of a simultaneous optimization of interlayer connectivity across all device-containing layers. This method provides a design having sufficient lateral heat flow in each of the device-containing layers in a semiconductor chip.
摘要翻译：在包含装置的层和紧邻相邻的装置层之间的层间连通性的同时优化的限制下，在每个含有装置的层内的块放置被优化。对于含有装置的层内的每个功能块，横向热流被计算为横向相邻的功能块。如果侧向热流小于一对相邻功能块的阈值，则在其间布置功能块和/或层间互连结构阵列或者修改层间互连结构阵列。对于每个含设备的层中的所有相邻的功能块对，重复此例程。随后，可以在跨所有含有装置的层的层间连接的同时优化的约束下优化在每个包含装置的层内的块放置。该方法提供了在半导体芯片中的每个含有器件的层中具有足够的横向热流的设计。

4. 发明申请

US20110286190A1 Enhanced Modularity in Heterogeneous 3D Stacks 有权
标题翻译：在异构3D堆栈中增强模块化
公开(公告)号：US20110286190A1
公开(公告)日：2011-11-24
申请号：US12774223
申请日：2010-05-20
申请人： Eren Kursun , Philip G. Emma , Jude A. Rivers
发明人： Eren Kursun , Philip G. Emma , Jude A. Rivers
IPC分类号： H05K7/02
CPC分类号： H01L23/147 , H01L21/4803 , H01L23/13 , H01L23/5382 , H01L23/5389 , H01L25/0652 , H01L25/18 , H01L2225/06575 , H01L2225/06589 , H01L2924/0002 , H01L2924/15311 , H05K3/30 , H05K3/465 , Y10T29/49128 , Y10T29/4913 , Y10T29/49137 , Y10T29/49146 , H01L2924/00
摘要： Enhanced modularity in heterogeneous three-dimensional computer processing chip stacks includes a method of manufacture. The method includes preparing a host layer and integrating the host layer with at least one other layer in the stack. The host layer is prepared by forming cavities on the host layer for receiving chips pre-configured with heterogeneous properties relative to each other, disposing the chips in corresponding cavities on the host layer, and joining the chips to respective surfaces of the cavities thereby forming an element having a smooth surface with respect to the host layer and the chips.
摘要翻译：异构三维计算机处理芯片堆栈中的增强的模块化包括制造方法。该方法包括准备主机层并将主机层与栈中的至少一个其他层集成。主体层通过在主体层上形成空腔来制备，用于接收相对于彼此预先配置有非均匀性质的芯片，将芯片设置在主体层上的相应空腔中，以及将芯片连接到空腔的相应表面，从而形成元件具有相对于主体层和芯片的平滑表面。

5. 发明授权

US08677613B2 Enhanced modularity in heterogeneous 3D stacks 有权
标题翻译：在异构3D堆栈中增强模块化
公开(公告)号：US08677613B2
公开(公告)日：2014-03-25
申请号：US12774223
申请日：2010-05-20
申请人： Eren Kursun , Philip G. Emma , Jude A. Rivers
发明人： Eren Kursun , Philip G. Emma , Jude A. Rivers
IPC分类号： H05K3/30
CPC分类号： H01L23/147 , H01L21/4803 , H01L23/13 , H01L23/5382 , H01L23/5389 , H01L25/0652 , H01L25/18 , H01L2225/06575 , H01L2225/06589 , H01L2924/0002 , H01L2924/15311 , H05K3/30 , H05K3/465 , Y10T29/49128 , Y10T29/4913 , Y10T29/49137 , Y10T29/49146 , H01L2924/00
摘要： Enhanced modularity in heterogeneous three-dimensional computer processing chip stacks includes a method of manufacture. The method includes preparing a host layer and integrating the host layer with at least one other layer in the stack. The host layer is prepared by forming cavities on the host layer for receiving chips pre-configured with heterogeneous properties relative to each other, disposing the chips in corresponding cavities on the host layer, and joining the chips to respective surfaces of the cavities thereby forming an element having a smooth surface with respect to the host layer and the chips.
摘要翻译：异构三维计算机处理芯片堆栈中的增强的模块化包括制造方法。该方法包括准备主机层并将主机层与栈中的至少一个其他层集成。主体层通过在主体层上形成空腔来制备，用于接收相对于彼此预先配置有非均匀性质的芯片，将芯片设置在主体层上的相应空腔中，以及将芯片连接到空腔的相应表面，从而形成元件具有相对于主体层和芯片的平滑表面。

6. 发明申请

US20120268909A1 Enhanced Modularity in Heterogeneous 3D Stacks 审中-公开
标题翻译：在异构3D堆栈中增强模块化
公开(公告)号：US20120268909A1
公开(公告)日：2012-10-25
申请号：US13535660
申请日：2012-06-28
申请人： Philip G. Emma , Eren Kursun , Jude A. Rivers
发明人： Philip G. Emma , Eren Kursun , Jude A. Rivers
IPC分类号： H05K7/02
CPC分类号： H01L23/147 , H01L21/4803 , H01L23/13 , H01L23/5382 , H01L23/5389 , H01L25/0652 , H01L25/18 , H01L2225/06575 , H01L2225/06589 , H01L2924/0002 , H01L2924/15311 , H05K3/30 , H05K3/465 , Y10T29/49128 , Y10T29/4913 , Y10T29/49137 , Y10T29/49146 , H01L2924/00
摘要： A three-dimensional computer processing chip stack that includes a host layer disposed on at least one other layer in the stack. The host layer includes cavities formed thereon for receiving chips pre-configured with heterogeneous properties relative to each other. The cavities are formed to accommodate the heterogeneous properties of the chips. The chips are joined to respective surfaces of the cavities, thereby forming an element having a smooth surface with respect to the host layer and the chips.
摘要翻译：一种三维计算机处理芯片堆叠，其包括布置在堆叠中的至少一个其他层上的主机层。主体层包括形成在其上的空腔，用于接收预先配置有相对于彼此的异质特性的芯片。形成空腔以适应芯片的不均匀性质。芯片被连接到空腔的相应表面，从而形成相对于主体层和芯片具有平滑表面的元件。

7. 发明授权

US09373557B2 Enhanced modularity in heterogeneous 3D stacks 有权
标题翻译：在异构3D堆栈中增强模块化
公开(公告)号：US09373557B2
公开(公告)日：2016-06-21
申请号：US13535675
申请日：2012-06-28
申请人： Philip G. Emma , Eren Kursun , Jude A. Rivers
发明人： Philip G. Emma , Eren Kursun , Jude A. Rivers
IPC分类号： G06F17/50 , H01L23/14 , H05K3/46 , H01L23/13 , H01L23/538 , H01L25/065 , H01L25/18 , H05K3/30 , H01L21/48
CPC分类号： H01L23/147 , H01L21/4803 , H01L23/13 , H01L23/5382 , H01L23/5389 , H01L25/0652 , H01L25/18 , H01L2225/06575 , H01L2225/06589 , H01L2924/0002 , H01L2924/15311 , H05K3/30 , H05K3/465 , Y10T29/49128 , Y10T29/4913 , Y10T29/49137 , Y10T29/49146 , H01L2924/00
摘要： A method for generating and implementing a three-dimensional (3D) computer processing chip stack plan that includes receiving system requirements from a plurality of clients, identifying common processing structures and technologies from the system requirements, and assigning the common processing structures and technologies to a layer in the 3D computer processing chip stack plan. The method also includes identifying uncommon processing structures and technologies from the system requirements and assigning the uncommon processing structures and technologies to a host layer in the 3D computer processing chip stack plan. The method further includes determining placement and wiring of the uncommon structures on the host layer, storing placement information in the plan, and transmitting the plan to manufacturing equipment. The manufacturing equipment generates and integrates both the layer including the common structures and technologies and the host layer including the uncommon structures and technologies to form the 3D computer processing chip stack.
摘要翻译：一种用于生成和实现三维（3D）计算机处理芯片堆栈计划的方法，其包括从多个客户端接收系统需求，从系统需求中识别公共处理结构和技术，以及将公共处理结构和技术分配给三层计算机处理芯片堆栈计划。该方法还包括从系统需求中识别不常见的处理结构和技术，并将不常见的处理结构和技术分配给3D计算机处理芯片堆栈计划中的主机层。该方法还包括确定主机层上的不常见结构的布置和布线，将布置信息存储在计划中，并将该计划传送到制造设备。制造设备生成并集成了包括公共结构和技术的层，以及主机层，包括不常见的结构和技术，以形成3D计算机处理芯片堆栈。

8. 发明申请

US20120272202A1 Enhanced Modularity in Heterogeneous 3D Stacks 有权
标题翻译：在异构3D堆栈中增强模块化
公开(公告)号：US20120272202A1
公开(公告)日：2012-10-25
申请号：US13535675
申请日：2012-06-28
申请人： Philip G. Emma , Eren Kursun , Jude A. Rivers
发明人： Philip G. Emma , Eren Kursun , Jude A. Rivers
IPC分类号： G06F17/50
CPC分类号： H01L23/147 , H01L21/4803 , H01L23/13 , H01L23/5382 , H01L23/5389 , H01L25/0652 , H01L25/18 , H01L2225/06575 , H01L2225/06589 , H01L2924/0002 , H01L2924/15311 , H05K3/30 , H05K3/465 , Y10T29/49128 , Y10T29/4913 , Y10T29/49137 , Y10T29/49146 , H01L2924/00
摘要： A method for generating and implementing a three-dimensional (3D) computer processing chip stack plan that includes receiving system requirements from a plurality of clients, identifying common processing structures and technologies from the system requirements, and assigning the common processing structures and technologies to a layer in the 3D computer processing chip stack plan. The method also includes identifying uncommon processing structures and technologies from the system requirements and assigning the uncommon processing structures and technologies to a host layer in the 3D computer processing chip stack plan. The method further includes determining placement and wiring of the uncommon structures on the host layer, storing placement information in the plan, and transmitting the plan to manufacturing equipment. The manufacturing equipment generates and integrates both the layer including the common structures and technologies and the host layer including the uncommon structures and technologies to form the 3D computer processing chip stack.
摘要翻译：一种用于生成和实现三维（3D）计算机处理芯片堆栈计划的方法，其包括从多个客户端接收系统需求，从系统需求中识别公共处理结构和技术，以及将公共处理结构和技术分配给三层计算机处理芯片堆栈计划。该方法还包括从系统需求中识别不常见的处理结构和技术，并将不常见的处理结构和技术分配给3D计算机处理芯片堆栈计划中的主机层。该方法还包括确定主机层上的不常见结构的布置和布线，将布置信息存储在计划中，并将该计划传送到制造设备。制造设备生成并集成了包括公共结构和技术的层，以及主机层，包括不常见的结构和技术，以形成3D计算机处理芯片堆栈。

9. 发明申请

US20100333056A1 TEMPERATURE-CONTROLLED 3-DIMENSIONAL BUS PLACEMENT 有权
标题翻译：温度控制三维总线布置
公开(公告)号：US20100333056A1
公开(公告)日：2010-12-30
申请号：US12493599
申请日：2009-06-29
申请人： Philip G. Emma , Eren Kursun , Jude A. Rivers
发明人： Philip G. Emma , Eren Kursun , Jude A. Rivers
IPC分类号： G06F17/50
CPC分类号： G06F17/5072
摘要： Block placement within each device-containing layer is optimized under the constraint of a simultaneous optimization of interlayer connectivity between the device-containing layer and immediately adjacent device-containing layers. For each functional block within the device-containing layer, lateral heat flow is calculated to laterally adjacent functional blocks. If the lateral heat flow is less than a threshold value for a pair of adjacent functional blocks, placement of the functional blocks and/or interlayer interconnect structure array therebetween or modification of the interlayer interconnect structure array is performed. This routine is repeated for all adjacent pairs of functional blocks in each of the device-containing layers. Subsequently, block placement within each device-containing layer may be optimized under the constraint of a simultaneous optimization of interlayer connectivity across all device-containing layers. This method provides a design having sufficient lateral heat flow in each of the device-containing layers in a semiconductor chip.
摘要翻译：在包含装置的层和紧邻相邻的装置层之间的层间连通性的同时优化的限制下，在每个含有装置的层内的块放置被优化。对于含有装置的层内的每个功能块，横向热流被计算为横向相邻的功能块。如果侧向热流小于一对相邻功能块的阈值，则在其间布置功能块和/或层间互连结构阵列或者修改层间互连结构阵列。对于每个含设备的层中的所有相邻的功能块对，重复此例程。随后，可以在跨所有含有装置的层的层间连接的同时优化的约束下优化在每个包含装置的层内的块放置。该方法提供了在半导体芯片中的每个含有器件的层中具有足够的横向热流的设计。

10. 发明授权

US09390989B2 Enhanced modularity in heterogeneous 3D stacks 有权
标题翻译：在异构3D堆栈中增强模块化
公开(公告)号：US09390989B2
公开(公告)日：2016-07-12
申请号：US13535694
申请日：2012-06-28
申请人： Philip G. Emma , Eren Kursun , Jude A. Rivers
发明人： Philip G. Emma , Eren Kursun , Jude A. Rivers
IPC分类号： G06F17/50 , H01L23/14 , H05K3/46 , H01L23/13 , H01L23/538 , H01L25/065 , H01L25/18 , H05K3/30 , H01L21/48
CPC分类号： H01L23/147 , H01L21/4803 , H01L23/13 , H01L23/5382 , H01L23/5389 , H01L25/0652 , H01L25/18 , H01L2225/06575 , H01L2225/06589 , H01L2924/0002 , H01L2924/15311 , H05K3/30 , H05K3/465 , Y10T29/49128 , Y10T29/4913 , Y10T29/49137 , Y10T29/49146 , H01L2924/00
摘要： A computer program product for generating and implementing a three-dimensional (3D) computer processing chip stack plan. The computer readable program code includes computer readable program code configured for receiving system requirements from a plurality of clients, identifying common processing structures and technologies from the system requirements, and assigning the common processing structures and technologies to at least one layer in the 3D computer processing chip stack plan. The computer readable program code is also configured for identifying uncommon processing structures and technologies from the system requirements and assigning the uncommon processing structures and technologies to a host layer in the 3D computer processing chip stack plan. The computer readable program code is further configured for determining placement and wiring of the uncommon structures on the host layer, storing placement information in the plan, and transmitting the plan to manufacturing equipment. The manufacturing equipment forms the 3D computer processing chip stack.
摘要翻译：一种用于生成和实现三维（3D）计算机处理芯片堆栈计划的计算机程序产品。计算机可读程序代码包括被配置为从多个客户端接收系统需求的计算机可读程序代码，从系统要求中识别公共处理结构和技术，以及将公共处理结构和技术分配给3D计算机处理中的至少一个层芯片堆栈计划。计算机可读程序代码还被配置用于根据系统要求识别不常见的处理结构和技术，并将不常见的处理结构和技术分配给3D计算机处理芯片堆栈计划中的主机层。计算机可读程序代码还被配置用于确定主机层上的不常见结构的布置和布线，将布置信息存储在计划中，并将该计划传送到制造设备。制造设备构成3D计算机处理芯片堆栈。

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