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1. 发明授权

US06989322B2 Method of forming ultra-thin silicidation-stop extensions in mosfet devices 有权
标题翻译：在mosfet器件中形成超薄硅化 - 停止延伸的方法
公开(公告)号：US06989322B2
公开(公告)日：2006-01-24
申请号：US10707175
申请日：2003-11-25
申请人： Oleg G. Gluschenkov , Cyril Cabral, Jr. , Omer Dokumaci , Christian Lavoie
发明人： Oleg G. Gluschenkov , Cyril Cabral, Jr. , Omer Dokumaci , Christian Lavoie
IPC分类号： H01L21/3205 , H01L21/4763
CPC分类号： H01L29/0847 , H01L21/28518 , H01L29/665 , H01L29/66636 , H01L29/7833
摘要： Very low resistance, scaled in MOSFET devices are formed by employing thin silicidation-stop extension that act both as a silicidation “stop” barriers and as thin interface layers between source/drain silicide regions and channel region of the MOSFET. By acting as silicidation stops, the silicidation-stop extensions confine silicidation, and are not breached by source/drain silicide. This permits extremely thin, highly-doped silicidation-stop extensions to be formed between the silicide and the channel, providing an essentially ideal, low series resistance interface between the silicide and the channel.
摘要翻译：通过使用薄硅化停止扩展来形成MOSFET器件中的非常低的电阻，其既用作硅化“阻挡”势垒，又作为源/漏硅化物区域和MOSFET的沟道区之间的薄界面层。通过作为硅化停止，硅化 - 停止扩展限制硅化，并且不被源/漏硅化物破坏。这允许在硅化物和沟道之间形成非常薄的，高掺杂的硅化 - 停止延伸，在硅化物和沟道之间提供基本理想的低串联电阻接口。

2. 发明申请

US20050112857A1 ULTRA-THIN SILICIDATION-STOP EXTENSIONS IN MOSFET DEVICES 有权
公开(公告)号：US20050112857A1
公开(公告)日：2005-05-26
申请号：US10707175
申请日：2003-11-25
申请人： Oleg Gluschenkov , Cyril Cabral , Omer Dokumaci , Christian Lavoie
发明人： Oleg Gluschenkov , Cyril Cabral , Omer Dokumaci , Christian Lavoie
IPC分类号： H01L21/285 , H01L21/3205 , H01L21/336 , H01L21/8234 , H01L27/092 , H01L29/08 , H01L29/78
CPC分类号： H01L29/0847 , H01L21/28518 , H01L29/665 , H01L29/66636 , H01L29/7833
摘要： Very low resistance, scaled in MOSFET devices are formed by employing thin silicidation-stop extension that act both as a silicidation “stop” barriers and as thin interface layers between source/drain silicide regions and channel region of the MOSFET. By acting as silicidation stops, the silicidation-stop extensions confine silicidation, and are not breached by source/drain silicide. This permits extremely thin, highly-doped silicidation-stop extensions to be formed between the silicide and the channel, providing an essentially ideal, low series resistance interface between the silicide an the channel. On an appropriately prepared substrate, a selective etching process is performed to expose the sides of the channel region (transistor body). A very thin layer of a silicidation-stop material, e.g., SiGe, is disposed in the etched away area, coating the exposed sides of the channel region. The silicidation-stop material is doped (highly) appropriately for the type of MOSFET being formed (n-channel or p-channel). The etched away areas are then filled with silicon, e.g., by an Si epi process. Silicidation is then performed (to form, e.g., CoSi2) on the newly filled areas. The silicidation stop material constrains silicidation to the silicon fill material, but prevents silicide expansion past the silicidation stop material. Because the germanium (Ge) in SiGe is insoluble in CoSi2, the SiGe acts as a barrier to silicidation, permitting silicidation to go to completion in the Si fill but stopping silicidation at the SiGe boundary when silicidation is performed at a temperature above a silicidation threshold temperature for Si, but below a silicidation threshold temperature for SiGe. This results in a very compact, well-defined lateral junction characterized by a thin layer of SiGe disposed between silicide lateral extensions and the sides of the channel region. Because of the thin, highly-doped SiGe layer between the channel and the silicide lateral extensions, the extension resistance is very low.

3. 发明授权

US07041600B2 Methods of planarization 失效
标题翻译：平面化方法
公开(公告)号：US07041600B2
公开(公告)日：2006-05-09
申请号：US10604196
申请日：2003-06-30
申请人： Omer Dokumaci , Bruce Doris , David Horak , Fen F. Jamin
发明人： Omer Dokumaci , Bruce Doris , David Horak , Fen F. Jamin
IPC分类号： H10L21/302
CPC分类号： H01L21/31053
摘要： A method of planarization allows for the use of chemical mechanical polishing (CMP) in starting structures having films not generally suitable for CMP processes. Two material layers are formed over a starting structure, and the upper layer is planarized in a CMP process. A nonselective etch is then used to transfer the planar topography to the lower level.
摘要翻译：平面化方法允许在起始结构中使用化学机械抛光（CMP），其具有通常不适用于CMP工艺的膜。在起始结构上形成两个材料层，并且在CMP工艺中将上层平坦化。然后使用非选择性蚀刻将平面形貌转移到较低水平。

4. 发明申请

US20050275060A1 Structure and method to preserve STI during etching 审中-公开
标题翻译：蚀刻期间保留STI的结构和方法
公开(公告)号：US20050275060A1
公开(公告)日：2005-12-15
申请号：US11151506
申请日：2005-06-13
申请人： Omer Dokumaci , Bruce Doris
发明人： Omer Dokumaci , Bruce Doris
IPC分类号： H01L21/76 , H01L21/301 , H01L21/311 , H01L21/318 , H01L21/762 , H01L29/00
CPC分类号： H01L21/02271 , H01L21/02118 , H01L21/0217 , H01L21/02211 , H01L21/31144 , H01L21/3185 , H01L21/76224 , H01L21/76283
摘要： Disclosed is a method of protecting a semiconductor shallow trench isolation (STI) oxide from etching, the method comprising lowering, if necessary, the upper surface of said STI oxide to a level below that of adjacent silicon active areas, depositing a nitride liner upon said STI oxide and adjacent silicon active areas in a manner effective in defining a depression above said STI oxide, filling said depression with a protective film, and removing said nitride layer from said adjacent active areas.
摘要翻译：公开了一种保护半导体浅沟槽隔离（STI）氧化物免受蚀刻的方法，所述方法包括如果需要，将所述STI氧化物的上表面降低至低于相邻硅有源区的上表面，将氮化物衬垫沉积在所述 STI氧化物和相邻的硅有源区，以有效地限定所述STI氧化物上方的凹陷的方式，用保护膜填充所述凹陷，以及从所述相邻的活性区域移除所述氮化物层。

5. 发明申请

US20050245017A1 Structure and method to improve channel mobility by gate electrode stress modification 失效
公开(公告)号：US20050245017A1
公开(公告)日：2005-11-03
申请号：US11175223
申请日：2005-07-07
申请人： Michael Belyansky , Dureseti Chidambarrao , Omer Dokumaci , Bruce Doris , Oleg Glusehenkov
发明人： Michael Belyansky , Dureseti Chidambarrao , Omer Dokumaci , Bruce Doris , Oleg Glusehenkov
IPC分类号： H01L21/20 , H01L21/28 , H01L21/302 , H01L21/336 , H01L21/44 , H01L21/461 , H01L21/4763 , H01L21/8238 , H01L27/092 , H01L29/49 , H01L29/72 , H01L29/78 , H01L29/786 , H01L31/062
CPC分类号： H01L29/7845 , H01L21/823807 , H01L21/823835 , H01L21/823842 , H01L29/4908 , H01L29/66795 , H01L29/785
摘要： In producing complementary sets of metal-oxide-semiconductor (CMOS) field effect transistors, including nFET and pFET), carrier mobility is enhanced or otherwise regulated through the reacting the material of the gate electrode with a metal to produce a stressed alloy (preferably CoSi2, NiSi, or PdSi) within a transistor gate. In the case of both the nFET and pFET, the inherent stress of the respective alloy results in an opposite stress on the channel of respective transistor. By maintaining opposite stresses in the nFET and pFET alloys or silicides, both types of transistors on a single chip or substrate can achieve an enhanced carrier mobility, thereby improving the performance of CMOS devices and integrated circuits.

6. 发明申请

US20050191795A1 Method of manufacture of FinFET devices with T-shaped fins and devices manufactured thereby 失效
标题翻译：具有T形翅片的FinFET器件的制造方法和由此制造的器件
公开(公告)号：US20050191795A1
公开(公告)日：2005-09-01
申请号：US10790550
申请日：2004-03-01
申请人： Dureseti Chidambarrao , Omer Dokumaci
发明人： Dureseti Chidambarrao , Omer Dokumaci
IPC分类号： H01L21/335 , H01L21/336 , H01L21/8242 , H01L29/772 , H01L29/786
CPC分类号： H01L29/7853 , H01L29/66795 , H01L29/7842
摘要： An FET device comprises a semiconductor structure with a source island, a drain island over a horizontal surface of a substrate comprising an insulating material. A channel structure over the horizontal surface of the substrate connects between the drain and the source, with the channel structure comprising a horizontal semiconductor channel fin above a vertical fin with the planar fin and the vertical fin having a T-shaped cross-section. The vertical fin is contact with the horizontal surface of the substrate and the planar fin is in contact with the top of the vertical fin. A gate dielectric layer covers exposed surfaces of the channel structure. A gate electrode straddles the channel gate dielectric and the channel structure. Then a sacrificial layer such as SiGe is deposited upon the substrate before forming the vertical fin which may be either a semiconductor or dielectric material. The planar fin is a semiconductor material such as Si, SiGe or Ge.
摘要翻译： FET器件包括具有源岛的半导体结构，在包括绝缘材料的衬底的水平表面上的漏极岛。衬底的水平表面上的沟道结构连接在漏极和源极之间，其中沟道结构包括在具有平面翅片的垂直翅片上方的水平半导体沟道翅片，并且垂直翅片具有T形横截面。垂直翅片与基板的水平表面接触，并且平面翅片与垂直翅片的顶部接触。栅介质层覆盖通道结构的暴露表面。栅电极横跨沟道栅极电介质和沟道结构。然后在形成可以是半导体或电介质材料的垂直翅片之前，将诸如SiGe的牺牲层沉积在衬底上。平面翅片是诸如Si，SiGe或Ge的半导体材料。

7. 发明申请

US20050145992A1 Method for reduced N+ diffusion in strained Si on SiGe substrate 有权
标题翻译： SiGe衬底上应变Si中N +扩散减少的方法
公开(公告)号：US20050145992A1
公开(公告)日：2005-07-07
申请号：US11057129
申请日：2005-02-15
申请人： Dureseti Chidambarrao , Omer Dokumaci
发明人： Dureseti Chidambarrao , Omer Dokumaci
IPC分类号： H01L21/265 , H01L21/332 , H01L21/336 , H01L21/461 , H01L21/8234 , H01L21/8238 , H01L29/10 , H01L29/78 , H01L31/117
CPC分类号： H01L21/823814 , H01L21/26506 , H01L21/26513 , H01L29/1054 , H01L29/6656
摘要： The first source and drain regions are formed in an upper surface of a SiGe substrate. The first source and drain regions containing an N type impurity. Vacancy concentration in the first source and drain regions are reduced in order to reduce diffusion of the N type impurity contained In the first source and drain regions. The vacancy concentration Is reduced by an interstitial element or a vacancy-trapping element in the first source and drain regions. The interstitial element or the vacancy-trapping element is provided by ion-implantation.
摘要翻译：第一源区和漏区形成在SiGe衬底的上表面中。含有N型杂质的第一源区和漏区。减少第一源区和漏区中的空位浓度，以便减少在第一源区和漏区中含有的N型杂质的扩散。空位浓度通过第一源极和漏极区域中的间隙元素或空穴捕获元素而减小。间隙元素或空位捕获元件通过离子注入提供。

8. 发明申请

US20050142788A1 MOSFET performance improvement using deformation in SOI structure 失效
标题翻译：使用SOI结构中的变形的MOSFET性能改进
公开(公告)号：US20050142788A1
公开(公告)日：2005-06-30
申请号：US11065061
申请日：2005-02-25
申请人： Dureseti Chidambarrao , Omer Dokumaci
发明人： Dureseti Chidambarrao , Omer Dokumaci
IPC分类号： H01L21/762 , H01L21/84 , H01L27/12 , H01L29/06 , H01L21/331 , H01L21/8222 , H01L31/0328 , H01L31/0336 , H01L31/072 , H01L31/109
CPC分类号： H01L21/84 , H01L21/7624 , H01L27/1203 , H01L29/7849
摘要： A method for manufacturing a semiconductor device is provided. The method includes forming a semiconductor layer on a substrate. The first region of the substrate is expanded to push up the first portion of the semiconductor layer, thereby applying tensile stress to the first portion. The second region of the substrate is compressed to pull down the second portion of the semiconductor layer, thereby applying compressive stress to the second portion. An N type device is formed over the first portion of the semiconductor layer, and a P type device is formed over the second portion of the semiconductor layer.
摘要翻译：提供一种制造半导体器件的方法。该方法包括在衬底上形成半导体层。衬底的第一区域被膨胀以向上推动半导体层的第一部分，从而对第一部分施加拉伸应力。衬底的第二区域被压缩以拉下半导体层的第二部分，从而向第二部分施加压应力。在半导体层的第一部分上形成N型器件，并且在半导体层的第二部分上形成P型器件。

9. 发明申请

US20050093059A1 Structure and method to improve channel mobility by gate electrode stress modification 有权
标题翻译：通过栅电极应力改变来提高沟道迁移率的结构和方法
公开(公告)号：US20050093059A1
公开(公告)日：2005-05-05
申请号：US10695752
申请日：2003-10-30
申请人： Michael Belyansky , Dureseti Chidambarrao , Omer Dokumaci , Bruce Deris , Oleg Gluschenkov
发明人： Michael Belyansky , Dureseti Chidambarrao , Omer Dokumaci , Bruce Deris , Oleg Gluschenkov
IPC分类号： H01L21/20 , H01L21/28 , H01L21/302 , H01L21/336 , H01L21/44 , H01L21/461 , H01L21/4763 , H01L21/8238 , H01L27/092 , H01L29/49 , H01L29/72 , H01L29/78 , H01L29/786 , H01L31/062
CPC分类号： H01L29/7845 , H01L21/823807 , H01L21/823835 , H01L21/823842 , H01L29/4908 , H01L29/66795 , H01L29/785
摘要： In producing complementary sets of metal-oxide-semiconductor (CMOS) field effect transistors, including nFET and PFET), carrier mobility is enhanced or otherwise regulated through the reacting the material of the gate electrode with a metal to produce a stressed alloy (preferably CoSi2, NiSi, or PdSi) within a transistor gate. In the case of both the nFET and pFET, the inherent stress of the respective alloy results in an opposite stress on the channel of respective transistor. By maintaining opposite stresses in the nFET and pFET alloys or silicides, both types of transistors on a single chip or substrate can achieve an enhanced carrier mobility, thereby improving the performance of CMOS devices and integrated circuits.
摘要翻译：在制造包括nFET和PFET的互补金属氧化物半导体（CMOS）场效应晶体管的情况下，通过使栅电极的材料与金属反应来增强或调节载流子迁移率，以产生应力合金（优选CoSi 2Si，NiSi或PdSi）。在nFET和pFET两者的情况下，各合金的固有应力对相应晶体管的沟道产生相反的应力。通过在nFET和pFET合金或硅化物中保持相反的应力，单个芯片或衬底上的两种类型的晶体管可以实现增强的载流子迁移率，从而提高CMOS器件和集成电路的性能。

10. 发明申请

US20050087824A1 HIGH PERFORMANCE FET WITH LATERALLY THIN EXTENSION 失效
标题翻译：高性能FET，具有较小的延伸性
公开(公告)号：US20050087824A1
公开(公告)日：2005-04-28
申请号：US10605769
申请日：2003-10-24
申请人： Cyril Cabral , Omer Dokumaci , Oleg Gluschenkov
发明人： Cyril Cabral , Omer Dokumaci , Oleg Gluschenkov
IPC分类号： G05F1/10 , G05F3/02 , H01L21/28 , H01L21/3205 , H01L21/336 , H01L21/4763 , H01L21/8238 , H01L21/84 , H01L27/092 , H01L27/12 , H01L29/51 , H01L29/76 , H01L29/772 , H01L29/78 , H01L29/94 , H01L31/062 , H01L31/113 , H01L31/119
CPC分类号： H01L21/28194 , H01L21/28202 , H01L29/51 , H01L29/513 , H01L29/517 , H01L29/518 , H01L29/665 , H01L29/66545 , H01L29/66628 , H01L29/66636 , H01L29/7836
摘要： field effect transistor (FET), integrated circuit (IC) chip including the FETs and a method of forming the FETs. The FETs have a device channel and a gate above the device channel with a doped source/drain extension at said each end of the thin channel. A portion of a low resistance material layer (e.g., a silicide layer) is disposed on source/drain extensions. The portions on the doped extensions laterally form a direct contact with the doped source/drain extension. Any low resistance material layer on the gate is separated from the low resistance material portions on the source/drain extensions.
摘要翻译：场效应晶体管（FET），包括FET的集成电路（IC）芯片和形成FET的方法。 FET在器件沟道上方具有器件沟道和栅极，在薄沟道的每个端部具有掺杂的源极/漏极延伸。低电阻材料层（例如硅化物层）的一部分设置在源极/漏极延伸部分上。掺杂延伸部分上的部分横向形成与掺杂源极/漏极延伸部的直接接触。栅极上的任何低电阻材料层与源极/漏极延伸部分上的低电阻材料部分分离。

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