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1. 发明授权

US08148757B2 Semiconductor device, and its manufacturing method 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：US08148757B2
公开(公告)日：2012-04-03
申请号：US12447113
申请日：2007-10-23
申请人： Masayuki Terai , Shinji Fujieda , Akio Toda
发明人： Masayuki Terai , Shinji Fujieda , Akio Toda
IPC分类号： H01L29/04 , H01L29/92
CPC分类号： H01L21/28282 , H01L27/11565 , H01L27/11568 , H01L29/42344 , H01L29/42348 , H01L29/42352 , H01L29/66833 , H01L29/7923 , H01L29/7926
摘要： A channel is formed at a recessed portion or a projecting portion of a substrate, and a gate insulating film is formed so as to have first to third insulating regions along the channel. Each of the gate insulating films of the first and third insulating regions has a first gate insulating film containing no electric charge trap formed on a plane different from a principal surface of the substrate, an electric charge accumulating film containing an electric charge trap, and a second gate insulating film containing no electric charge trap. The gate insulating film of the second insulating region at the middle is formed on a plane parallel to the principal surface of the substrate and is composed of only a third gate insulating film containing no electric charge trap.
摘要翻译：在基板的凹部或突出部形成沟道，并且形成栅极绝缘膜，以沿着沟道具有第一至第三绝缘区域。第一绝缘区域和第三绝缘区域的每个栅极绝缘膜具有不包含形成在不同于基板的主面的平面上的电荷阱的第一栅极绝缘膜，含有电荷阱的电荷积累膜，以及不含电荷陷阱的第二栅绝缘膜。中间的第二绝缘区域的栅极绝缘膜形成在与基板的主表面平行的平面上，并且仅由不含电荷陷阱的第三栅极绝缘膜构成。

2. 发明申请

US20100090257A1 SEMICONDUCTOR DEVICE, AND ITS MANUFACTURING METHOD 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：US20100090257A1
公开(公告)日：2010-04-15
申请号：US12447113
申请日：2007-10-23
申请人： Masayuki Terai , Shinji Fujieda , Akio Toda
发明人： Masayuki Terai , Shinji Fujieda , Akio Toda
IPC分类号： H01L29/04 , H01L29/792 , H01L21/336
CPC分类号： H01L21/28282 , H01L27/11565 , H01L27/11568 , H01L29/42344 , H01L29/42348 , H01L29/42352 , H01L29/66833 , H01L29/7923 , H01L29/7926
摘要： A channel is formed at a recessed portion or a projecting portion of a substrate, and a gate insulating film is formed so as to have first to third insulating regions along the channel. Each of the gate insulating films of the first and third insulating regions has a first gate insulating film containing no electric charge trap formed on a plane different from a principal surface of the substrate, an electric charge accumulating film containing an electric charge trap, and a second gate insulating film containing no electric charge trap. The gate insulating film of the second insulating region at the middle is formed on a plane parallel to the principal surface of the substrate and is composed of only a third gate insulating film containing no electric charge trap.
摘要翻译：在基板的凹部或突出部形成沟道，并且形成栅极绝缘膜，以沿着沟道具有第一至第三绝缘区域。第一绝缘区域和第三绝缘区域的每个栅极绝缘膜具有不包含形成在不同于基板的主面的平面上的电荷阱的第一栅极绝缘膜，含有电荷阱的电荷积累膜，以及不含电荷陷阱的第二栅绝缘膜。中间的第二绝缘区域的栅极绝缘膜形成在与基板的主表面平行的平面上，并且仅由不含电荷陷阱的第三栅极绝缘膜构成。

3. 发明授权

US09748556B2 Negative electrode material for secondary battery, and secondary battery 有权
公开(公告)号：US09748556B2
公开(公告)日：2017-08-29
申请号：US14389514
申请日：2013-03-06
申请人： Akio Toda , Kimiyoshi Fukatsu , Ryota Yuge , Shinji Fujieda
发明人： Akio Toda , Kimiyoshi Fukatsu , Ryota Yuge , Shinji Fujieda
IPC分类号： H01M4/133 , C01B31/04 , H01M4/36 , H01M4/587 , H01M10/0525 , H01M4/02
CPC分类号： H01M4/133 , C01B32/20 , H01M4/36 , H01M4/587 , H01M10/0525 , H01M2004/021 , H01M2004/027
摘要： The present invention relates to a negative electrode material for secondary batteries, comprising graphite; wherein the graphite comprises hexagonal crystal graphite and rhombohedral crystal graphite, and has a low-crystalline carbon coating on a surface thereof; and the graphite has exothermic peaks in the range of 600° C. or lower and in the range of 690° C. or higher in DTA measurement, or the graphite has a full width at half maximum of a (101) peak of the hexagonal crystal graphite of 0.2575° or less in XRD measurement, or the graphite has an absolute value of the difference between the lattice strain obtained from (101) plane spacing of the hexagonal crystal graphite and the lattice strain obtained from (100) plane spacing of the hexagonal crystal graphite of 7.1×10−4 or less in XRD measurement.

4. 发明授权

US07064382B2 Nonvolatile memory and nonvolatile memory manufacturing method 失效
标题翻译：非易失性存储器和非易失性存储器制造方法
公开(公告)号：US07064382B2
公开(公告)日：2006-06-20
申请号：US11074064
申请日：2005-03-08
申请人： Noriaki Kodama , Kohji Kanamori , Junichi Suzuki , Teiichirou Nishizaka , Yasuhide Den , Shinji Fujieda , Akio Toda
发明人： Noriaki Kodama , Kohji Kanamori , Junichi Suzuki , Teiichirou Nishizaka , Yasuhide Den , Shinji Fujieda , Akio Toda
IPC分类号： H01L29/788
CPC分类号： H01L27/115 , H01L27/11521 , H01L29/1033 , H01L29/7845 , H01L29/7846 , H01L29/7881
摘要： A nonvolatile memory device includes source and drain regions formed in a semiconductor substrate, and an insulating film formed on a channel region between the source region and the drain region in the semiconductor substrate. The nonvolatile memory device also includes a dielectric film formed above the channel region to store electric charge, and a control gate formed on the dielectric film. Compressive stress in the channel region is equal to or less than 50 MPa.
摘要翻译：非易失性存储器件包括形成在半导体衬底中的源区和漏区，以及形成在半导体衬底中的源区和漏区之间的沟道区上的绝缘膜。非易失性存储器件还包括形成在通道区域上方以存储电荷的电介质膜，以及形成在电介质膜上的控制栅极。通道区域的压缩应力为50MPa以下。

5. 发明申请

US20050199945A1 Nonvolatile memory and nonvolatile memory manufacturing method 失效
标题翻译：非易失性存储器和非易失性存储器制造方法
公开(公告)号：US20050199945A1
公开(公告)日：2005-09-15
申请号：US11074064
申请日：2005-03-08
申请人： Noriaki Kodama , Kohji Kanamori , Junichi Suzuki , Teiichirou Nishizaka , Yasuhide Den , Shinji Fujieda , Akio Toda
发明人： Noriaki Kodama , Kohji Kanamori , Junichi Suzuki , Teiichirou Nishizaka , Yasuhide Den , Shinji Fujieda , Akio Toda
IPC分类号： H01L21/8247 , H01L21/8239 , H01L27/10 , H01L27/105 , H01L27/115 , H01L29/10 , H01L29/745 , H01L29/76 , H01L29/788 , H01L29/792
CPC分类号： H01L27/115 , H01L27/11521 , H01L29/1033 , H01L29/7845 , H01L29/7846 , H01L29/7881
摘要： A nonvolatile memory device includes source and drain regions formed in a semiconductor substrate, and an insulating film formed on a channel region between the source region and the drain region in the semiconductor substrate. The nonvolatile memory device also includes a dielectric film formed above the channel region to store electric charge, and a control gate formed on the dielectric film. Compressive stress in the channel region is equal to or less than 50 MPa.
摘要翻译：非易失性存储器件包括形成在半导体衬底中的源区和漏区，以及形成在半导体衬底中的源区和漏区之间的沟道区上的绝缘膜。非易失性存储器件还包括形成在通道区域上方以存储电荷的电介质膜，以及形成在电介质膜上的控制栅极。通道区域的压缩应力为50MPa以下。

6. 发明申请

US20060163647A1 MOS semiconductor device 有权
标题翻译： MOS半导体器件
公开(公告)号：US20060163647A1
公开(公告)日：2006-07-27
申请号：US11386833
申请日：2006-03-23
申请人： Akio Toda , Haruihiko Ono
发明人： Akio Toda , Haruihiko Ono
IPC分类号： H01L29/76
CPC分类号： H01L29/7842 , H01L21/823807 , H01L21/823878 , H01L2924/0002 , H01L2924/00
摘要： While using conventional manufacturing processes, it is intended to apply a compressive strain in the channel direction to the p-channel MOS field effect transistor and also apply a tensile strain in the channel direction to the n-channel MOS field effect transistor for increasing both MOS currents. In the MOS semiconductor device isolated by a trench device isolation region, the p-channel MOS field effect transistor is designed so that a length of a source/drain region in the channel direction is not more than 1 micrometer, and the gate length is not more than 0.2 micrometers. The n-channel MOS field effect transistor is designed so that a face of the source/drain region in parallel to the gate width direction is adjacent to the device isolation film with the inserted silicon nitride film, and a face of the source/drain region parallel to the gate length direction is adjacent to the device isolation film comprising the silicon oxide film only.
摘要翻译：在使用传统制造工艺的过程中，旨在将通道方向上的压缩应变施加到p沟道MOS场效应晶体管，并且还在沟道方向施加拉应变至n沟道MOS场效应晶体管，以增加MOS 电流。在由沟槽器件隔离区隔离的MOS半导体器件中，p沟道MOS场效应晶体管被设计成使得沟道方向上的源极/漏极区域的长度不大于1微米，并且栅极长度不是大于0.2微米。 n沟道MOS场效应晶体管被设计成使得源极/漏极区域平行于栅极宽度方向的面与所插入的氮化硅膜相邻于器件隔离膜，并且源极/漏极区域的面平行于栅极长度方向与仅包含氧化硅膜的器件隔离膜相邻。

7. 发明申请

US20130064491A1 OPTICAL MODULATOR 有权
标题翻译：光学调制器
公开(公告)号：US20130064491A1
公开(公告)日：2013-03-14
申请号：US13582841
申请日：2011-03-01
申请人： Junichi Fujikata , Motofumi Saitoh , Jun Ushida , Akio Toda
发明人： Junichi Fujikata , Motofumi Saitoh , Jun Ushida , Akio Toda
IPC分类号： G02F1/035 , H01L21/02
CPC分类号： G02F1/035 , G02F1/025 , H01L21/02
摘要： To provide an optical modulator having a reduced size and reduced power consumption and capable of being easily connected to a waveguide and a method of manufacturing the optical modulator. The optical modulator has at least semiconductor layer (8) having a rib-shaped portion and doped so as to be of a first conduction type, dielectric layer (11) laid on first-conduction-type semiconductor layer (8), and semiconductor layer (9) laid on dielectric layer (11), having the width at the side opposite from dielectric layer (11) increased relative to the width of the rib-shaped portion, and doped so as to be of a second conduction type.
摘要翻译：提供具有减小的尺寸和降低的功率消耗并且能够容易地连接到波导的光学调制器和制造光学调制器的方法。光调制器至少具有肋状部分并掺杂成第一导电类型的半导体层（8），布置在第一导电型半导体层（8）上的电介质层（11）和半导体层放置在电介质层（11）上的与介电层（11）相对的宽度相对于肋状部分的宽度增加并且掺杂成第二导电类型的放电层（9）。

8. 发明申请

US20050219738A1 Insulation sheet and disk device provided with the same 审中-公开
标题翻译：绝缘片与磁盘装置相同
公开(公告)号：US20050219738A1
公开(公告)日：2005-10-06
申请号：US11082034
申请日：2005-03-17
申请人： Yukio Iida , Jun Nishida , Akio Toda , Hiroshi Okamura
发明人： Yukio Iida , Jun Nishida , Akio Toda , Hiroshi Okamura
IPC分类号： G11B33/08 , G11B17/00 , G11B25/04 , G11B33/12 , H05K1/02 , H05K3/28
CPC分类号： G11B33/121 , G11B25/043 , H05K1/0256 , H05K1/0271 , H05K3/284 , H05K2201/2045 , H05K2203/1311
摘要： A disk device has a motor provided on a bottom wall of a case. A PCB is located opposite an outer surface of the bottom wall of the case, and an insulation sheet is sandwiched between the outer surface of the bottom wall and the PCB. The insulation sheet has a sheet body formed of an insulator and located opposite the outer surface of the bottom wall and a plurality of damping members provided independently of one another on the sheet body. The damping members include a first damping member situated near the motor and abutting against the PCB and a second damping member abutting against an electronic component mounted on the PCB.
摘要翻译：磁盘装置具有设置在壳体的底壁上的电动机。 PCB与壳体的底壁的外表面相对设置，并且绝缘片夹在底壁的外表面和PCB之间。绝缘片具有由绝缘体形成并且与底壁的外表面相对并且在片体上彼此独立设置的多个阻尼构件的片体。阻尼构件包括位于马达附近并抵靠PCB的第一阻尼构件和抵靠安装在PCB上的电子部件的第二阻尼构件。

9. 发明授权

US5295263A Programmable controller which allows control in formation to be updated during execution 失效
标题翻译：可编程控制器，允许在执行期间更新控制
公开(公告)号：US5295263A
公开(公告)日：1994-03-15
申请号：US823965
申请日：1992-01-22
申请人： Kenji Kojima , Akio Toda
发明人： Kenji Kojima , Akio Toda
IPC分类号： G05B19/05 , G06F9/445 , G06F9/00
CPC分类号： G06F8/67 , Y02P90/265
摘要： A programmable controller having a loading feature for changing such control information as control programs. The controller comprises a load execution unit and an allocation unit. The load execution unit checks, upon receipt of new control information, the execution state of the program to be changed based on management information stored in a management table. The load execution unit loads the new control information into an area indicated by addresses held in a management table if the program is in non-executing or non-executable state. The load execution unit loads the new control information into a reserved area indicated by addresses held in a reserved table if the program is in executing or executable state. The allocation unit replaces the content of the addresses held in the management table with the content of the addresses held in the reserved table after the load execution unit has loaded the new control information into the reserved area.
摘要翻译：一种具有用于改变控制程序的控制信息的加载特征的可编程控制器。控制器包括负载执行单元和分配单元。负载执行单元在接收到新的控制信息时，根据存储在管理表中的管理信息来检查要变更的程序的执行状态。如果程序处于非执行或不可执行状态，则负载执行单元将新的控制信息加载到由管理表中所保存的地址指示的区域内。如果程序正在执行或可执行状态，则负载执行单元将新的控制信息加载到由保留表保存的地址指示的保留区域中。在负载执行单元将新的控制信息加载到保留区域之后，分配单元将保存在管理表中的地址的内容替换为保留在保留表中的地址的内容。

10. 发明申请

US20110311178A1 OPTICAL MODULATION STRUCTURE AND OPTICAL MODULATOR 有权
标题翻译：光学调制结构和光学调制器
公开(公告)号：US20110311178A1
公开(公告)日：2011-12-22
申请号：US13202680
申请日：2010-02-18
申请人： Junichi Fujikata , Jun Ushida , Akio Toda , Motofumi Saitoh
发明人： Junichi Fujikata , Jun Ushida , Akio Toda , Motofumi Saitoh
IPC分类号： G02F1/025
CPC分类号： G02F1/025
摘要： The components are a lower clad layer (102), a first silicon layer (103) that is formed on the lower clad layer (102) as a single body made of silicon of a first conduction type and has a slab region (105) that is disposed at a core (104) and on both sides of the core (104) and connects to the core, a concave section (104a) that is formed in the top surface of the core (104), and a second silicon layer (109) of a second conduction type that is formed inside the concave section (104a) with an intervening dielectric layer (108) to fill the inside of the concave section (104a).
摘要翻译：这些部件是下包层（102），第一硅层（103），其形成在下包层（102）上，作为由第一导电类型的硅制成的单体，并具有板区域（105）设置在芯部（104）处并且在芯部（104）的两侧并且连接到芯部，形成在芯部（104）的顶表面中的凹部（104a）和第二硅层（ 109），其形成在所述凹部（104a）的内部，并具有填充所述凹部（104a）的内部的中间介电层（108）。

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