专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US07009404B2 Method and device for testing the ESD resistance of a semiconductor component 有权
标题翻译：用于测试半导体部件的ESD电阻的方法和装置
公开(公告)号：US07009404B2
公开(公告)日：2006-03-07
申请号：US10160740
申请日：2002-05-31
申请人： Martin Wendel , Richard Owen , Harald Gossner , Wolfgang Stadler , Philipp Riess , Martin Streibl , Kai Esmark
发明人： Martin Wendel , Richard Owen , Harald Gossner , Wolfgang Stadler , Philipp Riess , Martin Streibl , Kai Esmark
IPC分类号： G01R31/08 , G01R27/08
CPC分类号： G01R31/002 , G01R31/129
摘要： To test the ESD resistance of a semiconductor component, for example of a NOS transistor, which can be used as a PSD protective element in a chip, a direct current characteristic of the semiconductor component is monitored and the ESD resistance of the respective semiconductor component is inferred depending on this. In particular, the direct current failure threshold of the semiconductor component at which an increased leakage current occurs in the non-conducting direction of the semiconductor component can be monitored in operation of the semiconductor component using an applied direct current and the ESD resistance of the semiconductor component inferred depending on a change in this direct current failure threshold.
摘要翻译：为了测试可用作芯片中的PSD保护元件的例如可用作PSD保护元件的NOS晶体管的半导体部件的ESD电阻，监视半导体部件的直流特性，并且各半导体部件的ESD电阻为据此推断。特别地，可以在使用所施加的直流电流和半导体的ESD电阻的半导体组件的操作中监视在半导体组件的非导通方向上发生增加的漏电流的半导体组件的直流故障阈值根据该直流故障阈值的变化推断分量。

2. 发明授权

US06905892B2 Operating method for a semiconductor component 有权
标题翻译：半导体元件的操作方法
公开(公告)号：US06905892B2
公开(公告)日：2005-06-14
申请号：US10200067
申请日：2002-07-19
申请人： Kai Esmark , Harald Gossner , Philipp Riess , Wolfgang Stadler , Martin Streibl , Martin Wendel
发明人： Kai Esmark , Harald Gossner , Philipp Riess , Wolfgang Stadler , Martin Streibl , Martin Wendel
IPC分类号： H01L27/04 , H01L21/822 , H01L23/60 , H01L29/74 , G01R31/26
CPC分类号： H01L23/60 , H01L2924/0002 , H01L2924/00
摘要： The present invention creates an operating method for a semiconductor component having a substrate; having a conductive polysilicon strip which is applied to the substrate; having a first and a second electrical contact which are connected to the conductive polysilicon strip such that this forms an electrical resistance in between them; with the semiconductor component being operated reversibly in a current/voltage range in which it has a first differential resistance (Rdiff1) up to a current limit value (It) corresponding to an upper voltage limit value (Vt) and, at current values greater than this, has a second differential resistance (Rdiff2), which is less than the first differential resistance (Rdiff1).
摘要翻译：本发明创造了具有基板的半导体部件的操作方法; 具有施加到衬底的导电多晶硅条; 具有连接到导电多晶硅条的第一和第二电接触，使得它们之间形成电阻; 半导体部件在其具有第一差分电阻（Rdiff 1）的电流/电压范围内可逆地操作，直到对应于上限电压限制值（Vt）的电流限制值（It），并且在当前值更大具有小于第一差分电阻（Rdiff 1）的第二差分电阻（Rdiff 2）。

3. 发明授权

US06930501B2 Method for determining an ESD/latch-up strength of an integrated circuit 失效
公开(公告)号：US06930501B2
公开(公告)日：2005-08-16
申请号：US10866863
申请日：2004-06-14
申请人： Silke Bargstädt-Franke , Kai Esmark , Harald Gossner , Philipp Riess , Wolfgang Stadler , Martin Streibl , Martin Wendel
发明人： Silke Bargstädt-Franke , Kai Esmark , Harald Gossner , Philipp Riess , Wolfgang Stadler , Martin Streibl , Martin Wendel
IPC分类号： H01L23/544 , H01L23/60 , G01R31/26
CPC分类号： H01L22/34 , H01L23/60 , H01L2924/0002 , H01L2924/3011 , H01L2924/00
摘要： A method for determining an ESD/latch-up strength of an integrated circuit includes producing an integrated circuit and a test structure using the same fabrication process. Electrical parameters at the test structure are measured and characteristic values associated with the integrated circuit are derived from the measured parameter values, wherein the characteristic values characterize an ESD or latch-up characteristic curve associated with the integrated circuit. The method further includes testing whether the characteristic values in each case lie within a predetermined range assigned to them, wherein the ranges are chosen such that a desired ESD/latch-up strength is present if the characteristic values in each case lie within their range.

4. 发明申请

US20050003564A1 Method for determining an ESD/latch-up strength of an integrated circuit 失效
标题翻译：用于确定集成电路的ESD /闭锁强度的方法
公开(公告)号：US20050003564A1
公开(公告)日：2005-01-06
申请号：US10866863
申请日：2004-06-14
申请人： Silke Bargstadt-Franke , Kai Esmark , Harald Gossner , Philipp Riess , Wolfgang Stadler , Martin Streibl , Martin Wendel
发明人： Silke Bargstadt-Franke , Kai Esmark , Harald Gossner , Philipp Riess , Wolfgang Stadler , Martin Streibl , Martin Wendel
IPC分类号： H01L23/544 , H01L23/60 , G01R31/26
CPC分类号： H01L22/34 , H01L23/60 , H01L2924/0002 , H01L2924/3011 , H01L2924/00
摘要： A method for determining an ESD/latch-up strength of an integrated circuit includes producing an integrated circuit and a test structure using the same fabrication process. Electrical parameters at the test structure are measured and characteristic values associated with the integrated circuit are derived from the measured parameter values, wherein the characteristic values characterize an ESD or latch-up characteristic curve associated with the integrated circuit. The method further includes testing whether the characteristic values in each case lie within a predetermined range assigned to them, wherein the ranges are chosen such that a desired ESD/latch-up strength is present if the characteristic values in each case lie within their range.
摘要翻译：用于确定集成电路的ESD /闭锁强度的方法包括使用相同的制造工艺制造集成电路和测试结构。测量测试结构的电气参数，并且从测量的参数值导出与集成电路相关联的特征值，其中特征值表征与集成电路相关联的ESD或闭锁特性曲线。该方法还包括测试每种情况下的特征值是否在分配给它们的预定范围内，其中选择范围使得如果每种情况下的特征值在其范围内，则存在期望的ESD /闩锁强度。

5. 发明授权

US07359169B2 Circuit for protecting integrated circuits against electrostatic discharges 有权
标题翻译：保护集成电路免受静电放电的电路
公开(公告)号：US07359169B2
公开(公告)日：2008-04-15
申请号：US10536176
申请日：2003-11-24
申请人： Kai Esmark , Harald Gossner , Wolfgang Stadler , Martin Streibl , Martin Wendel
发明人： Kai Esmark , Harald Gossner , Wolfgang Stadler , Martin Streibl , Martin Wendel
IPC分类号： H02H9/00 , H02H9/08 , H02H3/20 , H02H9/04 , H02H3/22 , H02H1/00 , H02H1/04 , H02H9/06 , H01C7/12
CPC分类号： H02H9/046
摘要： A circuit is described that protects an integrated circuit from electrostatic discharges or electrical over-stress. The circuit arrangement has first and second protective elements connected in series between a connection of the integrated circuit and a supply voltage. When electrostatic discharges or electrical over-stress occurs, current flows through the conductive path formed through the first and second protective elements. A current path that contains a circuit element limits current through the first protective element is connected in parallel with the first protective element. The first protective element has blocking behavior when no electrostatic discharges or electrical over-stress occurs, a limited current flows through the current path and the second protective element.
摘要翻译：描述了保护集成电路免受静电放电或电过压的电路。电路装置具有在集成电路的连接和电源电压之间串联连接的第一和第二保护元件。当发生静电放电或电过压时，电流流过形成在第一和第二保护元件上的导电路径。包含电路元件的电流路径限制通过第一保护元件的电流与第一保护元件并联连接。当不产生静电放电或电过度应力时，第一保护元件具有阻塞行为，有限的电流流过电流通路和第二保护元件。

6. 发明申请

US20060056121A1 Circuit for protecting integrated circuits against electrostatic discharges 有权
标题翻译：保护集成电路免受静电放电的电路
公开(公告)号：US20060056121A1
公开(公告)日：2006-03-16
申请号：US10536176
申请日：2003-11-24
申请人： Kai Esmark , Harald Gossner , Wolfgang Stadler , Martin Streibl , Martin Wendel
发明人： Kai Esmark , Harald Gossner , Wolfgang Stadler , Martin Streibl , Martin Wendel
IPC分类号： H02H9/00
CPC分类号： H02H9/046
摘要： A circuit is described that protects an integrated circuit from electrostatic discharges or electrical over-stress. The circuit arrangement has first and second protective elements connected in series between a connection of the integrated circuit and a supply voltage. When electrostatic discharges or electrical over-stress occurs, current flows through the conductive path formed through the first and second protective elements. A current path that contains a circuit element limits current through the first protective element is connected in parallel with the first protective element. The first protective element has blocking behavior when no electrostatic discharges or electrical over-stress occurs, a limited current flows through the current path and the second protective element.
摘要翻译：描述了保护集成电路免受静电放电或电过压的电路。电路装置具有在集成电路的连接和电源电压之间串联连接的第一和第二保护元件。当发生静电放电或电过压时，电流流过形成在第一和第二保护元件上的导电路径。包含电路元件的电流路径限制通过第一保护元件的电流与第一保护元件并联连接。当不产生静电放电或电过度应力时，第一保护元件具有阻塞行为，有限的电流流过电流通路和第二保护元件。

7. 发明申请

US20050195540A1 ESD protective circuit with collector-current-controlled triggering for a monolithically integrated circuit 有权
标题翻译：具有集电极电流控制触发的ESD保护电路用于单片集成电路
公开(公告)号：US20050195540A1
公开(公告)日：2005-09-08
申请号：US11070824
申请日：2005-03-01
申请人： Martin Streibl , Kai Esmark , Christian Russ , Martin Wendel , Harald Gossner
发明人： Martin Streibl , Kai Esmark , Christian Russ , Martin Wendel , Harald Gossner
IPC分类号： H01L23/60 , H02H9/00 , H02H9/02
CPC分类号： H01L27/0262 , H01L27/0259
摘要： An ESD protective circuit protects an input or output of a monolithically integrated circuit. The ESD protective circuit has at least one bipolar transistor structure and one ESD protective element between two supply networks. The emitter of the bipolar transistor structure is electrically connected to the input or output, while the base is electrically connected to one of the two supply networks. The collector produces a current signal, which is used for triggering of the ESD protective element, when an ESD load occurs at the input or output.
摘要翻译： ESD保护电路保护单片集成电路的输入或输出。 ESD保护电路在两个供电网络之间具有至少一个双极晶体管结构和一个ESD保护元件。双极晶体管结构的发射极电连接到输入或输出，而基极电连接到两个供电网络之一。当输入或输出发生ESD负载时，集电极产生电流信号，用于触发ESD保护元件。

8. 发明授权

US07087938B2 ESD protective circuit with collector-current-controlled triggering for a monolithically integrated circuit 有权
标题翻译：具有集电极电流控制触发的ESD保护电路用于单片集成电路
公开(公告)号：US07087938B2
公开(公告)日：2006-08-08
申请号：US11070824
申请日：2005-03-01
申请人： Martin Streibl , Kai Esmark , Christian Russ , Martin Wendel , Harald Gossner
发明人： Martin Streibl , Kai Esmark , Christian Russ , Martin Wendel , Harald Gossner
IPC分类号： H01L29/72 , H02H3/00
CPC分类号： H01L27/0262 , H01L27/0259
摘要： An ESD protective circuit protects an input or output of a monolithically integrated circuit. The ESD protective circuit has at least one bipolar transistor structure and one ESD protective element between two supply networks. The emitter of the bipolar transistor structure is electrically connected to the input or output, while the base is electrically connected to one of the two supply networks. The collector produces a current signal, which is used for triggering of the ESD protective element, when an ESD load occurs at the input or output.
摘要翻译： ESD保护电路保护单片集成电路的输入或输出。 ESD保护电路在两个供电网络之间具有至少一个双极晶体管结构和一个ESD保护元件。双极晶体管结构的发射极电连接到输入或输出，而基极电连接到两个供电网络之一。当输入或输出发生ESD负载时，集电极产生电流信号，用于触发ESD保护元件。

9. 发明授权

US07694247B2 Identification of ESD and latch-up weak points in an integrated circuit 有权
标题翻译：识别集成电路中的ESD和闭锁弱点
公开(公告)号：US07694247B2
公开(公告)日：2010-04-06
申请号：US10569986
申请日：2005-03-17
申请人： Kai Esmark , Harald Gossner , Wolfgang Stadler , Marin Streibl
发明人： Kai Esmark , Harald Gossner , Wolfgang Stadler , Marin Streibl
IPC分类号： G06F17/50
CPC分类号： G06F17/5036
摘要： A program-controlled arrangement for the identification of ESD and/or latch-up weak points in the design or in the concept of an integrated circuit comprises a pre-processor, which processes first data about the description of the integrated circuit, second data about already ESD-characterized circuit parts of the integrated circuit, and third data which contain information about ESD test standards. A simulator device is connected downstream of the pre-processor which has a simulator which, by using the fourth and fifth data generated by the pre-processor, performs an ESD simulation of the integrated circuit, which has a monitoring controller for controlling the ESD simulation sequence in the simulator. An analysis device is connected downstream of the simulator device, which performs an evaluation of the sixth data generated in the simulator device with regard to their physical validity and meaningfulness, and marks the simulation runs having physically relevant ESD failure events.
摘要翻译：用于在设计中或集成电路的概念中识别ESD和/或闭锁弱点的程序控制布置包括预处理器，其处理关于集成电路的描述的第一数据，关于集成电路已经具有ESD特征的电路部件，以及包含有关ESD测试标准信息的第三个数据。模拟器装置连接在预处理器的下游，其具有模拟器，通过使用由预处理器生成的第四和第五数据执行集成电路的ESD模拟，其具有用于控制ESD模拟的监视控制器序列在模拟器中。分析装置连接在模拟器装置的下游，对其模拟装置的物理有效性和有意义性进行评估，并对具有物理上相关的ESD故障事件的模拟运行进行标记。

10. 发明申请

US20070165344A1 Esd test arrangement and method 有权
标题翻译： Esd测试方法和方法
公开(公告)号：US20070165344A1
公开(公告)日：2007-07-19
申请号：US10569986
申请日：2005-03-17
申请人： Kai Esmark , Harald Gossner , Wolfgang Stadler , Marin Streibl
发明人： Kai Esmark , Harald Gossner , Wolfgang Stadler , Marin Streibl
IPC分类号： H02H9/00
CPC分类号： G06F17/5036
摘要： The invention relates to a program-controlled arrangement and a method for the identification of ESD and/or latch-up weak points in the design or in the concept of an integrated circuit, having a pre-processor, which processes first data about the description of the integrated circuit, second data about already ESD-characterized circuit parts of the integrated circuit, and third data which contain information about ESD test standards, having a simulator device connected downstream of the pre-processor, which has a simulator which, by using the fourth and fifth data generated by the pre-processor, performs an ESD simulation of the integrated circuit, which has a monitoring controller for controlling the ESD simulation sequence in the simulator, having an analysis device connected downstream of the simulator device, which performs an evaluation of the sixth data generated in the simulator device with regard to their physical validity and meaningfulness, and marks the simulation runs having physically relevant ESD failure events.
摘要翻译：本发明涉及一种用于在集成电路的设计或概念中识别ESD和/或闭锁弱点的程序控制布置和方法，所述集成电路具有预处理器，所述预处理器处理关于描述的第一数据集成电路的已经具有ESD特征的电路部分的第二数据以及包含关于ESD测试标准的信息的第三数据，具有连接在预处理器下游的模拟器装置，模拟器装置具有通过使用的模拟器由预处理器生成的第四和第五数据执行集成电路的ESD仿真，其具有用于控制模拟器中的ESD模拟序列的监视控制器，具有连接在模拟器装置的下游的分析装置，该分析装置执行对模拟器装置中生成的第六个数据的物理有效性和有意义进行评估，并标记模拟运行导致身体相关的ESD故障事件。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式