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1. 发明申请

US20070165344A1 Esd test arrangement and method 有权
标题翻译： Esd测试方法和方法
公开(公告)号：US20070165344A1
公开(公告)日：2007-07-19
申请号：US10569986
申请日：2005-03-17
申请人： Kai Esmark , Harald Gossner , Wolfgang Stadler , Marin Streibl
发明人： Kai Esmark , Harald Gossner , Wolfgang Stadler , Marin Streibl
IPC分类号： H02H9/00
CPC分类号： G06F17/5036
摘要： The invention relates to a program-controlled arrangement and a method for the identification of ESD and/or latch-up weak points in the design or in the concept of an integrated circuit, having a pre-processor, which processes first data about the description of the integrated circuit, second data about already ESD-characterized circuit parts of the integrated circuit, and third data which contain information about ESD test standards, having a simulator device connected downstream of the pre-processor, which has a simulator which, by using the fourth and fifth data generated by the pre-processor, performs an ESD simulation of the integrated circuit, which has a monitoring controller for controlling the ESD simulation sequence in the simulator, having an analysis device connected downstream of the simulator device, which performs an evaluation of the sixth data generated in the simulator device with regard to their physical validity and meaningfulness, and marks the simulation runs having physically relevant ESD failure events.
摘要翻译：本发明涉及一种用于在集成电路的设计或概念中识别ESD和/或闭锁弱点的程序控制布置和方法，所述集成电路具有预处理器，所述预处理器处理关于描述的第一数据集成电路的已经具有ESD特征的电路部分的第二数据以及包含关于ESD测试标准的信息的第三数据，具有连接在预处理器下游的模拟器装置，模拟器装置具有通过使用的模拟器由预处理器生成的第四和第五数据执行集成电路的ESD仿真，其具有用于控制模拟器中的ESD模拟序列的监视控制器，具有连接在模拟器装置的下游的分析装置，该分析装置执行对模拟器装置中生成的第六个数据的物理有效性和有意义进行评估，并标记模拟运行导致身体相关的ESD故障事件。

2. 发明授权

US07694247B2 Identification of ESD and latch-up weak points in an integrated circuit 有权
标题翻译：识别集成电路中的ESD和闭锁弱点
公开(公告)号：US07694247B2
公开(公告)日：2010-04-06
申请号：US10569986
申请日：2005-03-17
申请人： Kai Esmark , Harald Gossner , Wolfgang Stadler , Marin Streibl
发明人： Kai Esmark , Harald Gossner , Wolfgang Stadler , Marin Streibl
IPC分类号： G06F17/50
CPC分类号： G06F17/5036
摘要： A program-controlled arrangement for the identification of ESD and/or latch-up weak points in the design or in the concept of an integrated circuit comprises a pre-processor, which processes first data about the description of the integrated circuit, second data about already ESD-characterized circuit parts of the integrated circuit, and third data which contain information about ESD test standards. A simulator device is connected downstream of the pre-processor which has a simulator which, by using the fourth and fifth data generated by the pre-processor, performs an ESD simulation of the integrated circuit, which has a monitoring controller for controlling the ESD simulation sequence in the simulator. An analysis device is connected downstream of the simulator device, which performs an evaluation of the sixth data generated in the simulator device with regard to their physical validity and meaningfulness, and marks the simulation runs having physically relevant ESD failure events.
摘要翻译：用于在设计中或集成电路的概念中识别ESD和/或闭锁弱点的程序控制布置包括预处理器，其处理关于集成电路的描述的第一数据，关于集成电路已经具有ESD特征的电路部件，以及包含有关ESD测试标准信息的第三个数据。模拟器装置连接在预处理器的下游，其具有模拟器，通过使用由预处理器生成的第四和第五数据执行集成电路的ESD模拟，其具有用于控制ESD模拟的监视控制器序列在模拟器中。分析装置连接在模拟器装置的下游，对其模拟装置的物理有效性和有意义性进行评估，并对具有物理上相关的ESD故障事件的模拟运行进行标记。

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