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1. 发明授权

US5828616A Sensing scheme for flash memory with multilevel cells 失效
公开(公告)号：US5828616A
公开(公告)日：1998-10-27
申请号：US801004
申请日：1997-02-19
申请人： Mark E. Bauer , Sanjay Talreja , Albert Fazio , Gregory Atwood , Johnny Javanifard , Kevin W. Frary
发明人： Mark E. Bauer , Sanjay Talreja , Albert Fazio , Gregory Atwood , Johnny Javanifard , Kevin W. Frary
IPC分类号： G11C13/00 , G11C11/56 , G11C7/00
CPC分类号： G11C11/5621 , G11C11/5642 , G11C2211/5632
摘要： Methods and apparatus for determining the state of a memory cell having more than two possible states are disclosed. For a first embodiment, the state of a flash cell having n states, where n is a power of 2, is determined by selectively comparing the threshold voltage V.sub.t of a selected memory cell to (n-1) reference voltages. For every two states, a single comparator is provided such that the total number of comparators is equal to the number of bits stored in the memory cell.

2. 发明授权

US5748546A Sensing scheme for flash memory with multilevel cells 失效
标题翻译：具有多电平单元的闪存感测方案
公开(公告)号：US5748546A
公开(公告)日：1998-05-05
申请号：US827670
申请日：1997-04-10
申请人： Mark E. Bauer , Sanjay Talreja , Kevin W. Frary , Gregory Atwood , Albert Fazio , Johnny Javanifard
发明人： Mark E. Bauer , Sanjay Talreja , Kevin W. Frary , Gregory Atwood , Albert Fazio , Johnny Javanifard
IPC分类号： G11C13/00 , G11C11/56 , G11C7/00
CPC分类号： G11C11/5621 , G11C11/5642 , G11C2211/5632
摘要： Methods and apparatus for determining the state of a memory cell having more than two possible states are disclosed. For a first embodiment, the state of a flash cell having n states, where n is a power of 2, is determined by selectively comparing the threshold voltage V.sub.t of a selected memory cell to (n-1) reference voltages. For every two states, a single comparator is provided such that the total number of comparators is equal to the number of bits stored in the memory cell.
摘要翻译：公开了用于确定具有多于两种可能状态的存储单元的状态的方法和装置。对于第一实施例，通过选择性地将所选择的存储器单元的阈值电压Vt与（n-1）个参考电压进行比较来确定具有n个状态的闪存单元的状态，其中n是2的幂。对于每两个状态，提供单个比较器，使得比较器的总数等于存储在存储单元中的位数。

3. 发明授权

US5485422A Drain bias multiplexing for multiple bit flash cell 失效
标题翻译：多位闪存单元的漏极偏置复用
公开(公告)号：US5485422A
公开(公告)日：1996-01-16
申请号：US252684
申请日：1994-06-02
申请人： Mark E. Bauer , Kevin W. Frary , Sanjay S. Talreja
发明人： Mark E. Bauer , Kevin W. Frary , Sanjay S. Talreja
IPC分类号： G11C11/56 , G11C11/34
CPC分类号： G11C11/5621 , G11C11/5642 , G11C2211/5632 , G11C2211/5641
摘要： A memory device is disclosed which includes memory cells having m possible states, where m is at least 2. The memory device includes a multiplexed pair of output paths, wherein each output path is coupled to sense the state of a memory cell and includes a read path circuit, a column load circuit, and a comparator. Provided between the pair of output paths is a switching circuit for coupling the comparators to one another in response to a control signal. For single-bit read operations, each output path senses and outputs the data of the associated memory cell, and the control signal is inactive. When the control signal is active, the read path circuit and column load circuit of one of the output paths is disabled and the switching circuit couples the other read path circuit to the second comparator such that the state of the memory cell is sensed by two comparators.
摘要翻译：公开了一种存储器件，其包括具有m个可能状态的存储器单元，其中m至少为2.存储器件包括多路输出路径对，其中每个输出路径被耦合以感测存储器单元的状态，并且包括读取路径电路，列负载电路和比较器。在一对输出路径之间设置有用于响应于控制信号将比较器彼此耦合的开关电路。对于单位读取操作，每个输出路径检测并输出相关存储单元的数据，并且控制信号无效。当控制信号有效时，其中一个输出路径的读路径电路和列负载电路被禁止，并且开关电路将另一个读路径电路耦合到第二比较器，使得存储单元的状态由两个比较器。

4. 发明授权

US5539690A Write verify schemes for flash memory with multilevel cells 失效
标题翻译：使用多层单元写闪存的验证方案
公开(公告)号：US5539690A
公开(公告)日：1996-07-23
申请号：US252747
申请日：1994-06-02
申请人： Sanjay S. Talreja , Mark E. Bauer , Kevin W. Frary , Phillip M. L. Kwong
发明人： Sanjay S. Talreja , Mark E. Bauer , Kevin W. Frary , Phillip M. L. Kwong
IPC分类号： G11C11/56 , G11C11/34
CPC分类号： G11C11/5621 , G11C11/5628 , G11C11/5642 , G11C2211/5621 , G11C2211/5632 , G11C2211/5634
摘要： Schemes for verifying the successful programming of a memory cell having more than two possible states are disclosed. Each program verify reference flash cell is set to have a V.sub.t that defines a boundary of a possible state for the selected flash cell. For a first embodiment, program verify reference flash cells are used in the place of read reference cells to perform a binary search read operation similar to a standard read operation for the memory device architecture. The data sensed by the write verify operation is compared to expected data. For a second embodiment, a single program verify reference flash cell is used to define a threshold voltage beyond which the floating gate of the selected flash cell must be programmed to pass the write verify operation. Thus, for the second embodiment, the program verify reference flash cell is used to verify the analog V.sub.t voltage level of the selected flash cell, rather than to determine the data of the selected flash cell, as is done for the first embodiment.
摘要翻译：公开了用于验证具有两个以上可能状态的存储单元的成功编程的方案。每个程序验证参考闪存单元被设置为具有定义所选闪存单元的可能状态的边界的Vt。对于第一实施例，使用程序验证参考闪存单元来代替读取参考单元来执行类似于用于存储器件架构的标准读取操作的二进制搜索读取操作。将通过写入验证操作感测的数据与预期数据进行比较。对于第二实施例，使用单个程序验证参考闪存单元来定义阈值电压，超过该阈值电压的所选闪存单元的浮置栅极必须被编程以通过写入验证操作。因此，对于第二实施例，程序验证参考闪存单元用于验证所选择的闪存单元的模拟Vt电压电平，而不是确定所选择的闪存单元的数据，如第一实施例所做的那样。

5. 发明授权

US5663923A Nonvolatile memory blocking architecture 失效
标题翻译：非易失性内存阻塞架构
公开(公告)号：US5663923A
公开(公告)日：1997-09-02
申请号：US430882
申请日：1995-04-28
申请人： Robert L. Baltar , Mark E. Bauer , Kevin W. Frary , Steven D. Pudar , Sherif R. Sweha
发明人： Robert L. Baltar , Mark E. Bauer , Kevin W. Frary , Steven D. Pudar , Sherif R. Sweha
IPC分类号： G11C8/12 , G11C16/08 , G11C7/00
CPC分类号： G11C8/12 , G11C16/08
摘要： A nonvolatile memory includes a global line and a first block and a second block. The first block includes a plurality of first local lines and a first local decoder coupled to the global line and the first local lines for selectively coupling the global line to one of the first local lines in accordance with an address when the first local decoder is enabled and for isolating the first local lines from the global line when the first local decoder is disabled. The second block includes a plurality of second local lines and a second local decoder coupled to the global line and the second local lines for selectively coupling the global line to one of the second local lines in accordance with the address when the second local decoder is enabled and for isolating the second local lines from the global line when the second local decoder is disabled such that interference between the first and second blocks is eliminated during memory operations.
摘要翻译：非易失性存储器包括全局线，第一块和第二块。第一块包括多个第一本地线和耦合到全局线的第一本地解码器和第一本地线，用于根据当第一本地解码器被使能时的地址选择性地将全局线耦合到第一本地线之一并且当第一本地解码器被禁用时，用于将第一局部线与全局线隔开。第二块包括多个第二本地线和耦合到全局线的第二本地解码器和第二本地线，用于当第二本地解码器被使能时根据地址选择性地将全局线耦合到第二本地线之一并且当所述第二本地解码器被禁用时，用于将所述第二本地线路与全局线路隔离，使得在存储器操作期间消除所述第一和第二块之间的干扰。

6. 发明授权

US5243575A Address transition detection to write state machine interface circuit for flash memory 失效
标题翻译：地址转换检测写入闪存的状态机接口电路
公开(公告)号：US5243575A
公开(公告)日：1993-09-07
申请号：US901266
申请日：1992-06-19
申请人： Sachidanandan Sambandan , Peter K. Hazen , Kevin W. Frary
发明人： Sachidanandan Sambandan , Peter K. Hazen , Kevin W. Frary
IPC分类号： G06F12/02 , G11C8/18 , G11C16/02 , G11C16/06 , G11C16/32 , G11C17/00
CPC分类号： G11C16/32 , G11C8/18
摘要： A circuit to ensure that a flash memory device with a write state machine ("WSM") and address transition detection ("ATD") provides correct data after a write/erase step, after an erase suspend command is issued or when the device comes out of deep power-down mode. Whenever the WSM takes control of the device the ATD circuits are disabled. When the WSM relinquishes control over the read path it enables ATD by deasserting the disable ATD bar ("DATDB") signal. An internal signal that is a logical inversion of the chip enable bar ("CEB") input is used along with the DATDB signal to generate ATD pulses. Hence, if the user presents a valid address at the address pins with CEB held deasserted when entering the erase suspend mode, the deassertion of the DATDB by the WSM will generate an ATD pulse and valid data will be presented on output pads of the device after an access time. When the device enters the power-down mode, the ATD content addressable memory ("CAM") is powered-down to system power ("VCC") and all internal addresses are forced high. When the device comes out of the power-down mode, the DATDB signal toggles from high (logical one) to low (logical zero). This ensures that an ATD pulse is generated even if the addresses are not toggled.
摘要翻译：确保在写/擦除步骤之后，在发出擦除挂起命令或器件到来之后，具有写状态机（“WSM”）和地址转换检测（“ATD”）的闪存器件提供正确数据的电路超出掉电模式。无论何时WSM控制设备，ATD电路都被禁用。当WSM放弃对读取路径的控制时，通过取消禁止ATD条（“DATDB”）信号使其能够启用ATD。与DATDB信号一起使用作为芯片使能条（“CEB”）输入的逻辑反转的内部信号以产生ATD脉冲。因此，如果用户在进入擦除挂起模式时CEB被置为无效时在地址引脚上呈现有效地址，则通过WSM取消DATDB将产生ATD脉冲，并且有效数据将在器件的输出焊盘上呈现。访问时间。当设备进入掉电模式时，ATD内容可寻址存储器（“CAM”）掉电到系统电源（“VCC”），所有内部地址都被强制为高电平。当器件退出掉电模式时，DATDB信号从高（逻辑1）切换到低（逻辑0）。这确保即使地址不被切换也产生ATD脉冲。

7. 发明授权

US5289412A High-speed bias-stabilized current-mirror referencing circuit for non-volatile memories 失效
标题翻译：用于非易失性存储器的高速偏置稳压电流镜参考电路
公开(公告)号：US5289412A
公开(公告)日：1994-02-22
申请号：US901395
申请日：1992-06-19
申请人： Kevin W. Frary , Sachidanandan Sambandan
发明人： Kevin W. Frary , Sachidanandan Sambandan
IPC分类号： G11C16/28 , G11C7/00
CPC分类号： G11C16/28
摘要： A circuit for providing reference voltages to be used by sense amplifiers of output circuitry of an integrated circuit memory array to allow the sense amplifiers to ascertain the values stored by memory cells of the array. The circuit includes a first branch which has transistor circuitry for establishing a reference current, a second branch of the circuit including a first transistor device and apparatus for mirroring the reference current through the first transistor device, and a plurality of output branches each connected to a sense amplifier to provide a reference voltage to be used by the sense amplifier. Each of the output branches includes a second transistor device with characteristics essentially identical to the characteristics of the first transistor device. Apparatus is included in the output branches for providing voltages at all terminals of the second transistor devices equal to the voltages at all terminals of the first transistor device so that the reference current through each of the second transistor devices is forced to be identical to that through the first transistor device. The second branch is replicated to increase current available and circuit speed.
摘要翻译：一种用于提供由集成电路存储器阵列的输出电路的读出放大器使用的参考电压的电路，以允许读出放大器确定阵列的存储单元所存储的值。该电路包括具有用于建立参考电流的晶体管电路的第一分支，该电路的第二分支包括第一晶体管器件和用于镜像通过第一晶体管器件的参考电流的装置，以及多个输出分支，每个连接到读出放大器，以提供由读出放大器使用的参考电压。每个输出分支包括具有与第一晶体管器件的特性基本相同的特性的第二晶体管器件。装置包括在输出分支中，用于在第二晶体管器件的所有端子处提供等于第一晶体管器件的所有端子处的电压的电压，使得通过每个第二晶体管器件的参考电流被迫与通过第一晶体管器件。第二个分支被复制以增加电流可用和电路速度。

8. 发明授权

US5262990A Memory device having selectable number of output pins 失效
标题翻译：存储器件具有可选择的输出引脚数
公开(公告)号：US5262990A
公开(公告)日：1993-11-16
申请号：US729050
申请日：1991-07-12
申请人： Duane F. Mills , Jahanshir J. Javanifard , Rodney R. Rozman , Kevin W. Frary , Sherif R. B. Sweha
发明人： Duane F. Mills , Jahanshir J. Javanifard , Rodney R. Rozman , Kevin W. Frary , Sherif R. B. Sweha
IPC分类号： G11C7/00 , G11C7/10 , G11C8/12 , G06F13/00
CPC分类号： G11C8/12 , G11C7/00 , G11C7/1006
摘要： A memory device includes a memory array and a plurality of output pins. A control input is provided for receiving a control signal. The control signal can be in a first voltage state and a second voltage state. When the control signal is in the first voltage state, the memory device is in a first output mode. When the control signal is in the second voltage state, the memory device is in a second output mode. Circuitry is provided for selectively coupling the plurality of output pins to the memory array. An output mode select logic is coupled to receive the control signal for selecting the first output mode and the second output mode for the memory device. When the memory device is in the first output mode, the output mode select logic controls the circuitry to couple all of the plurality of output pins to the memory array. When the memory device is in the second output mode, the output mode select logic controls the circuitry to couple a portion of the plurality of output pins to the memory array. A method of controlling the memory device to switch between the first output mode and the second output mode is also described.
摘要翻译：存储器件包括存储器阵列和多个输出引脚。提供控制输入用于接收控制信号。控制信号可以处于第一电压状态和第二电压状态。当控制信号处于第一电压状态时，存储器件处于第一输出模式。当控制信号处于第二电压状态时，存储器件处于第二输出模式。提供电路用于选择性地将多个输出引脚耦合到存储器阵列。输出模式选择逻辑被耦合以接收用于选择存储器件的第一输出模式和第二输出模式的控制信号。当存储器件处于第一输出模式时，输出模式选择逻辑控制电路将所有多个输出引脚耦合到存储器阵列。当存储器件处于第二输出模式时，输出模式选择逻辑控制电路将多个输出引脚的一部分耦合到存储器阵列。还描述了一种控制存储器件在第一输出模式和第二输出模式之间切换的方法。

9. 发明授权

US5245574A Apparatus for increasing the speed of operation of non-volatile memory arrays 失效
标题翻译：用于提高非易失性存储器阵列的操作速度的装置
公开(公告)号：US5245574A
公开(公告)日：1993-09-14
申请号：US812631
申请日：1991-12-23
申请人： Kevin W. Frary , George Canepa , Sherif Sweha
发明人： Kevin W. Frary , George Canepa , Sherif Sweha
IPC分类号： G11C7/12 , G11C16/28
CPC分类号： G11C7/12 , G11C16/28
摘要： In a memory array having a plurality of bitlines each connected to a plurality of memory devices having a state in which current is transferred by the memory device and a state in which current is not transferred by the device, a column select device for activating each bitline, a plurality of wordlines for activating individual memory devices joined to each bitline, apparatus for providing constant current in the conducting state of a memory device connected to a bitline, a device connecting a source voltage to a plurality of bitlines, and a reference bitline for providing an output reference signal, the improvement including apparatus for providing a source of current in addition to current through the device connecting a source voltage to a plurality of bitlines in order to charge any capacitance of a selected bitline when that bitline is selected whereby switching between memory devices joined to different bitlines is accelerated.
摘要翻译：在具有多个位线的存储器阵列中，每个位线连接到具有由存储器件传送电流的状态的多个存储器件以及该器件不传送电流的状态;列选择器件，用于激活每个位线，用于激活连接到每个位线的各个存储器件的多个字线，用于在连接到位线的存储器件的导通状态下提供恒定电流的设备，将源极电压连接到多个位线的器件以及用于提供输出参考信号，该改进包括用于提供电流源的装置，除了通过将源电压连接到多个位线的装置之外还提供电流源，以便当选择该位线时对所选位线的任何电容进行充电，从而在选择位线之间切换连接到不同位线的存储器件被加速。

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