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1. 发明授权

US08914648B1 Stateless and stateful implementations of faithful execution 有权
标题翻译：无状态和有状态地执行忠实执行
公开(公告)号：US08914648B1
公开(公告)日：2014-12-16
申请号：US12542072
申请日：2009-08-17
申请人： Lyndon G. Pierson , Edward L. Witzke , Thomas D. Tarman , Perry J. Robertson , John M. Eldridge , Philip L. Campbell
发明人： Lyndon G. Pierson , Edward L. Witzke , Thomas D. Tarman , Perry J. Robertson , John M. Eldridge , Philip L. Campbell
IPC分类号： G06F11/30
CPC分类号： G06F21/52 , G06F21/64 , H04L9/0656 , H04L9/32
摘要： A faithful execution system includes system memory, a target processor, and protection engine. The system memory stores a ciphertext including value fields and integrity fields. The value fields each include an encrypted executable instruction and the integrity fields each include an encrypted integrity value for determining whether a corresponding one of the value fields has been modified. The target processor executes plaintext instructions decoded from the ciphertext while the protection engine is coupled between the system memory and the target processor. The protection engine includes logic to retrieve the ciphertext from the system memory, decrypt the value fields into the plaintext instructions, perform an integrity check based on the integrity fields to determine whether any of the corresponding value fields have been modified, and provide the plaintext instructions to the target processor for execution.
摘要翻译：忠实的执行系统包括系统内存，目标处理器和保护引擎。系统存储器存储包括值字段和完整性字段的密文。值字段各自包括加密的可执行指令，并且完整性字段各自包括加密的完整性值，用于确定值字段中对应的一个值是否已被修改。当保护引擎耦合在系统存储器和目标处理器之间时，目标处理器执行从密文解码的明文指令。保护引擎包括从系统存储器检索密文的逻辑，将值字段解密为明文指令，根据完整性字段执行完整性检查，以确定是否已对任何相应的值字段进行了修改，并提供明文指令到目标处理器执行。

2. 发明授权

US07257093B1 Localized radio frequency communication using asynchronous transfer mode protocol 失效
标题翻译：使用异步传输模式协议的本地化射频通信
公开(公告)号：US07257093B1
公开(公告)日：2007-08-14
申请号：US09975271
申请日：2001-10-10
申请人： Edward L. Witzke , Perry J. Robertson , Lyndon G. Pierson
发明人： Edward L. Witzke , Perry J. Robertson , Lyndon G. Pierson
IPC分类号： H04B7/00
CPC分类号： G06F13/4045 , H04L12/5601 , H04L2012/5607 , H05K1/14 , H05K2201/10098
摘要： A localized wireless communication system for communication between a plurality of circuit boards, and between electronic components on the circuit boards. Transceivers are located on each circuit board and electronic component. The transceivers communicate with one another over spread spectrum radio frequencies. An asynchronous transfer mode protocol controls communication flow with asynchronous transfer mode switches located on the circuit boards.
摘要翻译：一种本地化的无线通信系统，用于在多个电路板之间以及电路板上的电子部件之间进行通信。收发器位于每个电路板和电子元件上。收发器通过扩频无线电频率彼此通信。异步传输模式协议通过位于电路板上的异步传输模式开关控制通信流。

3. 发明授权

US08125357B1 Deflate decompressor 有权
标题翻译：放气解压器
公开(公告)号：US08125357B1
公开(公告)日：2012-02-28
申请号：US12729816
申请日：2010-03-23
申请人： Jason R. Hamlet , Perry J. Robertson , Lyndon G. Pierson , Ronald R. Olsberg
发明人： Jason R. Hamlet , Perry J. Robertson , Lyndon G. Pierson , Ronald R. Olsberg
IPC分类号： H03M7/34
CPC分类号： H03M7/4081 , H03M7/3086 , H03M7/4043 , H03M7/607
摘要： A deflate decompressor includes at least one decompressor unit, a memory access controller, a feedback path, and an output buffer unit. The memory access controller is coupled to the decompressor unit via a data path and includes a data buffer to receive the data stream and temporarily buffer a first portion the data stream. The memory access controller transfers fixed length data units of the data stream from the data buffer to the decompressor unit with reference to a memory pointer pointing into the memory buffer. The feedback path couples the decompressor unit to the memory access controller to feed back decrement values to the memory access controller for updating the memory pointer. The decrement values each indicate a number of bits unused by the decompressor unit when decoding the fixed length data units. The output buffer unit buffers a second portion of the data stream after decompression.
摘要翻译：放气解压缩器包括至少一个解压缩器单元，存储器存取控制器，反馈路径和输出缓冲器单元。存储器访问控制器经由数据路径耦合到解压缩器单元，并且包括数据缓冲器以接收数据流并临时缓冲数据流的第一部分。存储器访问控制器参考指向存储器缓冲器的存储器指针，将数据流的固定长度数据单元从数据缓冲器传送到解压缩器单元。反馈路径将解压缩器单元耦合到存储器访问控制器，以将反馈值反馈到存储器访问控制器以更新存储器指针。递减值分别表示解码固定长度数据单元时解压缩单元未使用的位数。输出缓冲器单元在解压缩之后缓冲数据流的第二部分。

4. 发明授权

US08514855B1 Extensible packet processing architecture 有权
标题翻译：可扩展包处理架构
公开(公告)号：US08514855B1
公开(公告)日：2013-08-20
申请号：US12773120
申请日：2010-05-04
申请人： Perry J. Robertson , Jason R. Hamlet , Lyndon G. Pierson , Ronald R. Olsberg , Guy D. Chun
发明人： Perry J. Robertson , Jason R. Hamlet , Lyndon G. Pierson , Ronald R. Olsberg , Guy D. Chun
IPC分类号： H04L12/28
CPC分类号： H04L49/3063
摘要： A technique for distributed packet processing includes sequentially passing packets associated with packet flows between a plurality of processing engines along a flow through data bus linking the plurality of processing engines in series. At least one packet within a given packet flow is marked by a given processing engine to signify by the given processing engine to the other processing engines that the given processing engine has claimed the given packet flow for processing. A processing function is applied to each of the packet flows within the processing engines and the processed packets are output on a time-shared, arbitered data bus coupled to the plurality of processing engines.
摘要翻译：一种用于分布式分组处理的技术包括在多个处理引擎之间沿着连接多个处理引擎串联的数据总线的流程顺序地传递与分组流相关联的分组。给定分组流中的至少一个分组由给定的处理引擎标记，由给定的处理引擎指示给定处理引擎已经要求给定的分组流进行处理的其他处理引擎。处理功能被应用于处理引擎内的每个分组流，并且处理的分组在耦合到多个处理引擎的时间共享的仲裁数据总线上输出。

5. 发明授权

US06323679B1 Flexible programmable logic module 有权
标题翻译：灵活的可编程逻辑模块
公开(公告)号：US06323679B1
公开(公告)日：2001-11-27
申请号：US09439104
申请日：1999-11-12
申请人： Perry J. Robertson , Robert L. Hutchinson , Lyndon G. Pierson
发明人： Perry J. Robertson , Robert L. Hutchinson , Lyndon G. Pierson
IPC分类号： H03K19177
CPC分类号： G06F15/7867 , H05K1/0286 , H05K1/181
摘要： The circuit module of this invention is a VME board containing a plurality of programmable logic devices (PLDs), a controlled impedance clock tree, and interconnecting buses. The PLDs are arranged to permit systolic processing of a problem by offering wide data buses and a plurality of processing nodes. The board contains a clock reference and clock distribution tree that can drive each of the PLDs with two critically timed clock references. External clock references can be used to drive additional circuit modules all operating from the same synchronous clock reference.
摘要翻译：本发明的电路模块是包含多个可编程逻辑器件（PLD），受控阻抗时钟树和互连总线的VME板。 PLD被设置为通过提供宽数据总线和多个处理节点来允许对问题的收缩处理。该板包含时钟参考和时钟分配树，可以使用两个临时定时的时钟参考来驱动每个PLD。外部时钟参考可用于驱动所有工作在相同同步时钟参考的附加电路模块。

6. 发明授权

US06209077B1 General purpose programmable accelerator board 有权
标题翻译：通用可编程加速板
公开(公告)号：US06209077B1
公开(公告)日：2001-03-27
申请号：US09217099
申请日：1998-12-21
申请人： Perry J. Robertson , Edward L. Witzke
发明人： Perry J. Robertson , Edward L. Witzke
IPC分类号： G06F928
CPC分类号： G06F15/7867 , G06F9/3879
摘要： A general purpose accelerator board and acceleration method comprising use of: one or more programmable logic devices; a plurality of memory blocks; bus interface for communicating data between the memory blocks and devices external to the board; and dynamic programming capabilities for providing logic to the programmable logic device to be executed on data in the memory blocks.
摘要翻译：一种通用加速器板和加速方法，包括使用：一个或多个可编程逻辑器件; 多个存储块; 总线接口，用于在存储器块和板外部的设备之间传送数据; 以及用于向可编程逻辑器件提供对存储器块中的数据执行逻辑的动态编程能力。

7. 发明授权

US4885480A Source follower field-effect logic gate (SFFL) suitable for III-V technologies 失效
标题翻译：源极跟随器场效应逻辑门（SFFL）适用于III-V技术
公开(公告)号：US4885480A
公开(公告)日：1989-12-05
申请号：US235862
申请日：1988-08-23
申请人： Aziz I. Faris , Perry J. Robertson
发明人： Aziz I. Faris , Perry J. Robertson
IPC分类号： H03K19/0952
CPC分类号： H03K19/0952
摘要： A high speed logic circuit having extremely low propagation delays, suitable for implementation in III-V technology. A logic stage provides the desired logic function by combining a predetermined number of input FETs. The drains of the input FETs couple to a pull-up FET and form a first intermediate output of the logic stage. The sources of the input FETs couple to a pull-down FET and form a second intermediate output of the first stage. A second stage, or buffer stage, responding to the intermediate outputs of the first stage, provides sufficient drive to an output terminal of the logic gate to drive multiple loads (gates) coupled thereto. The second stage includes a pull-down FET responsive to the second intermediate output of the first stage. The second stage also includes alternative combinations of FETs and diodes to pull-up the voltage on the output terminal of the logic gate.

8. 发明授权

US5479033A Complementary junction heterostructure field-effect transistor 失效
标题翻译：互补结异构结场场效应晶体管
公开(公告)号：US5479033A
公开(公告)日：1995-12-26
申请号：US250088
申请日：1994-05-27
申请人： Albert G. Baca , Timothy J. Drummond , Perry J. Robertson , Thomas E. Zipperian
发明人： Albert G. Baca , Timothy J. Drummond , Perry J. Robertson , Thomas E. Zipperian
IPC分类号： H01L27/06 , H01L29/80 , H01L31/0376 , H01L31/072
CPC分类号： H01L27/0605 , H01L29/802
摘要： A complimentary pair of compound semiconductor junction heterostructure field-effect transistors and a method for their manufacture are disclosed. The p-channel junction heterostructure field-effect transistor uses a strained layer to split the degeneracy of the valence band for a greatly improved hole mobility and speed. The n-channel device is formed by a compatible process after removing the strained layer. In this manner, both types of transistors may be independently optimized. Ion implantation is used to form the transistor active and isolation regions for both types of complimentary devices. The invention has uses for the development of low power, high-speed digital integrated circuits.
摘要翻译：公开了一对互补的化合物半导体结异质结场场效应晶体管及其制造方法。 p沟道结异质结场场效应晶体管使用应变层来分离价带的简并性，大大提高了空穴迁移率和速度。去除应变层后，n通道器件由兼容的工艺形成。以这种方式，可以独立优化两种类型的晶体管。离子注入用于形成两种类型的互补器件的晶体管有源和隔离区域。本发明用于开发低功率，高速数字集成电路。

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