专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US07581054B2 Data processing system 有权
标题翻译：数据处理系统
公开(公告)号：US07581054B2
公开(公告)日：2009-08-25
申请号：US11779189
申请日：2007-07-17
申请人： Kesami Hagiwara , Takeshi Kataoka , Hisakazu Sato , Shunichi Iwata , Yoshikazu Kiyoshige , Akihiko Tomita
发明人： Kesami Hagiwara , Takeshi Kataoka , Hisakazu Sato , Shunichi Iwata , Yoshikazu Kiyoshige , Akihiko Tomita
IPC分类号： G06F13/14 , G06F15/167
CPC分类号： G06F13/364
摘要： In a multiprocessor, one of two local memories can be accessed at a high speed by one of the two processors and also accessed by the other processor. In a multiprocessor, first and second local memories are coupled to first and second processors via first and second local buses. First and second bus bridges are coupled to a system bus and the first and second local buses. First and second bus interface units are coupled to the system bus and the first and second local memories. A high-speed access is made from the first processor to the first local memory via the first local bus. The first local memory is also accessed from the first processor via the first local bus, the first bus bridge, the system bus, and the first and third ports of the second bus interface unit and from the second processor via the second local bus, the second bus bridge, the system bus, and the second and third ports of the first bus interface unit. A high-speed access is made from the second processor to the second local memory via the second local bus. The second local memory is also accessed from the second processor via the second local bus, the second bus bridge, the system bus, and the second and third ports of the first bus interface unit and from the first processor via the first local bus, the first bus bridge, the system bus, and the first and third ports of the second bus interface unit.
摘要翻译：在多处理器中，两个本地存储器之一可以通过两个处理器之一高速访问，并且还可以由另一个处理器访问。在多处理器中，第一和第二本地存储器经由第一和第二本地总线耦合到第一和第二处理器。第一和第二总线桥耦合到系统总线和第一和第二本地总线。第一和第二总线接口单元耦合到系统总线和第一和第二本地存储器。通过第一本地总线从第一处理器到第一本地存储器进行高速访问。第一本地存储器还通过第一局部总线，第一总线桥，系统总线以及第二总线接口单元的第一和第三端口以及经由第二本地总线从第二处理器访问第一本地存储器，第二总线桥，系统总线，以及第一总线接口单元的第二和第三端口。通过第二本地总线从第二处理器到第二本地存储器进行高速访问。第二本地存储器还通过第二本地总线，第二总线桥，系统总线以及第一总线接口单元的第二和第三端口以及经由第一本地总线从第一处理器访问第二本地存储器，第一总线桥，系统总线，以及第二总线接口单元的第一和第三端口。

2. 发明申请

US20080022030A1 DATA PROCESSING SYSTEM 有权
标题翻译：数据处理系统
公开(公告)号：US20080022030A1
公开(公告)日：2008-01-24
申请号：US11779189
申请日：2007-07-17
申请人： Kesami Hagiwara , Takeshi Kataoka , Hisakazu Sato , Shunichi Iwata , Yoshikazu Kiyoshige , Akihiko Tomita
发明人： Kesami Hagiwara , Takeshi Kataoka , Hisakazu Sato , Shunichi Iwata , Yoshikazu Kiyoshige , Akihiko Tomita
IPC分类号： G06F13/36
CPC分类号： G06F13/364
摘要： In a multiprocessor, one of two local memories can be accessed at a high speed by one of the two processors and also accessed by the other processor. In a multiprocessor, first and second local memories are coupled to first and second processors via first and second local buses. First and second bus bridges are coupled to a system bus and the first and second local buses. First and second bus interface units are coupled to the system bus and the first and second local memories. A high-speed access is made from the first processor to the first local memory via the first local bus. The first local memory is also accessed from the first processor via the first local bus, the first bus bridge, the system bus, and the first and third ports of the second bus interface unit and from the second processor via the second local bus, the second bus bridge, the system bus, and the second and third ports of the first bus interface unit. A high-speed access is made from the second processor to the second local memory via the second local bus. The second local memory is also accessed from the second processor via the second local bus, the second bus bridge, the system bus, and the second and third ports of the first bus interface unit and from the first processor via the first local bus, the first bus bridge, the system bus, and the first and third ports of the second bus interface unit.
摘要翻译：在多处理器中，两个本地存储器之一可以通过两个处理器之一高速访问，并且还可以由另一个处理器访问。在多处理器中，第一和第二本地存储器经由第一和第二本地总线耦合到第一和第二处理器。第一和第二总线桥耦合到系统总线和第一和第二本地总线。第一和第二总线接口单元耦合到系统总线和第一和第二本地存储器。通过第一本地总线从第一处理器到第一本地存储器进行高速访问。第一本地存储器还通过第一局部总线，第一总线桥，系统总线以及第二总线接口单元的第一和第三端口以及经由第二本地总线从第二处理器访问第一本地存储器，第二总线桥，系统总线，以及第一总线接口单元的第二和第三端口。通过第二本地总线从第二处理器到第二本地存储器进行高速访问。第二本地存储器还通过第二本地总线，第二总线桥，系统总线以及第一总线接口单元的第二和第三端口以及经由第一本地总线从第一处理器访问第二本地存储器，第一总线桥，系统总线，以及第二总线接口单元的第一和第三端口。

3. 发明申请

US20080222336A1 DATA PROCESSING SYSTEM 审中-公开
标题翻译：数据处理系统
公开(公告)号：US20080222336A1
公开(公告)日：2008-09-11
申请号：US12014069
申请日：2008-01-14
申请人： Yoshikazu KIYOSHIGE , Shunichi Iwata , Kesami Hagiwara , Akihiko Tomita
发明人： Yoshikazu KIYOSHIGE , Shunichi Iwata , Kesami Hagiwara , Akihiko Tomita
IPC分类号： G06F9/30 , G06F13/14 , G06F9/302
CPC分类号： G06F9/3836 , G06F9/30101 , G06F9/3851 , G06F9/3877 , G06F9/3885 , G06F9/3891
摘要： To allow to use arithmetic circuits of sharable resources by priority with a simple procedure. In a data processing system including central processing units and a plurality of arithmetic circuits, wherein the central processing units are able to supply a command to one arithmetic circuit based on one fetched instruction and supply a command to other arithmetic circuit based on other fetched instruction, a memory circuit is provided which is used to store first information indicating which arithmetic circuit is executing a command, and second information indicating which central processing unit has reserved the arithmetic circuit for execution of the next command. When the arithmetic circuit is already executing a command, reservation of the arithmetic circuit for execution of the next command using the second information of the memory circuit, makes it possible, after the execution, to assign operation commands fast to the arithmetic circuits and cause them to execute the commands.
摘要翻译：允许以简单的过程优先使用可共享资源的算术电路。在包括中央处理单元和多个算术电路的数据处理系统中，其中中央处理单元能够基于一个获取的指令向一个算术电路提供命令，并且基于其他获取的指令向其他算术电路提供命令，提供了一种存储电路，用于存储指示哪个运算电路正在执行命令的第一信息，以及指示哪个中央处理单元预留了用于执行下一个命令的运算电路的第二信息。当算术电路已经在执行命令时，使用存储电路的第二信息来预约用于执行下一个命令的运算电路，使执行后能够将运算命令快速地分配给运算电路并使它们执行命令。

4. 发明申请

US20070124559A1 Microcontroller and RAM 失效
标题翻译：微控制器和RAM
公开(公告)号：US20070124559A1
公开(公告)日：2007-05-31
申请号：US11604806
申请日：2006-11-28
申请人： Hiromichi Yamada , Teppai Hirotsu , Teruaki Sakata , Takeshi Kataoka , Shunichi Iwata
发明人： Hiromichi Yamada , Teppai Hirotsu , Teruaki Sakata , Takeshi Kataoka , Shunichi Iwata
IPC分类号： G06F12/00
CPC分类号： G06F11/167 , G06F11/08 , G06F11/183
摘要： A microcontroller in which an increase in hardware is suppressed and data correction capability for software error of RAM can be improved is provided. A microcontroller which performs processing according to a program includes a CPU and a RAM for storing data processed by the CPU, wherein multiplexed regions are defined in the RAM, and when these regions are accessed, an access to an address outputted by the CPU and a copy access to an address obtained by adding or subtracting a certain value to or from the address outputted by the CPU are performed. By this means, the same data can be stored in a plurality of regions and the reliability can be improved.
摘要翻译：提供了一种微控制器，其中硬件的增加被抑制，并且可以提高对RAM的软件错误的数据校正能力。执行根据程序的处理的微控制器包括CPU和RAM，用于存储由CPU处理的数据，其中在RAM中定义复用区域，并且当这些区域被访问时，访问由CPU输出的地址和执行通过向CPU输出的地址添加或减去某个值而获得的地址的复制访问。通过这种方式，可以将相同的数据存储在多个区域中，并且可以提高可靠性。

5. 发明授权

US07752527B2 Microcontroller and RAM 失效
标题翻译：微控制器和RAM
公开(公告)号：US07752527B2
公开(公告)日：2010-07-06
申请号：US11604806
申请日：2006-11-28
申请人： Hiromichi Yamada , Teppei Hirotsu , Teruaki Sakata , Takeshi Kataoka , Shunichi Iwata
发明人： Hiromichi Yamada , Teppei Hirotsu , Teruaki Sakata , Takeshi Kataoka , Shunichi Iwata
IPC分类号： G11C29/00
CPC分类号： G06F11/167 , G06F11/08 , G06F11/183
摘要： A microcontroller in which an increase in hardware is suppressed and data correction capability for software error of RAM can be improved is provided. A microcontroller which performs processing according to a program includes a CPU and a RAM for storing data processed by the CPU, wherein multiplexed regions are defined in the RAM, and when these regions are accessed, an access to an address outputted by the CPU and a copy access to an address obtained by adding or subtracting a certain value to or from the address outputted by the CPU are performed. By this means, the same data can be stored in a plurality of regions and the reliability can be improved.
摘要翻译：提供了一种微控制器，其中硬件的增加被抑制，并且可以提高对RAM的软件错误的数据校正能力。执行根据程序的处理的微控制器包括CPU和RAM，用于存储由CPU处理的数据，其中在RAM中定义复用区域，并且当这些区域被访问时，访问由CPU输出的地址和执行通过向CPU输出的地址添加或减去某个值而获得的地址的复制访问。通过这种方式，可以将相同的数据存储在多个区域中，并且可以提高可靠性。

6. 发明授权

US5717946A Data processor 失效
标题翻译：数据处理器
公开(公告)号：US5717946A
公开(公告)日：1998-02-10
申请号：US783531
申请日：1997-01-14
申请人： Mitsugu Satou , Toyohiko Yoshida , Shunichi Iwata
发明人： Mitsugu Satou , Toyohiko Yoshida , Shunichi Iwata
IPC分类号： G06F9/30 , G06F9/34 , G06F9/38 , G06F13/42 , G06F13/00
CPC分类号： G06F9/30018 , G06F13/4243 , G06F9/30032 , G06F9/30036 , G06F9/30043 , G06F9/30054 , G06F9/30058 , G06F9/30076 , G06F9/30145 , G06F9/30167 , G06F9/321 , G06F9/324 , G06F9/34 , G06F9/345 , G06F9/3804 , G06F9/3806 , G06F9/3822 , G06F9/3853 , G06F9/3867 , G06F9/3885
摘要： A data processor having a string operation instruction and a bit map operation instruction, and comprises a bus interface unit 157 which inputs/outputs data by the burst transfer function, and an integer operation unit 155 building-in a main ALU and a sub-ALU, wherein data is repeatedly transferred to/from an external memory via a data bus 102 in unit greater than a width of the data bus 102. Further, is can be accessed in a high speed by the block transfer in the burst mode to efficiently execute the above instructions, therefore the data string and bit map data can be executed quickly even when a low-cost slow memory system is connected thereto.
摘要翻译：具有字符串操作指令和位图操作指令的数据处理器，并且包括通过突发传送功能输入/输出数据的总线接口单元157和建立在主ALU和子ALU中的整数运算单元155 其中数据经由数据总线102以大于数据总线102的宽度的单位被重复地传送到外部存储器。此外，可以通过突发模式下的块传输以高速访问以有效执行因此即使在连接有低成本的慢速存储器系统的情况下，也可以快速地执行数据串和位图数据。

7. 发明授权

US5471620A Data processor with means for separately receiving and processing different types of interrupts 失效
标题翻译：具有用于单独接收和处理不同类型中断的装置的数据处理器
公开(公告)号：US5471620A
公开(公告)日：1995-11-28
申请号：US257844
申请日：1994-06-10
申请人： Toru Shimizu , Shunichi Iwata
发明人： Toru Shimizu , Shunichi Iwata
IPC分类号： G06F9/48 , G06F13/26 , G06F13/24 , G06F9/46
CPC分类号： G06F9/4812 , G06F13/26
摘要： A data processor which is provided with a flag in a Processor Status Word (PSW) 116 for storing prohibiting/enabling status for receiving all of the interrupt requests, and in which the instruction execution control unit 114 controls so that the flag becomes in the enabling status when an interrupt request having a priority level is received and the flag becomes in the prohibiting status when an interrupt request having no priority level is received. Hence, for interrupt requests having priority levels, an interrupt request of high priority level can be received immediately without via the interrupt prohibiting status. For interrupt requests having priority levels, it becomes possible to receive an interrupt request of higher priority level without via the interrupt prohibiting status. For interrupt requests having no priority level such as for debugger and the like, it becomes unnecessary to perform a multi-interrupt processing.
摘要翻译：在处理器状态字（PSW）116中设置有用于存储用于接收所有中断请求的禁止/使能状态的数据处理器，并且其中指令执行控制单元114进行控制，使得该标志变为使能当接收到具有优先级的中断请求时，当接收到具有优先级的中断请求时，该状态变为处于禁止状态。因此，对于具有优先级的中断请求，可以立即接收到高优先级的中断请求而不经过中断禁止状态。对于具有优先级的中断请求，可以通过中断禁止状态来接收更高优先级的中断请求。对于没有诸如调试器等优先级的中断请求，不需要执行多中断处理。

8. 发明授权

US06463520B1 Processor for executing instruction codes of two different lengths and device for inputting the instruction codes 失效
标题翻译：用于执行两种不同长度的指令代码的处理器和用于输入指令代码的装置
公开(公告)号：US06463520B1
公开(公告)日：2002-10-08
申请号：US08811005
申请日：1997-03-04
申请人： Sugako Otani , Shunichi Iwata
发明人： Sugako Otani , Shunichi Iwata
IPC分类号： G06E1500
CPC分类号： G06F9/30145 , G06F9/3005 , G06F9/30149 , G06F9/30152 , G06F9/3016 , G06F9/30167 , G06F9/30181 , G06F9/322
摘要： Exemplary embodiments of the present invention are directed toward a technique which facilitates the process instruction codes in processor. According to the present invention, a memory device is provided which comprises a plurality of 2N-bit word boundaries, where N is greater than or equal to one. The processor of the present invention executes instruction codes of a 2N-bit length and a N-bit length. The instruction codes are stored in the memory device is such a way that the 2-N bit word boundaries contains either a single 2N-bit instruction code or two N-bit instruction codes. The most significant bit of each instruction code serves as a instruction format identifier which controls the execution (or decoding) sequence of the instruction codes. As a result, only two transfer paths from an instruction fetch portion to an instruction decode portion of the processor are necessary thereby reducing the hardware requirement of the processor and increasing system throughput.
摘要翻译：本发明的示例性实施例涉及促进处理器中的处理指令代码的技术。根据本发明，提供一种包括多个2N位字边界的存储器件，其中N大于或等于1。本发明的处理器执行2N位长度和N位长度的指令代码。指令码存储在存储器件中，使得2-N位字边界包含单个2N位指令代码或两个N位指令代码。每个指令代码的最高有效位用作控制指令代码的执行（或解码）序列的指令格式标识符。结果，仅需要从处理器的指令提取部分到指令解码部分的两个传送路径，从而减少处理器的硬件需求并提高系统吞吐量。

9. 发明授权

US06209079B1 Processor for executing instruction codes of two different lengths and device for inputting the instruction codes 有权
标题翻译：用于执行两种不同长度的指令代码的处理器和用于输入指令代码的装置
公开(公告)号：US06209079B1
公开(公告)日：2001-03-27
申请号：US09562643
申请日：2000-05-01
申请人： Sugako Otani , Shunichi Iwata
发明人： Sugako Otani , Shunichi Iwata
IPC分类号： G06F930
CPC分类号： G06F9/30145 , G06F9/3005 , G06F9/30149 , G06F9/30152 , G06F9/3016 , G06F9/30167 , G06F9/30181 , G06F9/322
摘要： For a processor having instruction codes of two instruction lengths (16 bits and 32 bits), methods of locating the instruction codes are limited to two types: (1) two 16-bit instruction codes are stored within 32-bit word boundaries, and (2) a single 32-bit instruction code is stored intactly within the 32-bit word boundaries. A branch destination address is specified only on the 32-bit word boundary. The MSB of each instruction code serves as a 1-bit instruction length identifier for controlling the execution sequence of the instruction codes. This provides two transfer paths from an instruction fetch portion to an instruction decode portion within the processor, achieving reduction in code side and in the amount of hardware and, accordingly, the increase in operating speed.
摘要翻译：对于具有两个指令长度（16位和32位）的指令代码的处理器，定位指令代码的方法被限制为两种类型：（1）两个16位指令代码存储在32位字边界内，并且（ 2）单个32位指令代码完整地存储在32位字边界内。分支目的地址仅在32位字边界上指定。每个指令代码的MSB用作1位指令长度标识符，用于控制指令代码的执行顺序。这提供了从处理器内的指令获取部分到指令解码部分的两个传送路径，实现了代码侧的减少和硬件的数量以及相应的操作速度的提高。

10. 发明授权

US5872903A Integrated circuit device with a memory that preserves its content independently of a synchronizing signal when given a self-control request 失效
标题翻译：具有存储器的集成电路器件，当给定自我控制请求时，该存储器可独立于同步信号保持其内容
公开(公告)号：US5872903A
公开(公告)日：1999-02-16
申请号：US805350
申请日：1997-02-24
申请人： Shunichi Iwata , Mitsugu Satou
发明人： Shunichi Iwata , Mitsugu Satou
IPC分类号： G06F1/32 , G05B15/02 , G05B19/02 , G05B19/05 , G06F1/04 , G06F1/26 , G06F12/08 , G06F15/78 , G06F15/16
CPC分类号： G06F12/0891 , G06F1/26 , Y02B60/1225
摘要： When a CPU (1) writes "10" into a register (RG) provided in a controller (5), an AND gate (10) receives a CPU clock mask signal (CMS1) having the logic of "0" by one of its input terminals and accordingly cuts off the supply of a clock signal CLK to the CPU (1). Then, the CPU (1) is suspended, thereby reducing power consumption of the CPU (1). To return out of this state, a user has only to input an interrupt request to the controller (5) through a terminal (T1). Receiving the request, the controller (5) outputs the CPU clock mask signal (CMS1) having the logic of "1" to one of the input terminals of the AND gate (10) so as to supply the CPU (1) with the clock signal (CLK) again. Upon restarting the supply of the clock signal (CLK), the CPU (1) starts an operation to implement the interrupt request. With this configuration, an integrated circuit device including a control circuit for controlling operations of a processing circuit and a memory circuit with excellent operability can be provided.
摘要翻译：当CPU（1）将“10”写入到控制器（5）中提供的寄存器（RG）中时，与门（10）通过其中的一个接收具有逻辑“0”的CPU时钟屏蔽信号（CMS1）输入端子，从而切断向CPU（1）提供时钟信号CLK。然后，CPU（1）暂停，从而降低CPU（1）的功耗。为了退出该状态，用户仅通过终端（T1）向控制器（5）输入中断请求。接收到该请求后，控制器（5）将具有逻辑“1”的CPU时钟屏蔽信号（CMS1）输出到与门（10）的输入端之一，以向CPU（1）提供时钟信号（CLK）。在重新启动时钟信号（CLK）的提供时，CPU（1）开始执行中断请求的操作。利用这种配置，可以提供一种集成电路装置，其包括用于控制处理电路的操作的控制电路和具有优异的可操作性的存储电路。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式