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1. 发明申请

US20100230729A1 PIXEL SENSOR CELL INCLUDING LIGHT SHIELD 有权
标题翻译：像素传感器细胞，包括光泽
公开(公告)号：US20100230729A1
公开(公告)日：2010-09-16
申请号：US12538194
申请日：2009-08-10
申请人： John Ellis-Monaghan , Jeffrey P. Gambino , Mark D. Jaffe , Richard J. Rassel
发明人： John Ellis-Monaghan , Jeffrey P. Gambino , Mark D. Jaffe , Richard J. Rassel
IPC分类号： H01L27/148 , H01L27/146 , H01L31/0216 , H01L21/30 , G06F17/50
CPC分类号： H01L27/14689 , H01L27/14609 , H01L27/14623 , H01L27/1464
摘要： CMOS image sensor pixel sensor cells, methods for fabricating the pixel sensor cells and design structures for fabricating the pixel sensor cells are designed to allow for back side illumination in global shutter mode by providing light shielding from back side illumination of at least one transistor within the pixel sensor cells. In a first particular generalized embodiment, a light shielding layer is located and formed interposed between a first semiconductor layer that includes a photoactive region and a second semiconductor layer that includes the at least a second transistor, or a floating diffusion, that is shielded by the light blocking layer. In a second generalized embodiment, a thin film transistor and a metal-insulator-metal capacitor are used in place of a floating diffusion, and located shielded in a dielectric isolated metallization stack over a carrier substrate
摘要翻译： CMOS图像传感器像素传感器单元，用于制造像素传感器单元的方法和用于制造像素传感器单元的设计结构被设计成允许在全局快门模式中进行背面照明，通过提供来自至少一个晶体管的背面照明的光屏蔽像素传感器单元。在第一特定广义实施例中，遮光层位于包括光活性区的第一半导体层和包括至少第二晶体管的第二半导体层之间并形成，或者浮置扩散部被屏蔽遮光层。在第二广义实施例中，使用薄膜晶体管和金属 - 绝缘体 - 金属电容器代替浮动扩散，并且被定位在载体衬底上的电介质隔离金属化堆叠中

2. 发明授权

US09543356B2 Pixel sensor cell including light shield 有权
标题翻译：像素传感器单元包括遮光罩
公开(公告)号：US09543356B2
公开(公告)日：2017-01-10
申请号：US12538194
申请日：2009-08-10
申请人： Jeffrey P. Gambino , Mark D. Jaffe , John Ellis-Monaghan , Richard Rassel
发明人： Jeffrey P. Gambino , Mark D. Jaffe , John Ellis-Monaghan , Richard Rassel
IPC分类号： H01L27/148 , H01L27/146
CPC分类号： H01L27/14689 , H01L27/14609 , H01L27/14623 , H01L27/1464
摘要： CMOS image sensor pixel sensor cells, methods for fabricating the pixel sensor cells and design structures for fabricating the pixel sensor cells are designed to allow for back side illumination in global shutter mode by providing light shielding from back side illumination of at least one transistor within the pixel sensor cells. In a first particular generalized embodiment, a light shielding layer is located and formed interposed between a first semiconductor layer that includes a photoactive region and a second semiconductor layer that includes the at least a second transistor, or a floating diffusion, that is shielded by the light blocking layer. In a second generalized embodiment, a thin film transistor and a metal-insulator-metal capacitor are used in place of a floating diffusion, and located shielded in a dielectric isolated metallization stack over a carrier substrate.
摘要翻译： CMOS图像传感器像素传感器单元，用于制造像素传感器单元的方法和用于制造像素传感器单元的设计结构被设计成允许在全局快门模式中进行背面照明，通过提供来自至少一个晶体管的背侧照明的光屏蔽像素传感器单元。在第一特定广义实施例中，遮光层位于包括光活性区的第一半导体层和包括至少第二晶体管的第二半导体层之间并形成，或者浮置扩散部被屏蔽遮光层。在第二广义实施例中，使用薄膜晶体管和金属 - 绝缘体 - 金属电容器来代替浮动扩散，并且被定位在载体衬底上的介电隔离金属化堆叠中。

3. 发明授权

US07459360B2 Method of forming pixel sensor cell having reduced pinning layer barrier potential 有权
标题翻译：形成具有降低的钉扎层势垒势垒的像素传感器单元的方法
公开(公告)号：US07459360B2
公开(公告)日：2008-12-02
申请号：US11681454
申请日：2007-03-02
申请人： James W. Adkisson , Andres Bryant , John Ellis-Monaghan , Jeffrey P. Gambino , Mark D. Jaffe , Jerome B. Lasky , Richard A. Phelps
发明人： James W. Adkisson , Andres Bryant , John Ellis-Monaghan , Jeffrey P. Gambino , Mark D. Jaffe , Jerome B. Lasky , Richard A. Phelps
IPC分类号： H01L21/8238
CPC分类号： H01L27/14689 , H01L27/14603 , H01L27/14609 , H01L31/0352
摘要： A method of forming a pixel sensor cell structure. The method of forming the pixel cell comprises forming a doped layer adjacent to a first side of a transfer gate structure for coupling a collection well region and a channel region. Potential barrier interference to charge transfer caused by a pinning layer is reduced.
摘要翻译：一种形成像素传感器单元结构的方法。形成像素单元的方法包括形成与传输栅极结构的第一侧相邻的掺杂层，用于耦合收集阱区和沟道区。减少了由钉扎层引起的对电荷转移的电势障碍干扰。

4. 发明授权

US07205591B2 Pixel sensor cell having reduced pinning layer barrier potential and method thereof 有权
标题翻译：具有降低的钉扎层势垒势的像素传感器单元及其方法
公开(公告)号：US07205591B2
公开(公告)日：2007-04-17
申请号：US10907570
申请日：2005-04-06
申请人： James W. Adkisson , Andres Bryant , John Ellis-Monaghan , Jeffrey P. Gambino , Mark D. Jaffe , Jerome B Lasky , Richard A. Phelps
发明人： James W. Adkisson , Andres Bryant , John Ellis-Monaghan , Jeffrey P. Gambino , Mark D. Jaffe , Jerome B Lasky , Richard A. Phelps
IPC分类号： H01L27/148
CPC分类号： H01L27/14689 , H01L27/14603 , H01L27/14609 , H01L31/0352
摘要： A pixel sensor cell structure and method of manufacture. The pixel cell comprises a doped layer formed adjacent to a first side of a transfer gate structure for coupling a collection well region and a channel region. Potential barrier interference to charge transfer caused by a pinning layer is reduced.
摘要翻译：像素传感器单元结构及其制造方法。像素单元包括与传输栅极结构的第一侧相邻形成的用于耦合收集阱区和沟道区的掺杂层。减少了由钉扎层引起的对电荷转移的电势障碍干扰。

5. 发明授权

US08618588B2 Anti-blooming pixel sensor cell with active neutral density filter, methods of manufacture, and design structure 有权
标题翻译：具有活性中性密度滤光片的防晕像素传感器单元，制造方法和设计结构
公开(公告)号：US08618588B2
公开(公告)日：2013-12-31
申请号：US12915888
申请日：2010-10-29
申请人： Kristin M. Ackerson , Jeffrey P. Gambino , Mark D. Jaffe , Robert K. Leidy , Richard J. Rassel , Robert M. Rassel
发明人： Kristin M. Ackerson , Jeffrey P. Gambino , Mark D. Jaffe , Robert K. Leidy , Richard J. Rassel , Robert M. Rassel
IPC分类号： H01L31/062 , H01L31/113
CPC分类号： H04N5/238 , H01L27/14623 , H01L27/14625 , H01L27/14685 , H04N5/3591
摘要： A method of preventing blooming in a pixel array includes affecting an amount of light that impinges on a photoelectric conversion element by adjusting a transmissivity of an electrochromic element based on an output of the photoelectric conversion element.
摘要翻译：防止像素阵列中的起霜的方法包括通过基于光电转换元件的输出调节电致变色元件的透射率来影响照射到光电转换元件上的光量。

6. 发明授权

US07772028B2 CMOS imager with Cu wiring and method of eliminating high reflectivity interfaces therefrom 失效
标题翻译：具有Cu布线的CMOS成像器和从其中消除高反射率界面的方法
公开(公告)号：US07772028B2
公开(公告)日：2010-08-10
申请号：US11959841
申请日：2007-12-19
申请人： James W. Adkisson , Jeffrey P. Gambino , Mark D. Jaffe , Robert K. Leidy , Richard J. Rassel , Anthony K. Stamper
发明人： James W. Adkisson , Jeffrey P. Gambino , Mark D. Jaffe , Robert K. Leidy , Richard J. Rassel , Anthony K. Stamper
IPC分类号： H01L21/66
CPC分类号： H01L27/14636 , H01L21/76819 , H01L21/76834 , H01L27/14621 , H01L27/14625 , H01L27/14627 , H01L27/14629 , H01L27/14645 , H01L27/14683
摘要： A CMOS image sensor and method of fabrication wherein the sensor includes Copper (Cu) metallization levels allowing for incorporation of a thinner interlevel dielectric stack to result in a pixel array exhibiting increased light sensitivity. The CMOS image sensor includes structures having a minimum thickness of barrier layer metal that traverses the optical path of each pixel in the sensor array or, that have portions of barrier layer metal selectively removed from the optical paths of each pixel, thereby minimizing reflectance. That is, by implementing various block or single mask methodologies, portions of the barrier layer metal are completely removed at locations of the optical path for each pixel in the array. In a further embodiment, the barrier metal layer may be formed atop the Cu metallization by a self-aligned deposition.
摘要翻译： CMOS图像传感器和制造方法，其中传感器包括铜（Cu）金属化水平，允许结合较薄的层间电介质堆叠以产生呈现增加的光灵敏度的像素阵列。 CMOS图像传感器包括具有穿过传感器阵列中的每个像素的光路的阻挡层金属的最小厚度的结构，或者具有从每个像素的光路中选择性地去除的阻挡层金属的部分，从而使反射率最小化的结构。也就是说，通过实现各种块或单掩模方法，在阵列中的每个像素的光路的位置处完全去除了阻挡层金属的部分。在另一个实施例中，阻挡金属层可以通过自对准沉积形成在Cu金属化之上。

7. 发明授权

US07521798B2 Stacked imager package 有权
标题翻译：堆叠成像器包
公开(公告)号：US07521798B2
公开(公告)日：2009-04-21
申请号：US11943277
申请日：2007-11-20
申请人： James W. Adkisson , Jeffrey P. Gambino , Mark D. Jaffe , Robert K. Leidy , Stephen E. Luce , Richard J. Rassel , Edmund J. Sprogis
发明人： James W. Adkisson , Jeffrey P. Gambino , Mark D. Jaffe , Robert K. Leidy , Stephen E. Luce , Richard J. Rassel , Edmund J. Sprogis
IPC分类号： H01L23/48
CPC分类号： H01L27/14618 , H01L25/0657 , H01L2224/13025 , H01L2224/16145 , H01L2224/16146 , H01L2224/16227 , H01L2224/17181 , H01L2224/48091 , H01L2224/48227 , H01L2224/73265 , H01L2225/06513 , H01L2225/06517 , H01L2225/06541 , H01L2924/13091 , H01L2924/15151 , H01L2924/00014 , H01L2924/00
摘要： An imaging system for use in a digital camera or cell phone utilizes one chip for logic and one chip for image processing. The chips are interconnected using around-the-edge or through via conductors extending from bond pads on the active surface of the imaging chip to backside metallurgy on the imaging chip. The backside metallurgy of the imaging chip is connected to metallurgy on the active surface of the logic chip using an array of solder bumps in BGA fashion. The interconnection arrangement provides a CSP which matches the space constraints of a cell phone, for example. The arrangement also utilizes minimal wire lengths for reduced noise. Connection of the CSP to a carrier package may be either by conductive through vias or wire bonding. The CSP is such that the imaging chip may readily be mounted across an aperture in the wall of a cell phone, for example, so as to expose the light sensitive pixels on the active surface of said imaging chip to light.
摘要翻译：用于数码相机或手机的成像系统利用一个芯片用于逻辑和一个芯片用于图像处理。这些芯片使用围绕成像芯片的有源表面上的接合焊盘的边缘或通孔导体互连，从而在成像芯片上进行背面冶金。成像芯片的背面冶金采用BGA焊料凸块阵列与逻辑芯片的有源表面上的冶金连接。互连装置提供例如与手机的空间限制相匹配的CSP。该布置还利用最小的线长度来降低噪声。将CSP连接到载体封装可以通过通孔或引线键合导电。 CSP使得成像芯片可以容易地安装在例如手机的壁中的孔之间，以便将所述成像芯片的有效表面上的光敏像素曝光到光。

8. 发明授权

US07361581B2 High surface area aluminum bond pad for through-wafer connections to an electronic package 有权
标题翻译：高表面积铝合金焊盘，用于通过晶片连接到电子封装
公开(公告)号：US07361581B2
公开(公告)日：2008-04-22
申请号：US10904677
申请日：2004-11-23
申请人： James W. Adkisson , Jeffrey P. Gambino , Mark D. Jaffe , Richard J. Rassel , Edmund J. Sprogis
发明人： James W. Adkisson , Jeffrey P. Gambino , Mark D. Jaffe , Richard J. Rassel , Edmund J. Sprogis
IPC分类号： H01L21/44
CPC分类号： H01L24/02 , H01L23/3114 , H01L23/481 , H01L2224/0401 , H01L2924/01013 , H01L2924/01014 , H01L2924/01019 , H01L2924/01022 , H01L2924/01024 , H01L2924/01027 , H01L2924/01028 , H01L2924/01029 , H01L2924/01033 , H01L2924/01046 , H01L2924/01047 , H01L2924/01072 , H01L2924/01073 , H01L2924/01074 , H01L2924/01076 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/14 , H01L2924/1461 , H01L2924/3011 , H01L2924/00
摘要： A bond pad for effecting through-wafer connections to an integrated circuit or electronic package and method of producing thereof. The bond pad includes a high surface area aluminum bond pad in order to resultingly obtain a highly reliable, low resistance connection between bond pad and electrical leads.
摘要翻译：用于实现通过晶片连接到集成电路或电子封装的接合焊盘及其制造方法。接合焊盘包括高表面积铝键合焊盘，以便得到接合焊盘和电引线之间的高度可靠的低电阻连接。

9. 发明授权

US07622364B2 Bond pad for wafer and package for CMOS imager 失效
标题翻译：晶圆封装和CMOS成像器封装
公开(公告)号：US07622364B2
公开(公告)日：2009-11-24
申请号：US11465622
申请日：2006-08-18
申请人： James W. Adkisson , Jeffrey P. Gambino , Mark D. Jaffe , Richard J. Rassel
发明人： James W. Adkisson , Jeffrey P. Gambino , Mark D. Jaffe , Richard J. Rassel
IPC分类号： H01L21/00
CPC分类号： H01L24/05 , H01L23/3114 , H01L23/485 , H01L23/562 , H01L23/585 , H01L24/03 , H01L2224/05553 , H01L2224/0558 , H01L2224/05624 , H01L2924/01013 , H01L2924/01014 , H01L2924/01022 , H01L2924/01023 , H01L2924/01024 , H01L2924/01027 , H01L2924/01029 , H01L2924/01033 , H01L2924/01046 , H01L2924/01047 , H01L2924/01072 , H01L2924/01073 , H01L2924/01074 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/14 , H01L2924/1461 , H01L2924/00014 , H01L2924/00
摘要： An electronic packaging having at least one bond pad positioned on a chip for effectuating through-wafer connections to an integrated circuit. The electronic package is equipped with an edge seal between the bond pad region and an active circuit region, and includes a crack stop, which is adapted to protect the arrangement from the entry of deleterious moisture and combination into the active regions of the chip containing the bond pads.
摘要翻译：一种电子封装，其具有位于芯片上的至少一个接合焊盘，用于实现与集成电路的晶圆连接。电子封装在接合焊盘区域和有源电路区域之间配备有边缘密封，并且包括裂缝停止件，其适于保护布置免受有害水分和组合进入含有接合垫

10. 发明申请

US20080116537A1 CMOS IMAGER ARRAY WITH RECESSED DIELECTRIC 有权
标题翻译： CMOS图像阵列带有电介质
公开(公告)号：US20080116537A1
公开(公告)日：2008-05-22
申请号：US11560882
申请日：2006-11-17
申请人： James W. Adkisson , Jeffrey P. Gambino , Zhong-Xiang He , Mark D. Jaffe , Robert K. Leidy , Stephen E. Luce , Richard J. Rassel , Edmund J. Sprogis
发明人： James W. Adkisson , Jeffrey P. Gambino , Zhong-Xiang He , Mark D. Jaffe , Robert K. Leidy , Stephen E. Luce , Richard J. Rassel , Edmund J. Sprogis
IPC分类号： H01L27/146 , H01L21/04
CPC分类号： H01L27/14687 , H01L27/14618 , H01L27/14621 , H01L27/14627 , H01L27/14632 , H01L27/14685 , H01L2224/05001 , H01L2224/05008 , H01L2224/05124 , H01L2224/05548 , H01L2224/05569 , H01L2224/05647 , H01L2224/13 , H01L2924/00014
摘要： A CMOS image sensor array and method of fabrication. The CMOS imager sensor array comprises a substrate; an array of light receiving pixel structures formed above the substrate, the array having formed therein “m” levels of conductive structures, each level formed in a corresponding interlevel dielectric material layer; a dense logic wiring region formed adjacent to the array of light receiving pixel structures having “n” levels of conductive structures, each level formed in a corresponding interlevel dielectric material layer, where n>m. A microlens array having microlenses and color filters formed above the interlevel dielectric material layer, a microlens and respective color filter in alignment with a respective light receiving structure formed at a surface of the substrate. A top surface of the interlevel dielectric material layer beneath the microlens array is recessed from a top surface of the interlevel dielectric material layers of the dense logic wiring region.
摘要翻译： CMOS图像传感器阵列及其制造方法。 CMOS成像器传感器阵列包括衬底; 形成在衬底上方的光接收像素结构的阵列，阵列中形成有“m”级的导电结构，每个级形成在相应的层间介电材料层中; 与具有“n”级的导电结构的光接收像素结构的阵列相邻形成的密集的逻辑布线区域，每个层级形成在相应的层间电介质材料层中，其中n> m。具有形成在层间电介质材料层上方的微透镜和滤色器的微透镜阵列，与形成在衬底表面处的各个光接收结构对准的微透镜和相应的滤色器。微透镜阵列下面的层间介电材料层的顶表面从密集逻辑布线区域的层间介电材料层的顶表面凹陷。

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