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1. 发明授权

US08122400B2 Logic difference synthesis 有权
标题翻译：逻辑差分合成
公开(公告)号：US08122400B2
公开(公告)日：2012-02-21
申请号：US12497499
申请日：2009-07-02
申请人： Jeremy T. Hopkins , John M. Isakson , Joachim Keinert , Smita Krishnaswamy , Nilesh A. Modi , Ruchir Puri , Haoxing Ren , David L. Rude
发明人： Jeremy T. Hopkins , John M. Isakson , Joachim Keinert , Smita Krishnaswamy , Nilesh A. Modi , Ruchir Puri , Haoxing Ren , David L. Rude
IPC分类号： G06F17/50
CPC分类号： G06F17/505
摘要： A computer executed method is disclosed which accepts an original circuit with an original logic, accepts a modified circuit, and synthesizes a difference circuit. The difference circuit represents changes that implement the modified circuit's logic for the original circuit. The synthesis may locate an output-side boundary in the original logic in such a manner that the original logic is free of logic changes in between the output-side boundary and the primary output elements of the original circuit. The disclosed synthesis may also locate an input-side boundary in the original logic in such a manner that the original logic is free of logic changes in between the input-side boundary and the primary input elements of the original circuit. A computer program products are also disclosed. The computer program product contains a computer useable medium having a computer readable program code embodied therein. The computer readable program code when executed on a computer causes the computer to carry out the methods of finding input and output side boundaries in an original logic, and synthesizing in between those boundaries a difference circuit representing logic changes.
摘要翻译：公开了一种用原始逻辑接收原始电路的计算机执行方法，接受修改的电路，并且合成差分电路。差分电路表示实现原始电路的修改电路逻辑的变化。合成可以将原始逻辑中的输出侧边界定位成使得原始逻辑在原始电路的输出侧边界和主要输出元件之间没有逻辑改变。所公开的合成还可以将原始逻辑中的输入侧边界定位成使得原始逻辑在原始电路的输入侧边界和主要输入元件之间没有逻辑改变。还公开了一种计算机程序产品。计算机程序产品包含具有体现在其中的计算机可读程序代码的计算机可用介质。计算机可读程序代码在计算机上执行时，使得计算机执行在原始逻辑中寻找输入和输出侧边界的方法，并且在这些边界之间合成表示逻辑的差异电路的变化。

2. 发明申请

US20110004857A1 LOGIC DIFFERENCE SYNTHESIS 有权
标题翻译：逻辑差异综合
公开(公告)号：US20110004857A1
公开(公告)日：2011-01-06
申请号：US12497499
申请日：2009-07-02
申请人： Jeremy T. Hopkins , John M. Isakson , Joachim Keinert , Smita Krishnaswamy , Nilesh A. Modi , Ruchir Puri , Haoxing Ren , David L. Rude
发明人： Jeremy T. Hopkins , John M. Isakson , Joachim Keinert , Smita Krishnaswamy , Nilesh A. Modi , Ruchir Puri , Haoxing Ren , David L. Rude
IPC分类号： G06F17/50
CPC分类号： G06F17/505
摘要： A computer executed method is disclosed which accepts an original circuit with an original logic, accepts a modified circuit, and synthesizes a difference circuit. The difference circuit represents changes that implement the modified circuit's logic for the original circuit. The synthesis may locate an output-side boundary in the original logic in such a manner that the original logic is free of logic changes inbetween the output-side boundary and the primary output elements of the original circuit. The disclosed synthesis may also locate an input-side boundary in the original logic in such a manner that the original logic is free of logic changes inbetween the input-side boundary and the primary input elements of the original circuit. A computer program products are also disclosed. The computer program product contains a computer useable medium having a computer readable program code embodied therein. The computer readable program code when executed on a computer causes the computer to carry out the methods of finding input and output side boundaries in an original logic, and synthesizing inbetween those boundaries a difference circuit representing logic changes.
摘要翻译：公开了一种用原始逻辑接收原始电路的计算机执行方法，接受修改的电路，并且合成差分电路。差分电路表示实现原始电路的修改电路逻辑的变化。合成可以将原始逻辑中的输出侧边界定位成使得原始逻辑在原始电路的输出侧边界和初级输出元件之间没有逻辑改变。所公开的合成还可以以原始逻辑在原始电路的输入侧边界和主要输入元件之间没有逻辑改变的方式将原始逻辑中的输入侧边界定位。还公开了一种计算机程序产品。计算机程序产品包含具有体现在其中的计算机可读程序代码的计算机可用介质。计算机可读程序代码在计算机上执行时，使得计算机执行在原始逻辑中寻找输入和输出侧边界的方法，并且在这些边界之间合成表示逻辑变化的差分电路。

3. 发明授权

US08166439B2 Techniques for selecting spares to implement a design change in an integrated circuit 有权
标题翻译：选择备件以实现集成电路中的设计变更的技术
公开(公告)号：US08166439B2
公开(公告)日：2012-04-24
申请号：US11966043
申请日：2007-12-28
申请人： Jeremy T. Hopkins , Thomas E. Rosser
发明人： Jeremy T. Hopkins , Thomas E. Rosser
IPC分类号： G06F17/50
CPC分类号： G06F17/5045 , G06F2217/72
摘要： A technique for implementing an engineering change order includes determining spares that are available to implement a modification to a circuit design. One of the available spares is then selected to implement the modification to the circuit design based on performance criteria associated with each of the available spares.
摘要翻译：实现工程变更订单的技术包括确定可用于实现对电路设计的修改的备件。然后选择一个可用备件，以根据与每个可用备件相关联的性能标准来实现对电路设计的修改。

4. 发明授权

US07979819B2 Minterm tracing and reporting 有权
标题翻译： Minterm跟踪和报告
公开(公告)号：US07979819B2
公开(公告)日：2011-07-12
申请号：US12358793
申请日：2009-01-23
申请人： Jeremy T. Hopkins , Thomas E. Rosser
发明人： Jeremy T. Hopkins , Thomas E. Rosser
IPC分类号： G06F17/50
CPC分类号： G06F17/505
摘要： Disclosed are a method, a system and a computer program product for determining and reporting minterms to aid in implementing an engineering change order (ECO). A Minterm Tracing and Reporting (MTR) utility, which executes on a computer system, receives two or more timing points of an optimized netlist, where one or more of the two or more timing points are received from one or more of a user, a memory medium, and/or a network. For example, a timing point is a primary input, a primary output, or a latch point. After receiving the two or more timing points of the optimized netlist, the MTR utility determines two or more minterms of the optimized netlist. In determining the minterms, from one timing point to a next timing point: a polarity at the timing point may be determined, and a forward trace from the timing point to the next timing point is performed to determine the two or more minterms of the optimized netlist. In the forward trace from the timing point to the next timing point, the MTR utility determines two or more logical cones and one or more intersections of the logical cones. The MTR utility reports (e.g., communicates) each of the determined minterms, the determined polarities, and the one or more intersections of logical cones to one or more of a computer-executable application, a network, a memory medium, and/or a display.
摘要翻译：公开了一种方法，系统和计算机程序产品，用于确定和报告子项以帮助实施工程变更单（ECO）。在计算机系统上执行的Minterm跟踪和报告（MTR）实用程序接收优化网表的两个或更多个定时点，其中两个或多个定时点中的一个或多个从用户的一个或多个接收，存储介质和/或网络。例如，定时点是主输入，主输出或锁存点。在接收到优化网表的两个或多个时间点之后，MTR实用程序确定优化网表的两个或更多个minterms。在从一个定时点到下一个定时点的确定中，可以确定定时点处的极性，并且执行从定时点到下一定时点的前向跟踪，以确定优化的时间点的两个或更多个小区网表。在从定时点到下一定时点的前向跟踪中，MTR实用程序确定逻辑锥的两个或更多个逻辑锥和一个或多个交集。 MTR实用程序将计算机可执行应用程序，网络，存储介质和/或其中的一个或多个报告（例如，通信）所确定的最小值，所确定的极性以及逻辑锥的一个或多个交叉点显示。

5. 发明授权

US08234612B2 Cone-aware spare cell placement using hypergraph connectivity analysis 有权
标题翻译：使用超图连接性分析的锥形识别备用单元布局
公开(公告)号：US08234612B2
公开(公告)日：2012-07-31
申请号：US12862949
申请日：2010-08-25
申请人： Benjiman L. Goodman , Nathaniel D. Hieter , Jeremy T. Hopkins , Samuel I. Ward
发明人： Benjiman L. Goodman , Nathaniel D. Hieter , Jeremy T. Hopkins , Samuel I. Ward
IPC分类号： G06F17/50
CPC分类号： G06F17/5072 , G06F2217/02 , G06F2217/72
摘要： Spare cells are placed in an IC design by assigning different spare utilization rates to logic cones, applying the rates to corresponding spare cell regions surrounding cells in the cones, identifying any overlap of regions from different logic cones, and inserting a spare cell at the overlapping region having the highest spare utilization rate. The best location for the spare cell is computed using a hypergraph wherein the cells are edges and the regions are nodes. Any node that is dominated by another node is removed and its edge is extended to the dominating node. The spare cell is inserted in the region having the most edges (the edges can be weighted). The process is repeated iteratively, updating the hypergraph by removing nodes connected to spare cell location, and inserting the next spare cell at a region corresponding to the node which then has the greatest number of connected edges.
摘要翻译：通过向逻辑锥分配不同的备用利用率来将备用单元放置在IC设计中，将速率应用于圆锥体中的小区周围的相应备用单元区域，识别来自不同逻辑锥的区域的任何重叠，以及在重叠处插入备用单元具有最高备用利用率的区域。使用超图来计算备用单元的最佳位置，其中单元是边缘，并且区域是节点。由另一个节点主导的任何节点被去除，其边缘被扩展到主导节点。备用单元插入具有最多边缘的区域（边缘可以加权）。该过程重复地重复，通过去除连接到备用单元位置的节点来更新超图，并且将下一个备用单元插入到与具有最大连接边数的节点相对应的区域。

6. 发明授权

US08479136B2 Decoupling capacitor insertion using hypergraph connectivity analysis 有权
标题翻译：使用超图连接分析去耦电容插入
公开(公告)号：US08479136B2
公开(公告)日：2013-07-02
申请号：US13099767
申请日：2011-05-03
申请人： Jeremy T. Hopkins , David A. Papa , Samuel I. Ward
发明人： Jeremy T. Hopkins , David A. Papa , Samuel I. Ward
IPC分类号： G06F17/50
CPC分类号： G06F17/5063 , G06F17/5072 , G06F2217/78
摘要： Decoupling capacitors (dcaps) are placed in an IC design by assigning different dcap utilization rates to logic cones, applying the rates to corresponding dcap regions surrounding cells in the cones, identifying any overlap of regions from different logic cones, and inserting a dcap at the overlapping region having the highest dcap utilization rate. The best location for the dcap is computed using a hypergraph wherein the cells are edges and the regions are nodes. Any node that is dominated by another node is removed and its edge is extended to the dominating node. The dcap is inserted in the region having the most edges (the edges can be weighted). The process is repeated iteratively, updating the hypergraph by removing nodes connected to dcap location, and inserting the next dcap at a region corresponding to the node which then has the greatest number of connected edges.
摘要翻译：将去耦电容（dcaps）放置在IC设计中，通过将不同的dcap利用率分配给逻辑锥，将速率应用于锥体中的细胞周围的相应dcap区域，识别来自不同逻辑锥的区域的任何重叠，以及将dcap插入到重叠区域具有最高的dcap利用率。使用超图来计算dcap的最佳位置，其中单元格是边缘，并且区域是节点。由另一个节点主导的任何节点被去除，其边缘被扩展到主导节点。将dcap插入具有最多边缘的区域（边缘可以加权）。该过程重复地重复，通过去除连接到dcap位置的节点来更新超图，并将下一个dcap插入到与具有最大连接边数的节点对应的区域。

7. 发明申请

US20120066654A1 STABILITY-DEPENDENT SPARE CELL INSERTION 有权
标题翻译：稳定性依赖的备用电池插入
公开(公告)号：US20120066654A1
公开(公告)日：2012-03-15
申请号：US12879516
申请日：2010-09-10
申请人： Jeremy T. Hopkins , Julie A. Rosser , Samuel I. Ward
发明人： Jeremy T. Hopkins , Julie A. Rosser , Samuel I. Ward
IPC分类号： G06F17/50
CPC分类号： G06F17/505 , G06F17/5072 , G06F2217/02 , G06F2217/72
摘要： Spare cells are placed in an IC design using stability values associated with logic cones of the design. A desired spare cell utilization rate is assigned to a cone based on its stability value, and an actual spare cell utilization rate for the cone bounding box is calculated. If the actual utilization rate is less than the desired utilization rate, additional spare cells are inserted as needed to attain the desired utilization rate. The stability value is provided by a logic or circuit designer, or derived from historical information regarding the logic cone in a previous design iteration. Spare cells are placed for each logic cone in the design until a global spare cell utilization target is exceeded. The spare cell placement method can be an integrated part of a placement directed synthesis which is followed by early mode padding and design routing.
摘要翻译：使用与设计的逻辑锥相关联的稳定性值将备用电池放置在IC设计中。基于其稳定性值将期望的备用小区利用率分配给锥，并且计算锥形边界框的实际备用小区利用率。如果实际使用率小于期望的利用率，则根据需要插入额外的备用单元以获得期望的利用率。稳定性值由逻辑或电路设计者提供，或从先前设计迭代中关于逻辑锥的历史信息导出。在设计中为每个逻辑锥放置备用单元，直到超过全局备用单元利用目标。备用单元放置方法可以是放置定向合成的集成部分，其后是早期模式填充和设计路由。

8. 发明申请

US20090172608A1 Techniques for Selecting Spares to Implement a Design Change in an Integrated Circuit 有权
标题翻译：选择备件以实现集成电路设计变更的技术
公开(公告)号：US20090172608A1
公开(公告)日：2009-07-02
申请号：US11966043
申请日：2007-12-28
申请人： Jeremy T. Hopkins , Thomas E. Rosser
发明人： Jeremy T. Hopkins , Thomas E. Rosser
IPC分类号： G06F17/50
CPC分类号： G06F17/5045 , G06F2217/72
摘要： A technique for implementing an engineering change order includes determining spares that are available to implement a modification to a circuit design. One of the available spares is then selected to implement the modification to the circuit design based on performance criteria associated with each of the available spares.
摘要翻译：实现工程变更订单的技术包括确定可用于实现对电路设计的修改的备件。然后选择一个可用备件，以根据与每个可用备件相关联的性能标准来实现对电路设计的修改。

9. 发明申请

US20120284676A1 DECOUPLING CAPACITOR INSERTION USING HYPERGRAPH CONNECTIVITY ANALYSIS 有权
标题翻译：使用HYPERGRAPH连接分析解耦电容器插入
公开(公告)号：US20120284676A1
公开(公告)日：2012-11-08
申请号：US13099767
申请日：2011-05-03
申请人： Jeremy T. Hopkins , Samuel I. Ward , David A. Papa
发明人： Jeremy T. Hopkins , Samuel I. Ward , David A. Papa
IPC分类号： G06F17/50
CPC分类号： G06F17/5063 , G06F17/5072 , G06F2217/78
摘要： Decoupling capacitors (dcaps) are placed in an IC design by assigning different dcap utilization rates to logic cones, applying the rates to corresponding dcap regions surrounding cells in the cones, identifying any overlap of regions from different logic cones, and inserting a dcap at the overlapping region having the highest dcap utilization rate. The best location for the dcap is computed using a hypergraph wherein the cells are edges and the regions are nodes. Any node that is dominated by another node is removed and its edge is extended to the dominating node. The dcap is inserted in the region having the most edges (the edges can be weighted). The process is repeated iteratively, updating the hypergraph by removing nodes connected to dcap location, and inserting the next dcap at a region corresponding to the node which then has the greatest number of connected edges.
摘要翻译：将去耦电容（dcaps）放置在IC设计中，通过将不同的dcap利用率分配给逻辑锥，将速率应用于锥体中的细胞周围的相应dcap区域，识别来自不同逻辑锥的区域的任何重叠，以及将dcap插入到重叠区域具有最高的dcap利用率。使用超图来计算dcap的最佳位置，其中单元格是边缘，并且区域是节点。由另一个节点主导的任何节点被去除，其边缘被扩展到主导节点。将dcap插入具有最多边缘的区域（边缘可以加权）。该过程重复地重复，通过去除连接到dcap位置的节点来更新超图，并将下一个dcap插入到与具有最大连接边数的节点对应的区域。

10. 发明授权

US08266566B2 Stability-dependent spare cell insertion 有权
标题翻译：稳定性依赖的备用电池插入
公开(公告)号：US08266566B2
公开(公告)日：2012-09-11
申请号：US12879516
申请日：2010-09-10
申请人： Jeremy T. Hopkins , Julie A. Rosser , Samuel I. Ward
发明人： Jeremy T. Hopkins , Julie A. Rosser , Samuel I. Ward
IPC分类号： G06F9/455 , G06F17/50 , G06F15/04
CPC分类号： G06F17/505 , G06F17/5072 , G06F2217/02 , G06F2217/72
摘要： Spare cells are placed in an IC design using stability values associated with logic cones of the design. A desired spare cell utilization rate is assigned to a cone based on its stability value, and an actual spare cell utilization rate for the cone bounding box is calculated. If the actual utilization rate is less than the desired utilization rate, additional spare cells are inserted as needed to attain the desired utilization rate. The stability value is provided by a logic or circuit designer, or derived from historical information regarding the logic cone in a previous design iteration. Spare cells are placed for each logic cone in the design until a global spare cell utilization target is exceeded. The spare cell placement method can be an integrated part of a placement directed synthesis which is followed by early mode padding and design routing.
摘要翻译：使用与设计的逻辑锥相关联的稳定性值将备用电池放置在IC设计中。基于其稳定性值将期望的备用小区利用率分配给锥，并且计算锥形边界框的实际备用小区利用率。如果实际使用率小于期望的利用率，则根据需要插入额外的备用单元以获得期望的利用率。稳定性值由逻辑或电路设计者提供，或从先前设计迭代中关于逻辑锥的历史信息导出。在设计中为每个逻辑锥放置备用单元，直到超过全局备用单元利用目标。备用单元放置方法可以是放置定向合成的集成部分，其后是早期模式填充和设计路由。

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