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1. 发明授权

US4962064A Method of planarization of topologies in integrated circuit structures 失效
标题翻译：集成电路结构拓扑的平面化方法
公开(公告)号：US4962064A
公开(公告)日：1990-10-09
申请号：US193478
申请日：1988-05-12
申请人： Jacob D. Haskell , Craig S. Sander , Steven C. Avanzino , Subhash Gupta
发明人： Jacob D. Haskell , Craig S. Sander , Steven C. Avanzino , Subhash Gupta
IPC分类号： H01L21/302 , H01L21/304 , H01L21/3065 , H01L21/31 , H01L21/3105 , H01L21/316 , H01L21/321 , H01L21/76 , H01L21/762
CPC分类号： H01L21/3212 , H01L21/31056 , H01L21/76229 , Y10S148/051 , Y10S438/959
摘要： A method is disclosed for making a highly planarized integrated circuit structure having deposited oxide portions planarized to the level of adjacent portions of the integrated circuit structure which comprises: deposition, over an integrated circuit structure having first portions at a height higher than the remainder of the integrated circuit structure, a conformal oxide layer; depositing a layer of a planarizing material such as polysilicon over the conformal oxide layer; polishing the structure a first time to expose the highest portions of the underlying conformal oxide layer; etching the structure a first time with an etchant system capable of removing the conformal oxide preferentially to the planarizing material; further polishing the structure a second time to remove planarizing material left from the first etching step; and then optionally etching the remainder of the structure to remove any remaining planarizing material and the remaining conformal oxide over the raised portions of the underlying integrated circuit structure to provide the desired highly planarized structure.

2. 发明授权

US4954459A Method of planarization of topologies in integrated circuit structures 失效
标题翻译：集成电路结构拓扑的平面化方法
公开(公告)号：US4954459A
公开(公告)日：1990-09-04
申请号：US376176
申请日：1989-07-03
申请人： Steven C. Avanzino , Jacob D. Haskell
发明人： Steven C. Avanzino , Jacob D. Haskell
IPC分类号： H01L21/76 , H01L21/3105 , H01L21/3205 , H01L21/321 , H01L21/762
CPC分类号： H01L21/3212 , H01L21/31056 , H01L21/76229 , Y10S148/051 , Y10S438/959
摘要： A method is disclosed for making a highly planarized integrated circuit structure having deposited oxide portions planarized to the level of adjacent portions of the integrated circuit structure which comprises: depositing, over an integrated circuit structure having first portions at a height higher than the remainder of the integrated circuit structure, a conformal oxide layer having a thickness which exceeds the height of said first portions above the remainder of the integrated circuit structure; forming a patterned mask layer over said deposited oxide layer with one or more openings therein in registry with the higher height first portions of the integrated circuit structure; etching exposed portions of said conformal oxide layer through the mask openings down to a level approximately equal to the level of the unexposed portion of the conformal oxide layer; removing the mask layer; and polishing the oxide layer to remove raised portions of the conformal oxide layer remaining after the etching step to form a highly planarized structure. Optionally, the oxide layer may be further etched anisotropically until the upper surfaces of the underlying integrated circuit structure is exposed.
摘要翻译：公开了一种用于制造具有平坦化到集成电路结构的相邻部分的平面的沉积氧化物部分的高度平坦化的集成电路结构的方法，其包括：在集成电路结构上沉积，该集成电路结构具有高于其余部分的高度的第一部分集成电路结构，具有超过所述集成电路结构的其余部分之上的所述第一部分的高度的厚度的共形氧化物层; 在其上具有一个或多个开口的所述沉积的氧化物层上形成图案化掩模层，与所述集成电路结构的较高高度的第一部分对齐; 将所述保形氧化物层的暴露部分通过所述掩模开口蚀刻到约等于所述共形氧化物层的未曝光部分的水平的水平; 去除掩模层; 并抛光氧化物层以除去在蚀刻步骤之后残留的保形氧化物层的凸起部分，以形成高度平坦化的结构。任选地，可以进一步各向异性地蚀刻氧化物层，直到暴露底层集成电路结构的上表面。

3. 发明授权

US5116778A Dopant sources for CMOS device 失效
标题翻译： CMOS器件的掺铒光源
公开(公告)号：US5116778A
公开(公告)日：1992-05-26
申请号：US474614
申请日：1990-02-05
申请人： Jacob D. Haskell , Steven C. Avanzino , Balaji Swaminathan
发明人： Jacob D. Haskell , Steven C. Avanzino , Balaji Swaminathan
IPC分类号： H01L21/22 , H01L21/225 , H01L21/316 , H01L21/74 , H01L21/76 , H01L21/762 , H01L21/8238 , H01L27/092
CPC分类号： H01L21/02274 , H01L21/02129 , H01L21/022 , H01L21/2255 , H01L21/31625 , H01L21/743 , H01L21/762 , H01L21/76229 , H01L21/76237 , H01L21/823878
摘要： A process is provided for doping both sidewalls (26, 28) of isolation trenches (24, 26, 28) and connector regions (46, 48) between sources (58) and gate areas (62) and between drains (60) and gate areas in silicon CMOS devices. Appropriately doped glasses (16, 18, 30) formed on the silicon substrate (14) serve as the source of doping.

4. 发明授权

US4677589A Dynamic random access memory cell having a charge amplifier 失效
标题翻译：具有电荷放大器的动态随机存取存储单元
公开(公告)号：US4677589A
公开(公告)日：1987-06-30
申请号：US759532
申请日：1985-07-26
申请人： Jacob D. Haskell , Craig S. Sander
发明人： Jacob D. Haskell , Craig S. Sander
IPC分类号： G11C11/404 , G11C11/405 , G11C11/24
CPC分类号： G11C11/404 , G11C11/405
摘要： An improved dynamic random access memory (DRAM) cell circuit (46) having a charge amplifier is presented. The improvement comprises a bipolar amplification means (64) for amplifying a charge as it is read out of the memory cell (46). According to one embodiment of the present invention, in addition to a standard charge storage capacitor (50) and MOS transistor (48), the memory cell (46) also includes a write control line (60) and a second MOS transistor (62) for writing a "1" bit of information into the memory cell (46). These improvements require little or no additional space when used in a DRAM circuit and allow a reduction in the required capacitor area.
摘要翻译：提出了具有电荷放大器的改进的动态随机存取存储器（DRAM）单元电路（46）。该改进包括用于在从存储单元（46）读出电荷时放大电荷的双极放大装置（64）。根据本发明的一个实施例，除了标准电荷存储电容器（50）和MOS晶体管（48）之外，存储单元（46）还包括写控制线（60）和第二MOS晶体管（62）用于将“1”位信息写入存储单元（46）。当在DRAM电路中使用时，这些改进需要很少或没有额外的空间，并且可以减少所需的电容器面积。

5. 发明授权

US5136361A Stratified interconnect structure for integrated circuits 失效
标题翻译：用于集成电路的分层互连结构
公开(公告)号：US5136361A
公开(公告)日：1992-08-04
申请号：US338439
申请日：1989-04-13
申请人： Donald L. Wollesen , Craig S. Sander , Jacob D. Haskell
发明人： Donald L. Wollesen , Craig S. Sander , Jacob D. Haskell
IPC分类号： H01L21/768 , H01L23/532
CPC分类号： H01L23/53223 , H01L21/76889 , H01L2924/0002
摘要： A low resistance interconnect structure for integrated circuits formed by a composite layer of aluminum below and an amorphous compound of refractory metal and silicon above. In the process of manufacturing the interconnect structure, care must be taken so that an aluminum oxide layer is not formed between the aluminum and compound layers.
摘要翻译：由下面的铝复合层和难熔金属和硅的无定形化合物形成的用于集成电路的低电阻互连结构。在制造互连结构的过程中，必须注意在铝和化合物层之间不形成氧化铝层。

6. 发明授权

US5395796A Etch stop layer using polymers for integrated circuits 失效
标题翻译：用于集成电路的聚合物的蚀刻停止层
公开(公告)号：US5395796A
公开(公告)日：1995-03-07
申请号：US2573
申请日：1993-01-11
申请人： Jacob D. Haskell , Subhash Gupta
发明人： Jacob D. Haskell , Subhash Gupta
IPC分类号： H01L21/3105 , H01L21/311 , H01L21/768 , H01L21/44
CPC分类号： H01L21/76801 , H01L21/31055 , H01L21/31116 , H01L21/76834 , Y10S438/97 , Y10T428/265 , Y10T428/31612 , Y10T428/31663
摘要： An etch stop layer (22) for permitting distinguishing between two similar layers (20, 24), such as two oxide layers, during etching is provided. The etch stop layer comprises a silicon-oxyhalide polymer, preferably a silicon-oxyfluoride polymer. Use of the polymer as an etch stop layer permits closer placement of metal conductor surfaces (12, 12') and contacts (14').
摘要翻译：提供了用于允许在蚀刻期间区分两个相似层（20,24），例如两个氧化物层的蚀刻停止层（22）。蚀刻停止层包括硅 - 卤氧化物聚合物，优选硅 - 氟氧化物聚合物。使用聚合物作为蚀刻停止层允许金属导体表面（12,12'）和触点（14'）的更靠近的放置。

7. 发明授权

US5198298A Etch stop layer using polymers 失效
标题翻译：使用聚合物的蚀刻停止层
公开(公告)号：US5198298A
公开(公告)日：1993-03-30
申请号：US426147
申请日：1989-10-24
申请人： Jacob D. Haskell , Subhash Gupta
发明人： Jacob D. Haskell , Subhash Gupta
IPC分类号： H01L21/3105 , H01L21/311 , H01L21/768
CPC分类号： H01L21/76801 , H01L21/31055 , H01L21/31116 , H01L21/76834 , Y10S438/97 , Y10T428/265 , Y10T428/31612 , Y10T428/31663
摘要： An etch stop player (22) for permitting distinguishing between two similar layers (20, 24), such as two oxide layers, during etching is provided. The etch stop layer comprises a silicon-oxyhalide polymer, preferably a silicon-oxyfluoride polymer. Use of the polymer as an etch stop layer permits closer placement of metal conductor surfaces (12, 12') and contacts (14').
摘要翻译：提供了用于允许在蚀刻期间区分两个相似层（20,24）（例如两个氧化物层）的蚀刻停止播放器（22）。蚀刻停止层包括硅 - 卤氧化物聚合物，优选硅 - 氟氧化物聚合物。使用聚合物作为蚀刻停止层允许金属导体表面（12,12'）和触点（14'）的更靠近的放置。

8. 发明授权

US4818714A Method of making a high performance MOS device having LDD regions with graded junctions 失效
标题翻译：制造具有分级结的LDD区的高性能MOS器件的方法
公开(公告)号：US4818714A
公开(公告)日：1989-04-04
申请号：US127995
申请日：1987-12-02
申请人： Jacob D. Haskell
发明人： Jacob D. Haskell
IPC分类号： H01L21/336 , H01L21/8238 , H01L29/78 , H01L21/265 , H01L21/70 , H01L27/00
CPC分类号： H01L29/6659 , H01L21/823814 , H01L29/6656 , H01L29/78 , Y10S148/106 , Y10S148/131 , Y10S257/90
摘要： An MOS structure and a method for making same, including the formation of el-shaped shielding members used to form one or more lightly doped drain regions to avoid short channel and punch-through problems is disclosed which comprises forming a shielding layer of an insulating material over a gate electrode on a substrate; forming another layer of a dissimilar material over the shielding layer; anisotropically etching the layer of dissimilar material to form spacer portions adjacent the sidewalls of the gate electrode; removing the portions of the shielding layer not masked by the spacer portions, leaving one or more el-shaped shielding members; removing the spacer portions; N+ or P+ implanting the substrate at a sufficiently low energy to prevent penetration of the dopant through the el-shaped shielding member to form a highly doped source/drain region in the substrate not shielded by the el-shaped shielding member or the gate electrode; N- or P- implanting the substrate at a sufficiently high energy to penetrate through the el-shaped shielding member to form a lightly doped source/drain region in the portion of the substrate adjacent the P+ or N+ source/drain regions and separating the channel region of the substrate beneath the gate electrode from the P+ or N+ source/drain region.
摘要翻译：公开了一种MOS结构及其制造方法，包括形成用于形成一个或多个轻掺杂漏极区的el形屏蔽构件以避免短沟道和穿通问题，其包括形成绝缘材料的屏蔽层在基板上的栅电极上; 在所述屏蔽层上形成不同材料的另一层; 各向异性地蚀刻不同材料层以形成邻近栅电极的侧壁的间隔部分; 去除未被隔离物部分掩蔽的屏蔽层的部分，留下一个或多个el形屏蔽构件; 移除间隔部分; N +或P +以足够低的能量注入衬底以防止掺杂剂穿过el形屏蔽构件，以在衬底中形成高度掺杂的源极/漏极区域，而不被EL形屏蔽构件或栅电极屏蔽; N或P-以足够高的能量注入衬底以穿透el形屏蔽构件，以在衬底的与P +或N +源极/漏极区相邻的部分中形成轻掺杂的源极/漏极区，并分离沟道从P +或N +源极/漏极区域到栅电极下方的衬底的区域。

9. 发明授权

US4729001A Short-channel field effect transistor 失效
标题翻译：短沟道场效应晶体管
公开(公告)号：US4729001A
公开(公告)日：1988-03-01
申请号：US555248
申请日：1983-11-25
申请人： Jacob D. Haskell
发明人： Jacob D. Haskell
IPC分类号： H01L29/10 , H01L29/78 , H01L29/786 , H01L29/08
CPC分类号： H01L29/1083 , H01L29/78 , H01L29/78621
摘要： An improved short-channel field effect transistor including a standard tip implant type of source and drain each disposed in the surface of a semiconductor substrate and a gate electrode positioned upon the substrate between the source and drain and control plugs disposed in the substrate and associated with and contiguous to the source and drain for eliminating substrate punch-through currents without substantially increasing the device junction capacitance.
摘要翻译：一种改进的短沟道场效应晶体管，其包括各自设置在半导体衬底的表面中的标准尖端注入型源极和漏极，以及位于源极和漏极之间的衬底上的栅电极以及布置在衬底中的控制插塞并且与源极和漏极相邻以消除衬底穿通电流而基本上不增加器件结电容。

10. 发明授权

US4495025A Process for forming grooves having different depths using a single masking step 失效
标题翻译：使用单个掩蔽步骤形成具有不同深度的槽的工艺
公开(公告)号：US4495025A
公开(公告)日：1985-01-22
申请号：US597617
申请日：1984-04-06
申请人： Jacob D. Haskell
发明人： Jacob D. Haskell
IPC分类号： H01L21/308 , H01L21/762 , H01L21/306 , B44C1/22 , C03C15/00 , C03C25/06
CPC分类号： H01L21/76232 , H01L21/3086 , H01L21/76229
摘要： A process for forming grooves of different depths using a single masking step is presented. In the preferred embodiment of the present invention a photoresist material is used as a single masking layer. The grooves of different types are defined in the masking layer such that the image for a first type groove is narrower in width than the image for a second type groove. The grooves are then formed by subsequent etching steps using conventional etching and anisotropic etching techniques. The grooves are etched to different depths by calculating the proper thickness of a protective layer in relationship to the different groove widths which will allow the deeper groove to be etched without affecting the shallower groove.
摘要翻译：提出了使用单个掩蔽步骤形成不同深度的槽的工艺。在本发明的优选实施方案中，光致抗蚀剂材料用作单一掩蔽层。在掩模层中限定不同类型的凹槽，使得用于第一类型凹槽的图像的宽度比第二类型凹槽的图像窄。然后通过使用常规蚀刻和各向异性蚀刻技术的后续蚀刻步骤形成凹槽。通过计算与不同沟槽宽度相关的保护层的适当厚度，将凹槽蚀刻到不同的深度，这将允许更深的凹槽被蚀刻而不影响较浅的凹槽。

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