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1. 发明授权

US5546591A Distributed power management system for battery operated personal computers 失效
标题翻译：用于电池供电的个人电脑的分布式电源管理系统
公开(公告)号：US5546591A
公开(公告)日：1996-08-13
申请号：US190697
申请日：1994-02-01
申请人： Henry Wurzburg , Walter H. Potts
发明人： Henry Wurzburg , Walter H. Potts
IPC分类号： G06F1/32 , G06F13/10 , G06F9/00
CPC分类号： G06F1/3215 , G06F1/3281 , G06F1/3287 , Y02B60/1264 , Y02B60/1282
摘要： A system for providing power to peripheral components associated with a personal computer is disclosed. A local power management unit is located at each controller for a peripheral component in order to provide a distributive power management arrangement. The local power management units communicate with an activity monitor provided in a central power management unit. The foregoing arrangement permits power to be maintained to the bus interface microchips at all times. Deactuation of a controller associated with a peripheral component is accomplished through inhibiting the clock signal produced by the local power management unit associated with the controller. By maintaining power to the bus interface microchips, power leakage through the bus interface microchips is eliminated.
摘要翻译：公开了一种用于向与个人计算机相关联的外围组件提供电力的系统。本地电源管理单元位于用于外围组件的每个控制器上，以便提供分布式电源管理装置。本地电源管理单元与中央电源管理单元中提供的活动监视器进行通信。上述布置允许在总线上将功率保持到总线接口微芯片。通过禁止与控制器相关联的本地电力管理单元产生的时钟信号来实现与外围组件相关联的控制器的去激活。通过维持总线接口微芯片的电源，消除了通过总线接口微芯片的电力泄漏。

2. 发明授权

US5410662A Programmable control of EMS page register addresses 失效
标题翻译： EMS页寄存器地址的可编程控制
公开(公告)号：US5410662A
公开(公告)日：1995-04-25
申请号：US802075
申请日：1991-12-03
申请人： William K. Hilton , James B. Nolan , Walter H. Potts
发明人： William K. Hilton , James B. Nolan , Walter H. Potts
IPC分类号： G06F9/30 , G06F9/318 , G06F9/355 , G06F12/06 , G06F12/02 , G06F12/00
CPC分类号： G06F12/0623 , G06F9/30098 , G06F9/30138
摘要： A full set of 36 EMS registers is provided for a computer, without using any of the registers located in the 256K to 640K address range of the standard RAM. This is accomplished by providing first and second alternate RAM sets of 12 registers each, which are accessed in the same 768K to 960K space as the standard twelve registers located in the 768K to 960K space. Access to the 24 registers in the first and second alternate sets of registers is controlled by two control bits. These bits translate address signals directed to the 768K to 960K space to be directed to one or the other of the first and second alternate sets of 12 registers; so that the alternate registers are accessed in the same space as the standard 12 registers in this 768K to 960K space.
摘要翻译：为计算机提供了一整套36个EMS寄存器，而不使用位于标准RAM 256K至640K地址范围内的寄存器。这是通过提供每个12个寄存器的第一和第二备用RAM组来实现的，这些寄存器在与768K至960K空间中的标准十二个寄存器相同的768K至960K空间中被访问。访问第一和第二备用寄存器组中的24个寄存器由两个控制位控制。这些位将指向768K至960K空间的地址信号转换为12个寄存器的第一和第二替代集合中的一个或另一个; 以便在768K至960K的空间中，与标准12寄存器相同的空间访问备用寄存器。

3. 发明授权

US5392252A Programmable memory addressing 失效
标题翻译：可编程存储器寻址
公开(公告)号：US5392252A
公开(公告)日：1995-02-21
申请号：US612293
申请日：1990-11-13
申请人： Charles R. Rimpo , Walter H. Potts , Joe A. Thomsen , Mitch A. Stones
发明人： Charles R. Rimpo , Walter H. Potts , Joe A. Thomsen , Mitch A. Stones
IPC分类号： G11C8/12 , G11C11/4076 , G11C11/408 , G11C8/00
CPC分类号： G11C8/12 , G11C11/4076 , G11C11/408
摘要： A software programmable memory addressing system operates with multiple banks of DRAM chips. The DRAM chips in the different banks may be of different sizes and may be located physically in arrangements where the largest memory chips are not necessarily placed in the first memory bank. The system permits 256K, 1M, and 4M DRAMs to be supported separately, and in combinations of any two of the three types. An internal DRAM controller generates row address strobes (RAS) and column address strobes (CAS) which are supplied to a multiplexer switch bank for routing the RAS and CAS strobes to the physical DRAM banks according to a program set in a register used to control the operation of the multiplexers. Consequently, internally generated logical RAS and CAS signals are routed to the appropriate physical banks of DRAM to create a valid memory map, without requiring the physical arrangement of the banks of DRAMs in a pre-established order.
摘要翻译：软件可编程存储器寻址系统与多组DRAM芯片一起工作。不同库中的DRAM芯片可以具有不同的尺寸，并且可以物理地定位在最大存储器芯片不一定放置在第一存储体中的布置中。该系统允许单独支持256K，1M和4M DRAM，并结合三种类型中的任何两种。内部DRAM控制器产生行地址选通（RAS）和列地址选通（CAS），其提供给多路复用器开关组，用于根据用于控制的RAM的寄存器中设置的程序将RAS和CAS选通路由到物理DRAM组多路复用器的操作。因此，内部产生的逻辑RAS和CAS信号被路由到DRAM的适当的物理组，以创建有效的存储器映射，而不需要预先建立的顺序的DRAM组的物理布置。

4. 发明授权

US5793990A Multiplex address/data bus with multiplex system controller and method therefor 失效
标题翻译：具有多路复用系统控制器的多路复用地址/数据总线及其方法
公开(公告)号：US5793990A
公开(公告)日：1998-08-11
申请号：US76876
申请日：1993-06-11
申请人： James J. Jirgal , David R. Evoy , Walter H. Potts
发明人： James J. Jirgal , David R. Evoy , Walter H. Potts
IPC分类号： G06F13/362 , G06F3/00
CPC分类号： G06F13/362
摘要： A computer system having a multiplex address/data bus with a multiplex system controller and method therefor is disclosed which provides in a computer system having time shared use of a multiplex address/data bus to reduce the number of required pins for devices within the computer system, a CPU having at least one address bus, at least one data bus, at least one memory input/output, and at least one CPU control bus coupled thereto for sending and receiving information. In addition, this system includes at least one memory input/output device coupled to a first portion of the address bus for sending and receiving at least one of address information and data information, at least one input/output only device coupled to a second portion of the address bus for sending and receiving at least one of address information and data information, and a multiplex system controller coupled to the CPU and the address bus and having a multiplex control bus coupled to both the memory input/output device and to the input/output only device for taking control of the address bus from the CPU.
摘要翻译：公开了一种具有多路复用地址/数据总线与多路复用系统控制器及其方法的计算机系统，其在计算机系统中提供具有多路复用地址/数据总线的时间共享使用以减少计算机系统内的设备的所需引脚数，具有至少一个地址总线的CPU，至少一个数据总线，至少一个存储器输入/输出以及耦合到其上的至少一个CPU控制总线，用于发送和接收信息。此外，该系统包括耦合到地址总线的第一部分的至少一个存储器输入/输出设备，用于发送和接收地址信息和数据信息中的至少一个，耦合到第二部分的至少一个输入/输出设备用于发送和接收地址信息和数据信息中的至少一个的地址总线，以及耦合到CPU和地址总线并具有耦合到存储器输入/输出设备和输入的多路复用控制总线的多路复用系统控制器 /仅用于从CPU控制地址总线的设备。

5. 发明授权

US5280587A Computer system in which a bus controller varies data transfer rate over a bus based on a value of a subset of address bits and on a stored value 失效
标题翻译：计算机系统，其中总线控制器基于地址位的子集的值和存储的值在总线上改变数据传输速率
公开(公告)号：US5280587A
公开(公告)日：1994-01-18
申请号：US860962
申请日：1992-03-31
申请人： Ataru Shimodaira , Walter H. Potts
发明人： Ataru Shimodaira , Walter H. Potts
IPC分类号： G06F13/28 , G06F13/42 , G06F13/00
CPC分类号： G06F13/28 , G06F13/423
摘要： A computer system includes a bus and a plurality of devices coupled to the bus. A CPU within the bus controller generates addresses for data transfers to and from the devices. A bus controller generates control signals for the data transfers. A data transfer rate controlled by the control signals is varied so that the data transfer rate is optimal for data transfers to and from each device. The data transfer rate for a data transfer to or from a first device is based on a subset of address bits used by the CPU to address the first device.
摘要翻译：计算机系统包括总线和耦合到总线的多个设备。总线控制器内的一个CPU产生用于从设备传出数据的地址。总线控制器产生用于数据传输的控制信号。由控制信号控制的数据传输速率是变化的，使得数据传输速率对于从每个设备传送到每个设备的数据传输速率是最佳的。用于向第一设备传输数据或从第一设备传输数据的数据传输速率基于由CPU用于寻址第一设备的地址位的子集。

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