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1. 发明授权

US5224125A Digital signed phase-to-frequency converter for very high frequency phase locked loops 失效
标题翻译：数字签名相位频率转换器，用于非常高频率的相位锁
公开(公告)号：US5224125A
公开(公告)日：1993-06-29
申请号：US681095
申请日：1991-04-05
申请人： Hee Wong , Tsun-Kit Chin
发明人： Hee Wong , Tsun-Kit Chin
IPC分类号： H03L7/06 , H03L7/08
CPC分类号： H03L7/08
摘要： A signed phase-to-frequency (`P-to-F`) converter for use in a very high frequency Phase Locked Loop is disclosed. The P-to-F converter receives an input signal indicating plus/minus phase errors and an enable signal. The input signal is converted into a count by a counting circuit. An upper part of the count signal is used to generate a 3-phase sawtooth digital pattern. A lower part of the count is converted by a lower-bit pulse density modulation (`PDM`) circuit to generate a signal indicating the binary weight of the lower part of the count. The output of the lower-bit PDM circuit is applied, along with the 3-phase digital pattern, to three higher-bit PDM circuits. The carry output of the higher-bit PDM circuits is the digital output of the P-to-F converter and is converted from a digital to an analog signal by RC filters. The positive and negative phase error is indicated by the leading/lagging phase among the 3-phase output waveforms.

2. 发明授权

US5351275A Digital serial loop filter for high speed control systems 失效
标题翻译：用于高速控制系统的数字串行环路滤波器
公开(公告)号：US5351275A
公开(公告)日：1994-09-27
申请号：US729973
申请日：1991-07-15
申请人： Hee Wong , Tsun-Kit Chin
发明人： Hee Wong , Tsun-Kit Chin
IPC分类号： H03L7/06 , H03H17/02 , H03L7/093 , H03L7/099 , H03D3/24
CPC分类号： H03L7/093 , H03L7/0991 , H03L2207/04
摘要： A digital programmable loop filter for high frequency control systems applications utilizing a serial processing technique on pulse densities. The loop filter contains a proportional signal path and an integral signal path. A 4-time-slot sequencer time-multiplexes the serial proportional and integral signals to emulate a 1-pole/1-zero filter. An acquisition speed control circuit controls the acquisition time as well as step sizes of the scaler (proportional path) and the integrator (integral path) to provide loop variable programmability.
摘要翻译：一种用于高频控制系统应用的数字可编程环路滤波器，利用脉冲密度的串行处理技术。环路滤波器包含比例信号路径和积分信号路径。 4时隙定序器对串行比例和积分信号进行时间复用，以模拟1极/ 1 - 零滤波器。采集速度控制电路控制采集时间以及缩放器（比例路径）和积分器（积分路径）的步长，以提供循环变量可编程性。

3. 发明授权

US5295079A Digital testing techniques for very high frequency phase-locked loops 失效
标题翻译：用于非常高频锁相环的数字测试技术
公开(公告)号：US5295079A
公开(公告)日：1994-03-15
申请号：US731963
申请日：1991-07-18
申请人： Hee Wong , Tsun-Kit Chin
发明人： Hee Wong , Tsun-Kit Chin
IPC分类号： G01R31/28 , H03L7/06 , H03L7/08 , H03L7/099 , G01R23/02
CPC分类号： H03L7/0991 , G01R31/282
摘要： A digital testing system providing for cost efficient comprehensive testing of very high frequency phase-locked loop performance parameters. The system tests PLL performance parameters both at integrated circuit level and communication board level. Cost efficiency of the testing system allows for volume testing by manufacturers.
摘要翻译：数字测试系统，提供高频锁相环性能参数的成本效益综合测试。该系统在集成电路级和通信板级测试PLL性能参数。测试系统的成本效率允许制造商进行批量测试。

4. 发明授权

US5239561A Phase error processor 失效
标题翻译：相位错误处理器
公开(公告)号：US5239561A
公开(公告)日：1993-08-24
申请号：US731138
申请日：1991-07-15
申请人： Hee Wong , Tsun-Kit Chin
发明人： Hee Wong , Tsun-Kit Chin
IPC分类号： H03L7/08 , H03L7/085 , H03L7/093 , H03L7/099 , H04L7/033
CPC分类号： H03L7/0991 , H03L7/085 , H04L7/033
摘要： A phase error processor interfaces a proportionate phase detector to a digital loop filter in a high frequency phase-locked loop (PLL). The PLL receives a high frequency stream of NRZI encoded data, which contains a variable density of data signal transitions. A phase detector in the PLL generates proportionate phase error information in the form of a phase error pulse signal PD1 and a reference pulse signal PD2 for each data transition in the incoming data s The phase error processor, using a "decimation" technique, integrates the proportionate phase error information from just one pair of adjacent positive and negative data transitions during each period of N clock cycles if the number of input data transitions which occur during that time period exceeds the expected minimum, otherwise the phase error processor passes no phase error information. The selection of window width is based on the coding scheme of the incoming data stream. The integrated information is converted by the phase error processor once during each N-clock cycle period into a one-bit Up/Down signal that is then used to either advance or retard the output phase of the PLL's digitally controlled oscillator. The phase error processor also detects when the density of edges in the incoming data stream falls below a minimum allowed level, and generates a "data valid" signal indicating whether the Up/Down signal are valid.

5. 发明授权

US5329559A Phase detector for very high frequency clock and data recovery circuits 失效
标题翻译：用于超高频时钟和数据恢复电路的相位检测器
公开(公告)号：US5329559A
公开(公告)日：1994-07-12
申请号：US26266
申请日：1993-03-04
申请人： Hee Wong , Tsun-Kit Chin
发明人： Hee Wong , Tsun-Kit Chin
IPC分类号： H03L7/08 , H03L7/085 , H03L7/099 , H04L7/033 , H03D3/20
CPC分类号： H03L7/085 , H03L7/0991 , H04L7/0025 , H04L7/033
摘要： A phase detector circuit, used in a very high frequency phase-locked loop, receives an incoming NRZI data stream and a phase-locked loop clock signal. For each data transition in the received data stream, the phase detector produces proportional phase error information in the form of two pulse signals PD1 and PD2. Pulse signal PD1 has a pulse width TW1 which corresponds to the amount and direction of any phase error between the data signal transition and the PLL clock signal. Pulse signal PD2 has a fixed width TW2 equal to half the period of the PLL clock signal. The phase detector also generates a recovered data signal and a recovered clock signal using identical parallel circuits so that the recovered signals are time synchronized. Furthermore, the recovered data signal is derived from signals in the phase error detection path, eliminating the need for two distinct circuits for data recovery and clock recovery. In the preferred embodiment, the pulse signals from one positive and one negative data transition are integrated or averaged so as to eliminate problems associated with any duty cycle distortion and/or jitter in the incoming data stream. The sign and magnitude of the difference in the widths of the averaged pulse signals are proportional to the average phase error between the incoming data signal and the PLL clock signal.
摘要翻译：在非常高频的锁相环中使用的相位检测器电路接收输入的NRZI数据流和锁相环时钟信号。对于接收数据流中的每个数据转换，相位检测器以两个脉冲信号PD1和PD2的形式产生比例相位误差信息。脉冲信号PD1具有对应于数据信号转换和PLL时钟信号之间的任何相位误差的量和方向的脉冲宽度TW1。脉冲信号PD2具有等于PLL时钟信号的周期的一半的固定宽度TW2。相位检测器还使用相同的并行电路产生恢复的数据信号和恢复的时钟信号，使得恢复的信号是时间同步的。此外，恢复的数据信号从相位误差检测路径中的信号导出，消除了对用于数据恢复和时钟恢复的两个不同电路的需要。在优选实施例中，来自一个正数据和一个负数据转换的脉冲信号被积分或平均，以消除与输入数据流中的任何占空比失真和/或抖动相关的问题。平均脉冲信号的宽度差的符号和幅度与输入数据信号和PLL时钟信号之间的平均相位误差成比例。

6. 发明授权

US5132633A PLL using a multi-phase frequency correction circuit in place of a VCO 失效
标题翻译： PLL使用多相频率校正电路代替VCO
公开(公告)号：US5132633A
公开(公告)日：1992-07-21
申请号：US703404
申请日：1991-05-21
申请人： Hee Wong , Tsun-Kit Chin
发明人： Hee Wong , Tsun-Kit Chin
IPC分类号： H03B21/00 , H03L7/099 , H03L7/16
CPC分类号： H03L7/16 , H03B21/00 , H03L7/0995
摘要： A phase-locked loop generates a periodic clock signal which matches the frequency of an input signal, such as digital data signals transmitted over an optical fiber. A ring oscillator or other clock generator generates a 2N-phase reference clock signal with a reference frequency f.sub.0, where N is a positive, odd integer having a value of at least three. The 2N reference clock phasor signals have evenly distributed phases. A waveform generator generates a 2N-phase control signal having a frequency .vertline.f.sub.M .vertline. which corresponds to the difference between the input signal's frequency and the reference frequency f.sub.0. The value of f.sub.M is greater than zero when the input signal's frequency is higher than f.sub.0, and it is less than zero when the input signal's frequency is less than f.sub.O. A frequency correction circuit (FCC) generates an output clock signal havng an output frequency which is equal to f.sub.0 +f.sub.M. The frequency correction circuit modulates each reference phasor signal with a corresponding one of the 2N control phasor signals, and then combines the result modulated reference phasor signals to generate the output clock signal. A phase detector continually compares the output frequency with the input signals's frequency, and adjusts the frequency f.sub.M of the 2N control phasor signals so that the output frequency closely matches the input frequency. Typically, the reference frequency differs from the input frequency by no more than a factor of one in a thousand.

7. 发明授权

US07979483B1 Multiplexed proportional-integral-derivative filter architecture (Mux-PID) for control-loop applications 有权
标题翻译：用于控制环应用的多路比例积分微分滤波器架构（Mux-PID）
公开(公告)号：US07979483B1
公开(公告)日：2011-07-12
申请号：US11506189
申请日：2006-08-16
申请人： Hee Wong
发明人： Hee Wong
IPC分类号： G06F17/10
CPC分类号： G05B11/42
摘要： A multiplexed digital proportional-integral-derivative filter receives error signal samples and operates in different states during sub-cycles of a single system cycle. A single multiplier and a single adder within the filter calculate at least portions of a proportional control signal, an integral control signal and a derivative control signal for one error signal sample during successive sub-cycles. The calculated control signal portions are aggregated to produce a filtered error signal for the respective error signal sample. The original resolution at lower cost, or increased resolution at the original cost, are achieved, as well as full programmability of loop gain with only negligible increase in loop latency.
摘要翻译：复用的数字比例积分微分滤波器接收误差信号采样并在单个系统周期的子周期期间以不同的状态操作。滤波器内的单个乘法器和单个加法器在连续的子周期期间计算一个误差信号采样的比例控制信号，积分控制信号和微分控制信号的至少一部分。所计算的控制信号部分被聚合以产生用于相应误差信号样本的滤波误差信号。以较低的成本或原始成本提高分辨率的原始分辨率，以及环路增益的全面可编程性，环路延迟增加可忽略不计。

8. 发明授权

US07930334B1 Gain control coding within proportional-integral-derivative filters for control-loop applications 有权
标题翻译：用于控制环应用的比例积分微分滤波器内的增益控制编码
公开(公告)号：US07930334B1
公开(公告)日：2011-04-19
申请号：US11731962
申请日：2007-04-02
申请人： Hee Wong
发明人： Hee Wong
IPC分类号： G06F17/10
CPC分类号： G05B11/42
摘要： Proportional, integral and derivative error gains within a proportional-integral-derivative filter are selected based on a magnitude of the error value and with successively higher gain values corresponding to larger ranges of error values. Coding of the error gains is selected based on one or more of: large code-dynamic-range to achieve good transient and quiescent responses; small code-step ratio to achieve smooth transitions between consecutive steps; large gain control range to satisfy the differing gain coverage requirements of the three proportional, integral and derivative error; positive and negative code symmetry with small step increment about zero; reservation of code space for dead band elimination; allocation of code space to prevent overflow/underflow during multiplying and bit-shifting; and minimum cost and power.
摘要翻译：基于比例积分微分滤波器中的比例积分和微分误差增益是基于误差值的大小以及对应于较大范围误差值的连续较高增益值来选择的。基于以下一个或多个选择误差增益的编码：大代码 - 动态范围以实现良好的瞬态和静态响应; 小代码步长比实现连续步骤之间的平滑过渡; 大增益控制范围满足三种比例，积分和微分误差的不同增益覆盖要求; 正，负码对称，小步增量约零; 预留死区消除代码空间; 分配代码空间，以防止在乘法和位移期间的溢出/下溢; 最低成本和最低功耗。

9. 发明授权

US07227476B1 Dither scheme using pulse-density modulation (dither PDM) 有权
标题翻译：使用脉冲密度调制（抖动PDM）的抖动方案
公开(公告)号：US07227476B1
公开(公告)日：2007-06-05
申请号：US11204297
申请日：2005-08-14
申请人： Hee Wong
发明人： Hee Wong
IPC分类号： H03M5/08
CPC分类号： H03M5/08
摘要： Dithering for the output of a digital pulse width modulator is provided by a pulse-density modulator formed from an adder incrementing a pulse-density count and generating a carry signal latched to a plus-one generator, which in turn adds a phase-division period to each of one or more selected pulses within a predetermined series of pulses from the digital pulse width modulator. Selected pulses are advanced by triggering a leading edge of the pulse at a time one phase-division period before the system clock edge, allowing trailing edges to be extended and providing minimal latency delay.
摘要翻译：用于数字脉宽调制器输出的抖动由脉冲浓度调制器提供，该脉冲密度调制器由加法器增加脉冲密度计数器并产生锁存到一加法器的进位信号，进位信号又增加一个相位分割周期到来自数字脉冲宽度调制器的预定的一系列脉冲内的一个或多个所选脉冲中的每一个。通过在系统时钟边沿之前的一个相位分割周期的时间触发脉冲的前沿，允许后沿被延长并且提供最小的等待时间延迟，所选脉冲被提前。

10. 发明授权

US06839551B1 Radio frequency mixer and method of operation 有权
标题翻译：射频混频器及操作方法
公开(公告)号：US06839551B1
公开(公告)日：2005-01-04
申请号：US09862048
申请日：2001-05-21
申请人： Hee Wong
发明人： Hee Wong
IPC分类号： H03D7/16 , H04B1/26 , H04B15/00
CPC分类号： H03D7/161
摘要： There is disclosed a radio frequency (RF) demodulation circuit comprising: 1) a first RF mixer having a first input port for receiving an in-phase RF signal having a frequency of RF and a second input port for receiving an in-phase local oscillator (LO) signal having a frequency of LO, wherein LO is approximately equal to one-half of RF, and wherein the first RF mixer generates a first intermediate frequency (IF) signal having a frequency of LO; 2) a second RF mixer having a first input port for receiving an out-of-phase RF signal having a frequency of RF and a second input port for receiving an out-of-phase local oscillator (LO) signal having a frequency of LO, and wherein the second RF mixer generates a second intermediate frequency (IF) signal having a frequency of LO; and 3) a first signal combiner for combining the first and second IF signals to generate a composite IF signal, wherein the first signal combiner combines a first leakage signal from the first RF mixer and a second leakage signal from the second RF mixer such that the first and second leakage signals at least partially cancel each other to produce an output leakage signal that is less than either of the first and second leakage signals.
摘要翻译：公开了一种射频（RF）解调电路，包括：1）第一RF混频器，具有用于接收具有RF频率的同相RF信号的第一输入端口和用于接收同相本机振荡器的第二输入端口（LO）信号，其中LO大约等于RF的一半，并且其中第一RF混频器产生具有LO频率的第一中频（IF）信号; 2）具有用于接收具有RF频率的异相RF信号的第一输入端口和用于接收具有频率为LO的异相本地振荡器（LO））信号的第二输入端口的第二RF混频器，，并且其中所述第二RF混频器产生具有LO频率的第二中频（IF）信号; 以及3）第一信号组合器，用于组合第一和第二IF信号以产生复合IF信号，其中第一信号组合器组合来自第一RF混频器的第一泄漏信号和来自第二RF混频器的第二泄漏信号，使得第一和第二泄漏信号至少部分地彼此抵消以产生小于第一和第二泄漏信号中的任一个的输出泄漏信号。

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